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    							FUJITSU SEMICONDUCTOR LIMITED 
Chapter: External Interrupt and NMI Control Sections 
This chapter explains the functions and operations of the external interrupt and NMI control 
sections. 
 
1. Overview 
2. Block Diagram 
3. Operations and Setting Procedure Examples 
4. Registers 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 CODE: 9BFEXTINT-E02.1_FW12-J1.03 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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1. Overview 
The external interrupt and NMI control sections have the following features. 
  Has up to 16 external interrupt input pins and one NMI input pin mounted. 
   Possible to select the H level, L level, rising ed ge, or falling edge to detect an external interrupt. 
   Possible to use an external interrupt input or NMI input to return from standby mode. 
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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2. Block Diagram 
The following shows the block diagram of the external interrupt and NMI control sections. 
Figure 2-1 Block diagram of external interrupt and NMI control sections 
Level detectionNormal: Falling edgeStop release: L levelCause F/F
NMIRRNon Maskable Interrupt Cause Request 
Register
NMICLNon Maskable Interrupt Cause Clear 
Register
NMIIRQ
NMIX
Level 
detectionCause F/FEN gate
EIRR
External Interrupt Cause Register
ENIR
Enable Interrupt Request Register INTIRQxx
INTxx
ELVR
External Interrupt Level Register 
EICL
External Interrupt Cause Clear Register
APB-BUS
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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3.  Operations and Setting Procedure Examples 
This section explains operations and setting procedure examples. 
 
3.1 Operations of external interrupt control section  
3.2  Operations of NMI control section 
 
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3.1.  Operations of external interrupt control section 
 Overview of operations in ext ernal interrupt control section 
The external interrupt control section outputs an extern al interrupt request to the interrupt controller in the 
following procedure. 
1.  The signal input to pin INTxx detects the edge or leve l specified in the External Interrupt Level Register 
(ELVR). The edge or level to be detected can be selected from the following four types: 
H level, L level, rising edge, falling edge 
2.  The detected interrupt input is held in the interrupt cause F/F. 
It is read with the External Interrupt Request Register (EIRR). 
The held interrupt cause is cleared with th e External Interrupt Clear Register (EICL). 
3.  If an external interrupt is enabled with the Enable Interrupt Request Register (ENIR), an external 
interrupt request (INTIRQxx) is ou tput to the interrupt controller. 
 Setting procedure 
Execute the following steps to conf igure external interrupt setting. 
1.  Disable an external interrupt with the Enable Interrupt Request Register (ENIR). 
2.  Specify the detection condition (effective edge or level) with the External Interrupt Level Register 
(ELVR). 
3.  Read the External Interrupt Level Register (ELVR). 
4.  Clear the external interrupt cause with the  External Interrupt Clear Register (EICL). 
5.  Enable the external interrupt with the Enable Interrupt Request Register (ENIR). 
 
Figure 3-1 External interrupt setting procedure 
Disables an external interrupt. (ENIR)
Specifies the detection condition.
(ELVR)
Checks the detec tion condition.
(ELVR)
Clears an interrupt cause.
(EICL)
Enables an external interrupt. (ENIR)
Starts setting.
Completes setting.
 
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 Canceling an external interrupt request 
When the external interrupt detection condition is set to  the H or L level, an interrupt cause is held in 
the External Interrupt Request Register (EIRR) even  if an external interrupt request input (INTxx) is 
canceled. Therefore, an exte rnal interrupt request (INTIRQxx) remains output to the interrupt controller. 
Execute the following steps to cancel  an external interrupt request. 
1.  Read the External Interrupt Request Regist er (EIRR), and check the interrupt cause. 
2.  Write 0 to the corresponding bit in the External Interrupt Clear Register (EICL) to clear it. 
3.  Read the External Interrupt Request Register (EI RR), and check that the interrupt cause is cleared. 
 
Figure 3-2 Clearing an interrupt cause 
 
H
Outputs an interrupt request.
INTIRQxx Inputs an interrupt request.
INTxxWhen H level detection is specified
Canceled when 0 is written to EICL.
 
 
Figure 3-3 Canceling an external interrupt request 
Checks an interrupt cause.
(EIRR)
Clears an interrupt cause.(EICL)
Checks that an interrupt is cleared .
(EIRR)
Starts clearing.
Completes clearing.
 
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3.2.  Operations of NMI control section 
 Overview of NMI control section 
The NMI control section outputs an NMI interrupt reque st (NMIIRQ) to the CPU if the edge or level is 
detected from the signal input to the NMI input pin (NMIX). The following edge or level is detected. 
   Normal mode  :  Falling edge 
   Stop mode  :  L level 
 Canceling an NMI request 
To cancel an NMI request, clear the  request register in the same way as for an external interrupt request. 
Execute the following steps to cancel an NMI request. 
1.  Read the NMI Request Register (NMIRR ), and check the interrupt cause. 
2.  Write 0 to the corresponding bit in the NMI Clear Register (NMICL) to clear it. 
3.  Read the NMI Request Register (NMIRR), and  check that the interrupt cause is cleared. 
 
Figure 3-4 Canceling an NMI request 
Checks an interrupt cause. (NMIRR)
Clears an interrupt cause.
(NMICL)
Checks that an interrupt is cleared .
(NMIRR)
Starts clearing.
Completes clearing.
 
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3.3.  Returning from timer or stop mode 
 Overview 
An external interrupt and NMI requests can be used to return from timer or stop mode. 
In timer or stop mode, the signal first input to pin INTxx or NMIX is input asynchronously, and the device 
can return from timer or stop mode. 
  Setting before changing to stop mode 
To use an external interrupt request, in the Enable In terrupt Request Register (ENIR), specify the pin used 
to return from stop mode and also specify the effective detection level before changing to stop mode. 
   Pin used to return from stop mode.  :  Interrupt request output enable (ENIR = 1) 
   Pin not used to return from stop mode.  :  Interrupt request output disable (ENIR = 0) 
 
To use an NMI request, only the L level is detected, and no register setting is required. 
  Returning from stop mode 
For external interrupt request, if the pre-specified effective level is detect ed in the pin used to return from 
stop mode, the device returns from stop mode. 
For NMI request, if the L level is detected  in stop mode, the device returns from stop mode. 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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 Notes on returning from stop mode 
Any other external interrupt requests cannot be recognized until the oscillation stabilization wait time lapses 
after stop mode was released. 
(For INT01 in Figure 3-5 , any external interrupt requests cannot be recognized.) 
Th erefore, to i
n

put an external interrupt after stop mode  was released, input an external interrupt signal after 
the oscillation stabilization wait time lapsed. 
Figure 3-5 Returning from stop mode 
STOP
INT01
Internal stop
INT00
Internal operation
(RUN)
X0
Peripheral clock (PCLK)
External Interrupt Cause Register ER0
External Interrupt Cause Register ER1
The oscillation stabilization wait timeRUN
1 (Set to Enable before changing to stop mode .)
1 (Set to Enable before changing to stop mode .)
Clears the external interrupt 
request flag.
Executes the instruction (run).
Enable Interrupt Request Register
EN0
Enable Interrupt Request Register EN1
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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4. Registers 
This section provides a list of registers. 
 Register list 
The following shows a list of registers in the  external interrupt and NMI control sections. 
Table 4-1 Registers in external interrupt and NMI control sections 
Abbreviation Register name See 
ENIR  Enable Interrupt Request Register  4.1 
EIRR External Interrupt Request Register  4.2 
EICL External Interrupt Clear Register  4.3 
ELVR External Interrupt Level Register    4.4 
NMIRR Non Maskable Interrupt Request Register  4.5 
NMICL Non Maskable Interrupt Clear Register  4.6 
 
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