Fujitsu Series 3 Manual
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3. USB host operations Figure 3-4 SOF timing 1ms Start of SOF Start of SOF EOF setting time EOF setting time EOF > 1-packet time FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1145 MB9Axxx/MB9Bxxx Series
3. USB host operations 3.4. Data packet When sending a data packet after a token packet, transfer toggle data based on the value of the TGGL bit of the Host Token Endpoint Register (HTOKEN). Further, send endpoint 1 or 2 buffer data, CRC16 data, and EOP depending on the value of the DIR bit of the EP1 Control Register (EP1C). When receiving a data packet, compare the value of the TGGL bit of the Host Token Endpoint Register (HTOKEN) with the received toggle data. If they match, the received data is distributed to the endpoint 1 or 2 buffer depending on the value of the DIR bit of the EP1 Control Register (EP1C) to verify whether or not a CRC16 error occurs. Data packet Take the following steps to send or receive a data packet after sending a token packet. 1. For sending Automatically send Sync. If the TGGL bit of the Host Token Endpoint Register (HTOKEN) is 0, send DATA0. If the TGGL bit is 1, send DATA1. If the DIR bit of the EP1 Control Register (EP1C) is 1, select the endpoint 1 buffer. If the DIR bit of the EP1 Control Register (EPIC) is 0, select the endpoint 2 buffer. Then, send all the target data. Send a 16-bit CRC. Send a 2-bit EOP. Send a 1-bit J State. 2. For receiving Receive Sync. Receive toggle data, and compare it with the value of the TGGL bit of the Host Token Endpoint Register (HTOKEN). If the toggle data matches the value of the TGGL b it, check the DIR bit of the EP1 Control Register (EP1C). If the DIR bit is 1, select the endpoint 2 buffer. If the DIR bit of the EP1 Control Register (EP1C) is 0, select the endpoint 1 buffer. Then, distribute th e received data to the respective buffers. Verify the 16-bit CRC when EOF is received. When the HOST bit of Host Control Register 0 (HCNT0) is 1, set the inverted value to the respective DIR bits of the EP1 Control Register (EP1C) and EP2 Contro l Register (EP2C). For example, if 0 is set to the DIR bit of the EP1 Control Register (EP1C), set 1 to the DIR bit of the EP2 Control Register (EP2C). FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1146 MB9Axxx/MB9Bxxx Series
3. USB host operations 3.5. Handshake packet A handshake packet is used to notify the remote device of the status of the local device. Handshake packet A handshake packet sends either one of ACK, NAK, and STALL from the receiving side when it is judged that the receiving side is ready to receive data norm ally. If the USB circuit receives a handshake packet, the type of the received handshake packet is set to the HS bit of the Host Error Status Register (HERR). If the USB circuit sends a handshake packet, the type of the sent handshake packet is set to the HS bit of the Host Error Status Register (HERR). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1147 MB9Axxx/MB9Bxxx Series
3. USB host operations 3.6. Retry function When a NAK or CRC error occurs at the end of a packet, if 1 is set to the RETRY bit of Host Control Register 1 (HCNT1), processing is retr ied repeatedly for the period specified in the Retry T imer Setting Register (HRTIMER). Retry function When an error* other than STALL or device disconnection occurs, the target token is retried if the RETRY bit of Host Control Register 1 (HCNT1) is 1. The following shows the conditions to end retry processing. * : HERR.HS=01, HERR.RERR=1, HERR.T OUT=1, HERR.TOUT=1, HERR.CRC=1, HERR.STUFF=1 The RETRY bit of Host Control Register 1 (HCNT1) is set to 0. 0 is detected in the retry timer. The interrupt flag is generated by SOF (SOFIRQ of HIRQ = 1). ACK is detected. A device disconnection is detected. The retry timer is activated at start of a token, and count ed down by a 1-bit transfer clock. If retry occurs in the EOF area, counting stops. If a SOF token is ende d while the SOFIRQ bit of HIRQ is 0, counting restarts from the timer value that is set when counting stopped. When the retry timer is set to 0, a packet is ended, and the CMPIRQ bit of the Host In terrupt Register (HIRQ) is set to 1. Figure 3-5 Retry timer operation (SOFIRQ of HIRQ = 0) Start of token EOF SOF Retry Token sending Timer Count Down Timer Stop Timer Restart Retry occurrence When retry processing is ended, end information of the EOP is set to each register. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1148 MB9Axxx/MB9Bxxx Series
3. USB host operations 3.7. SOF interrupt The SOFIRQ bit of the Host Interrupt Register (HIRQ) is set to 1 at start of SOF depending on the setting of the SOFSTEP bit of Host Control Register 1 (HCNT1) and SOF Interrupt Frame Compare Register (HFCOMP). If the SOFIRE bit of Host Control Register 0 (HCNT0) is 1, an int errupt occurs. When SOF processing is executed using the Host Token Endpoint Register (HTOKEN), the SOFIRQ bit of the Host Interrupt Register (HIRQ) is not set to 1. SOF interrupt When the SOFSTEP bit of Host Control Register 1 (H CNT1) is 0, the value of the SOF Interrupt Frame Compare Register (HFCOMP) is comp ared with the low-order eight bits of the frame number for SOF token. If they match, 1 is set to the SOFIRQ bit of the Host Interrupt Register (HIRQ) when sending SOF. When the SOFSTEP bit of Host Control Register 1 (HCN T1) is 1, 1 is set to the SOFIRQ bit of the Host Interrupt Register (HIR Q) each time SOF is sent. 1. When the SOFSTEP bit of Host Control Register 1 (HCNT1) is 1: Send SOF.Send the next SOF. SOFIRQ bit of HIRQ Clear software. Clear software. 2. When the SOFSTEP bit of Host Control Register 1 (HCNT1) is 0: Send SOF. Send the next SOF. HFRAME (010)h (011)h HFCOMP(011)h SOFIRQ bit of HIRQ The low-order eight bits of HFRAME matches the value of HFCOMP. If 1 is set to the CANSEL bit of Host Control Register 1 (HCNT1), the target token is not sent when it is set at the following timing. A token other than SOF is set to the Host Toke n Endpoint Register (HTOKEN) in the EOF area. If a token is set at this timing, the following operations are carried out. If the SOFIRQ bit of the Host Interrupt Register (HIR Q) is set to 1 when the next SOF is sent, the TKNEN bit of the Host Token Endpoint Register (HTOKEN) is cleared to 0b000. In this case, that token is not sent. The TKNEN bit of the Host Token Endpoint Register (HTOKEN) is cleared at the following timing. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1149 MB9Axxx/MB9Bxxx Series
3. USB host operations At this timing, the CMPIRQ bit of the Host Interrupt Register (HIRQ) is not set to 1. When the SOFIRQ bit is set to 1, the TCAN bit of the Host Interrupt Register (HIRQ) indicates that a token is canceled. When retrying to send a token, write 0 to the TCAN bit of the Host Interrupt Register (HIRQ). Then write a token to be sent to the TKNEN bit of the Host Token Endpoint Register (HTOKEN). If 0 is set to the CANCEL bit of Host Control Register 1 (HCNT1), the token specified in the Host Token Endpoint Register (HTOKEN) is sent following SOF. Figure 3-6 Token cancellation example at CANCEL bit of HCNT1 = 1 Write IN token. EOF area Send SOF. SOFIRQ bit of HIRQ TKNEN bit of HTOKEN (000)b (010)b (000)b CMPIRQ bit of HIRQ TCAN bit of HIRQ 0 Figure 3-7 Token operation example at CANCEL bit of HCNT1 = 0 Write IN token. EOF area Send SOF. Send IN token. SOFIRQ bit of HIRQ TKNEN bit of HTOKEN (000)b (010)b (000)b CMPIRQ bit of HIRQ FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1150 MB9Axxx/MB9Bxxx Series
3. USB host operations 3.8. Error status The USB host supports error information. Error status 1. Stuffing Error If 1 is successively set to six bits, 0 is inserted into one bit. If 1 is successively detected in seven bits, it is judged to be Stuffing Error, and the STUFF bit of the Host Error Status Register (HERR) is set to 1. To clear this status, writ e 0 to the STUFF bit. If the next token is sent without clearing the STUFF bit, a cause is reflected on the STUFF bit when the next token is ended. 2. To g g l e E r r o r When sending an IN token, the toggle data of a data packet is compared with the value of the TGGL bit of the Host Token Endpoint Register (HTOKEN). If th ey do not match, the TGERR bit of the Host Error Register (HERR) is set to 1. To clear the TGERR bit, write 0 to the TGERR bit of the Host Error Register (HERR). If the next token is sent without clearing the TGERR bit, a cause is reflected on the TGERR bit when the next token is ended. 3. CRC Error When receiving an IN token, data and CRC of th e received data packet are obtained with the CRC polynomial G(X) = X16 + X15 + X2 + 1. If the remainder is not (800d)h, it means that CRC Error occurs, and the CRC bit of the Host Er ror Register (HERR) is set to 1. To clear the CRC bit, write 0 to the CRC bit of the Host Error Register (HERR). If the next token is sent without clearing the CRC bit, a cause is reflected on the CRC bit when the next token is ended. 4. Time Out Error 1 is set to the TOUT bit of the Host Error Status Register (HERR) when: A data packet or handshake packet has not been input in the specified time; SE0 has been detected during data receiving; or Stuffing Error has been detected. To clear the TOUT bit, write 0 to the TOUT bit of the Host Error Register (HERR). If the next token is sent without clearing the TOUT bit, a cause is reflected on the TOUT bit when the next token is ended. 5. Receive Error If EP1 is used as a receive buffer, the value of the PKS bit of the EP1 Control Register (EP1C) is used as the receive packet size. If EP2 is used as a receive buffer, the value of the PKS bit of the EP2 Control Register (EP2C) is used as the receive packet size. When the received data exceeds the specified receive packet size, the RERR bit of the Host Error Status Regi ster (HERR) is set to 1. To clear the RERR bit, write 0 to the RERR bit of the Host Error Register (HERR). If the next token is sent without clearing the RERR bit, a cause is reflected on the RERR bit when the next token is ended. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1151 MB9Axxx/MB9Bxxx Series
3. USB host operations 3.9. End of packet If one packet is ended in the USB host, the CMPIRQ bit of the Host Interrupt Register (HIRQ) is set to 1. At this time, if the CMPIRE bit of Host Control Register 0 (HCNT0) is 1, an interrupt occurs. Packet end timing When one packet ends, the interrupt flag is generated when: The TKNEN bit of the Host Token Endpoint Register (HTOKEN) is (001)b, (010)b, or (011)b (SETUP token, IN token, or OUT token). Figure 3-8 Timing example 1 when setting the CMPIRQ bit of the Host Interrupt Register (HIRQ) Write data to the TKNEN bit of HTOKEN. Token packet Data packet Handshake packet CMPIRQ bit (HIRQ) J-ST : J State TKN : Token ADR : Address ENDPT : Endpoint TGGL : Toggle J-ST Sync TKN ADR ENDP CRC5 EOP J-ST SyncTGGLDATA CRC16 EOP J-ST Sync ACK EOP J-ST The TKNEN bit of the Host Token Endpoint Register (HTOKEN) is (100)b (SOF token). Figure 3-9 Timing example 2 (SOF token) when setting the CMPIRQ bit of the Host Interrupt Register (HIRQ) Write data to the TKNEN bit of HTOKEN. J-ST Sync TKN FRAME CRC5 EOP J-ST CMPIRQ bit (HIRQ) J-ST : J State TKN : Token FRAME : Frame Number FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1152 MB9Axxx/MB9Bxxx Series
3. USB host operations 3.10. Suspend and resume operations The USB host supports suspend and resume operations. Suspend operation If 1 is set to the SUSP bit of the Host Status Register (HSTATE), the procedure below is performed, and the USB circuit is placed into the suspend state. The USB bus is placed in the high-impedance state. A circuit block with no clock required is stopped. If the USB circuit is placed in the suspend state, the SU SP bit of the Host Status Register (HSTATE) is set to 1. However, the following operations are prohibited while resetting the USB bus. 1 is set to the SOFBUSY bit of the Host Status Register (HSTATE) or the USB circuit is placed into the suspend state during data transfer. Clocks supplied to the USB are stopped in the suspend state. Take the following steps to stop clocks. 1. Change to the stop or timer mode. 2. Set the UCEN bit of the USB Clock Setup Register (UCCR) to 0. Resume operation The USB bus changes from the suspen d state to the resume state to resume processing when one of the following conditions is satisfied. 0 is set to the SUSP bit of the Host Status Register (HSTATE). The host pin D+ or D- is placed in the K-state mode. A device disconnection is detected. A device connection is detected. After the RWKIRQ bit of the Host Interrupt Register (H RQ) has been set to 1, a token can be issued. The following shows the operation timing for each condition. 0 is set to the SUSP bit of the Host Status Register (HSTATE). Figure 3-10 Resume operation with register (Full-speed mode) When the SUSP bit of HSTATE is 1, Write 0 to the SUSP bit of HSTATE. Host pin D+ 20ms *11.33ms*11-bit time RWKIRQ bit of HIRQ : Output from USB host : Drive by pull-up or pull-down resistor *1: Note that the numeric values above are not guaranteed. Host pin D- FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1153 MB9Axxx/MB9Bxxx Series
3. USB host operations The host pin D+ or D- is placed in the K-state mode. Figure 3-11 Resume operation by device (Full-speed mode) Host pin D+ Host pin D- 20ms *11.33ms*11-bit time RWIRQ bit of HIRQ : Output from USB host : Output from device : Drive by pull-up or pull-down resistor *1: Note that the numeric values above are not guaranteed. A device disconnection is detected. Figure 3-12 Resume operation by device disconnection Disconnection Host pin D+ Host pin D- RWKIRQ bit of HIRQ (RWKIRE=1) DIRQ bit of HIRQ (DIRE=1) Interrupt occurrence CSTAT bit of HSTATE 2.5s or more : Drive by pull-up or pull-down resistor FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1154 MB9Axxx/MB9Bxxx Series