Fujitsu Series 3 Manual
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![Page 516
9. Descriptions of base timer functions
Selection of count clock
The count clock of the counter can be selected from eight types by setting bit 8: CKS3 in the TMCR2
register and bit 14 to 12: CKS2, CKS1, and CKS0 in the TMCR register.
The selectable count clocks are as follows:
TMCR2 and TMCR registers
CKS3, CKS2, CKS1, and CKS0 bits Internal count clock to be selected
0b0000
Machine clock [Initial value]
0b0001 1/4 frequency of the machine clock
0b0010 1/16 frequency of the machine...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-515.png "Page 516
9. Descriptions of base timer functions
Selection of count clock
The count clock of the counter can be selected from eight types by setting bit 8: CKS3 in the TMCR2
register and bit 14 to 12: CKS2, CKS1, and CKS0 in the TMCR register.
The selectable count clocks are as follows:
TMCR2 and TMCR registers
CKS3, CKS2, CKS1, and CKS0 bits Internal count clock to be selected
0b0000
Machine clock [Initial value]
0b0001 1/4 frequency of the machine clock
0b0010 1/16 frequency of the machine...")
![Page 522
9. Descriptions of base timer functions
9.4.2. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PWC
timer is selected
The Timer Control Register (TMCR) controls timer operations.
Timer Control Register (H igh-order bytes of TMCR)
bit 15 14 13 12 11 10 9 8
Field res CKS2 CKS1 CKS0 res EGS2 EGS1 EGS0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 15] res: Reserved bit The read value is 0.
Set 0 to this bit....](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-521.png "Page 522
9. Descriptions of base timer functions
9.4.2. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PWC
timer is selected
The Timer Control Register (TMCR) controls timer operations.
Timer Control Register (H igh-order bytes of TMCR)
bit 15 14 13 12 11 10 9 8
Field res CKS2 CKS1 CKS0 res EGS2 EGS1 EGS0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 15] res: Reserved bit The read value is 0.
Set 0 to this bit....")
![Page 523
9. Descriptions of base timer functions
[bit 10:8] EGS2 to EGS0: Measurement edge selection bits These bit set measurement edge conditions.
Changes to EGS2, EGS1, or EGS0 must be made when the counting is stopped (CTEN = 0). However,
it is possible to make changes at the same time you set 1 to the CTEN bit.
Bit 10 Bit 9 Bit 8 Description
0 0 0 HIGH pulse width measurement ( ↑ to ↓)
0 0 1 Cycle measurement between rising edges ( ↑ to ↑)
0 1 0 Cycle measurement between falling...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-522.png "Page 523
9. Descriptions of base timer functions
[bit 10:8] EGS2 to EGS0: Measurement edge selection bits These bit set measurement edge conditions.
Changes to EGS2, EGS1, or EGS0 must be made when the counting is stopped (CTEN = 0). However,
it is possible to make changes at the same time you set 1 to the CTEN bit.
Bit 10 Bit 9 Bit 8 Description
0 0 0 HIGH pulse width measurement ( ↑ to ↓)
0 0 1 Cycle measurement between rising edges ( ↑ to ↑)
0 1 0 Cycle measurement between falling...")
![Page 524
9. Descriptions of base timer functions
Timer Control Register (L ow-order bytes of TMCR)
bit 7 6 5 4 3 2 1 0
Field T32 FMD2 FMD1 FM D0 res MDSE CTEN res
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] T32: 32-bit timer selection bit This bit selects the 32-bit timer function.
When the FMD2, FMD1, and FMD0 bits are set to 0b100 to select the PWC function, setting the T32
bit to 1 selects 32-bit PWC mode.
Changes must be made while the timer...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-523.png "Page 524
9. Descriptions of base timer functions
Timer Control Register (L ow-order bytes of TMCR)
bit 7 6 5 4 3 2 1 0
Field T32 FMD2 FMD1 FM D0 res MDSE CTEN res
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] T32: 32-bit timer selection bit This bit selects the 32-bit timer function.
When the FMD2, FMD1, and FMD0 bits are set to 0b100 to select the PWC function, setting the T32
bit to 1 selects 32-bit PWC mode.
Changes must be made while the timer...")
![Page 525
9. Descriptions of base timer functions
[bit 2] MDSE: Mode selection bit Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make
changes at the same time you set 1 to the CTEN bit.
Bit Description
0 Continuous measurement mode (Buffer register enabled)
1 One-shot measurement mode (Stops after one measurement)
[bit 1] CTEN: Timer enable bit This bit enables the start or restart of the up counter.
When the counter is in operation en abled status...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-524.png "Page 525
9. Descriptions of base timer functions
[bit 2] MDSE: Mode selection bit Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make
changes at the same time you set 1 to the CTEN bit.
Bit Description
0 Continuous measurement mode (Buffer register enabled)
1 One-shot measurement mode (Stops after one measurement)
[bit 1] CTEN: Timer enable bit This bit enables the start or restart of the up counter.
When the counter is in operation en abled status...")
![Page 526
9. Descriptions of base timer functions
Timer Control Register 2 (High-order bytes of TMCR2)
bit 15 14 13 12 11 10 9 8
Field res CKS3
Attribute R/W R/W
Initial value 0b0000000 0
Note: This register is placed above the STC register.
[bit 15:9] res: Reserved bits The read value is 0.
Set 0 to this bit.
[bit 8] CKS3: Count clock selection bit See Count clock selection bit in 9.4.2 Timer Control Register (High-order bytes of TMCR).
FUJITSU SEMICO NDUCTOR LIMITED
CHAPTER 14-2: Base...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-525.png "Page 526
9. Descriptions of base timer functions
Timer Control Register 2 (High-order bytes of TMCR2)
bit 15 14 13 12 11 10 9 8
Field res CKS3
Attribute R/W R/W
Initial value 0b0000000 0
Note: This register is placed above the STC register.
[bit 15:9] res: Reserved bits The read value is 0.
Set 0 to this bit.
[bit 8] CKS3: Count clock selection bit See Count clock selection bit in 9.4.2 Timer Control Register (High-order bytes of TMCR).
FUJITSU SEMICO NDUCTOR LIMITED
CHAPTER 14-2: Base...")
9. Descriptions of base timer functions Pulse width measurement operation flowchart Figure 9-19 Pulse width measurement operation flowchart PWC mode selection Count clock selection Operation/ measurement mode selection Interrupt flag clea r Interrupt enable Settings Start by the CTEN bit Clearing of the counter Restart One- shot measurement mode Continuous measurement mode Measurement start edge detection Measurement start edge detection Start of count operation Start of count operation Increment Increment Occurrence of an overflow OVIR flag setting Occurrence of an overflow OVIR flag settingMeasurement end edge detection EDIR flag setting Stop of count operation Stop of operation Stop of count operation Transfer of the count value to the DTBF Measurement end edge detection EDIR flag setting FUJITSU SEMICONDUCT OR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 485 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.4.2. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PWC timer is selected The Timer Control Register (TMCR) controls timer operations. Timer Control Register (H igh-order bytes of TMCR) bit 15 14 13 12 11 10 9 8 Field res CKS2 CKS1 CKS0 res EGS2 EGS1 EGS0 Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 [bit 15] res: Reserved bit The read value is 0. Set 0 to this bit. [bit 14:12, TMCR2: bit 8] CKS3 to CKS0: Count clock selection bit Select the count clock for the 16-bit down counter. Changes to the count clock setting are applied immediately. For this reason, changes to CKS3 through CKS0 must be made when the counting is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. CKS3 CKS2 CKS1 CKS0 Description 0 0 0 0 0 0 0 1 /4 0 0 1 0 /16 0 0 1 1 /128 0 1 0 0 /256 0 1 0 1 0 1 1 0 0 1 1 1 Setting disabled 1 0 0 0 /512 1 0 0 1 /1024 1 0 1 0 /2048 Others Setting disabled [bit 11] res: Reserved bit The read value is 0. Set 0 to this bit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 486 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions [bit 10:8] EGS2 to EGS0: Measurement edge selection bits These bit set measurement edge conditions. Changes to EGS2, EGS1, or EGS0 must be made when the counting is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. Bit 10 Bit 9 Bit 8 Description 0 0 0 HIGH pulse width measurement ( ↑ to ↓) 0 0 1 Cycle measurement between rising edges ( ↑ to ↑) 0 1 0 Cycle measurement between falling edges ( ↓ to ↓) 0 1 1 Pulse width measurement between all edges ( ↑ or ↓ to ↓ or ↑) 1 0 0 LOW pulse width measurement ( ↓ to ↑) 1 0 1 1 1 0 1 1 1 Setting disabled FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 487 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Timer Control Register (L ow-order bytes of TMCR) bit 7 6 5 4 3 2 1 0 Field T32 FMD2 FMD1 FM D0 res MDSE CTEN res Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 [bit 7] T32: 32-bit timer selection bit This bit selects the 32-bit timer function. When the FMD2, FMD1, and FMD0 bits are set to 0b100 to select the PWC function, setting the T32 bit to 1 selects 32-bit PWC mode. Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit (see 32-bit mode operations). Bit Description 0 16-bit timer mode 1 32-bit timer mode [bit 6:4] FMD2 to FMD0: Timer function selection bits These bits select the timer function. When the FMD2, FMD1, and FMD0 bits are set to 0b100, the PWC timer function is selected. Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. Bit 6 Bit 5Bit 4 Description 0 0 0 Reset mode 0 0 1 Selection of the PWM function 0 1 0 Selection of the PPG function 0 1 1 Selection of the reload timer function 1 0 0 Selection of the PWC function 1 0 1 1 1 0 1 1 1 Setting disabled [bit 3] res: Reserved bit The read value is 0. Set 0 to this bit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 488 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions [bit 2] MDSE: Mode selection bit Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. Bit Description 0 Continuous measurement mode (Buffer register enabled) 1 One-shot measurement mode (Stops after one measurement) [bit 1] CTEN: Timer enable bit This bit enables the start or restart of the up counter. When the counter is in operation en abled status (the CTEN bit is 1), writing 1 restarts the counter. The counter is cleared and waits for a measurement start edge. When the counter is in operation en abled status (the CTEN bit is 1), writing 0 to this bit stops the counter. Bit Description 0 Stop 1 Operation enabled [bit 0] res: Reserved bit The read value is 0. Set 0 to this bit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 489 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Timer Control Register 2 (High-order bytes of TMCR2) bit 15 14 13 12 11 10 9 8 Field res CKS3 Attribute R/W R/W Initial value 0b0000000 0 Note: This register is placed above the STC register. [bit 15:9] res: Reserved bits The read value is 0. Set 0 to this bit. [bit 8] CKS3: Count clock selection bit See Count clock selection bit in 9.4.2 Timer Control Register (High-order bytes of TMCR). FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 490 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Status Control Register (STC) bit 7 6 5 4 3 2 1 0 Field ERR EDIE res OVIE res EDIR res OVIR Attribute R R/W R/W R/W R/W R R/W R/W Initial value 0 0 0 0 0 0 0 0 Note: The TMCR2 register is placed in the upper bytes of this register. [bit 7] ERR: Error flag bit This flag indicates that the next measurement has been completed in continuous measurement mode before the measurement result is read from the DTBF register. In this case, the result of the previous measurement in the DTBF register is repl aced by that of the next measurement. The measurement is continued regardless of the ERR bit value. The ERR is read-only. Writing a value does not affect the bit value. The ERR bit is cleared by reading the measurement result (DTBF). Bit Description 0 Normal status 1 A measurement result not yet read was overwritten by the next measurement result. [bit 6] EDIE: Measurement completion interrupt request enable bit This bit controls interrupt requests of bit 2 EDIR. When the EDIE bit is enabled, setting bit 2 EDIR generates an interrupt request to the CPU. Bit Description 0 Disables interrupt requests. 1 Enables interrupt requests. [bit 5] res : Reserved bit The read value is 0. Set 0 to this bit. [bit 4] OVIE: Overflow interrupt request enable bit This bit controls interrupt requests of bit 0 OVIR. When the OVIE bit is enabled, setting bit 0 OVIR generates an interrupt request to the CPU. Bit Description 0 Disables interrupt requests. 1 Enables interrupt requests. [bit 3] res: Reserved bit The read value is 0. Set 0 to this bit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 491 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions [bit 2] EDIR: Measurement completion interrupt request bit This bit indicates that the completion of measurement. The flag is set to 1 when the measurement is completed. The EDIR bit is cleared by read ing the measurement result (DTBF). The EDIR is read-only. Writing a value does not affect the bit value. Bit Description 0 Reads the measurement result (DTBF). 1 Detects an interrupt cause. [bit 1] res: Reserved bit The read value is 0. Set 0 to this bit. [bit 0] OVIR: Overflow interrupt request bit When a counter value overflow from 0xFFFF to 0x0000 occurs, the flag is set to 1. The OVIR bit is cleared by writing 0. Even if 1 is written to the OVIR bit, the bit value is not affected. The read value of read-modify-write instructions is 1 regardless of the bit value. Bit Description 0 Clears an interrupt cause. 1 Detects an interrupt cause. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 492 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions FUJITSU SEMICONDUCTOR LIMITED Chapter: Base Timer FUJITSU SEMICONDUCTOR CONFIDENTIAL 80 9.4.3. Data Buffer Register (DTBF) The Data Buffer Register (DTBF) is a register that reads the measured or count value of the PWC timer. In 32-bit mode, the value of the lower 16 bits is read for the even channel and that of the upper 16 bits for the odd channel. Be sure to use the 16-bit data transfer instruction to read this register. bit 15 0 Field DTBF [15:0] Attribute R Initial value 0x0000 The DTBF register is read-only in both continuous and one-shot measurement modes. Writing a value does not change the register value. In continuous measurement mode (TMCR bit 3 MDSE = 1) , this register works as a buffer register that stores the previous measurement result. In one-shot measurement mode (TMCR bit 3 MDSE = 0), the DTBF register accesses the up counter directly. The count value can be r ead during counting. The measurem ent value is retained after the completion of measurement. Access the DTBF register with 16-bit data. CHAPTER 14-2: Base Timer MN706-00002-1v0-E 493 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 494 MB9Axxx/MB9Bxxx Series