Fujitsu Series 3 Manual
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4. LIN Interface (Ver. 2.1) Operations 4. LIN Interface (Ver. 2.1) Operations The LIN interface (ver. 2.1) performs bi-directional LIN communication of master and slave. Master mode operations Selecting master mode To operate the LIN interface as a master, set the SCR:MS bit to 0. Break field transmission-sy nc field transmission The break field length (ESCR:LBL1, LBL0) and the break field delimiter length (ESCR:DEL1, DEL0) can be selected. If transmission is enabled (SCR:TXE=1), and the SCR:LBR bit (LIN Break field setting bit) is set to 1, then the break field is transmitted. The sync field is transmitted when 0x55 is written to the Transmit Data Register (TDR). Before setting th e Tr ansmit Data Register (TDR) to 0x55, set the SCR:LBR bit (LIN break field setting bit) to 1. Setting the SCR:RXE bit (reception enable bit) to 1 does not enable the break field to perform reception. Figure 4-1 Break field-sync field transmission LIN bus SCR:LBR LIN Break ESCR:DEL1/0 LIN Break delimiter ESCR:LBL1/0Synch Field Data writing in Sync field (0x55) SCR:TXE SSR:TDRE Break field length - ESCR:LBL1, LBL0 and, theref ore, it can be set between 13 and 16 bits long. Break delimiter length - ESCR:DEL1 , DEL0 and, therefore, it can be set between 1 and 4 bits long. SCR:RXE SSR:TBI FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 925 MB9Axxx/MB9Bxxx Series
4. LIN Interface (Ver. 2.1) Operations Sync field transmission- ID field transmission When the first bit of the sync field (0x55) is transm itted, the SSR:TDRE (transmit data empty) bit is set to 1. If transmit interrupts are enabled (SCR:TIE = 1) during this time, a transmit interrupt occurs. If a transmit interrupt occurs, the ID field can be written to the Transmit Data Register (TDR). If a receive interrupt occurs, compare the received data with the transmit data to make sure that no error has occurred. The ID field is output in 8-bit data length and LSB-first order. LIN bus ST ID FieldSynch Field Data writing in ID field SSR:TDRE Sync Break delimiter SSR:RDRF 012345 67SPST0 1 23456 7SP ID field transmission-DATA field transmission/reception Select whether to transmit the DATA field to a slave device or to receive the DATA field. (To transmit the DATA field) When the first bit of the ID field is transmitted, the SSR:TDRE bit is set to 1. Then data can be written to the DATA field. Figure 4-2 ID field transmission-DATA field transmission LIN bus Data field transmissionID field transmission Data writing in Data field SSR:TDRE Sync Field (To receive the DATA field) When the first bit of the ID field is transmitted, th e SSR:TDRE bit is set to 1. However, do not write any transmit data then. Also disable transmit interrupts (SCR:TIE = 0). When the DATA field is received, SSR:RDRF is set to 1. If receive interrupts are enabled (SSR:RIE = 1) then, a receive interrupt occurs. A start bit is detected when a falling edge is detected after data passes the noise filter (with the majority value applied after sampling serial data input three times with the bus clock) and a LOW level is detected for the data passing the sampling point. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 926 MB9Axxx/MB9Bxxx Series
4. LIN Interface (Ver. 2.1) Operations
Figure 4-3 ID field transmission-DATA field reception
LIN bus
Data field receptionID field transmission
Data reading of
Data field
SSR:TDRE
Sync Field
SSR:RDRF
The LIN interface (Ve r
. 2.1) in
cludes noise filter (with the majority value applied after sampling serial
data input three times with the bus clock). However, design the board so as not to allow noise to pass
through this filter or perform communications so that any noise that has passed does not cause any
problems (e.g., by adding a data checksum to the end and resending the data if any error occurs).
During reception, if a falling edge of the serial data is detected concur rently with, or 1 to 2 bus clocks
before the sampling po int of the stop bit, the edge is ignored and the next data cannot be received
successfully. To output frames continuously, adequate intervals should be considered between frames.
Master mode operation timing ch art (when FIFO is not used)
Figure 4-4 LIN bus timing (when DATA field is transmitted and FIFO is not used)
SCR:LBR
LIN bus
Data writing
in TDR
TDR
TIE
RIE,TXE
RDRF(RIRQ)
Start of LIN break
Data writing in Sync
field (0x55)
A transmit interrupt occurred.:
The ID field is set.
Break field Sync Field ID Field Data field transmission
TDRE(TIRQ)
SCR:RXE
Sync Field (0x55) ID Fild
DATA1
DATA2
DATA3
A transmit interrupt occurred.:
The Data field is set. SCR:MS
0
A receive interrupt occurred.:
The Data field is read.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051
MN706-00002-1v0-E
927
MB9Axxx/MB9Bxxx Series
4. LIN Interface (Ver. 2.1) Operations Figure 4-5 LIN bus timing (when DATA field is received and FIFO is not used) SCR:LBR LIN bus Data writing in TDR TDR TIE RIE,TXE RDRF(RIRQ) Start of LIN break Data writing in Sync field (0x55) A transmit interrupt occurred.: The ID field is set. TIE is cleared. Break field Sync Field ID Fi eld Data field reception TDRE SCR:TBIE Sync Field(0x55) ID Field A receive interrupt occurred.: The Data is read. Data reading from RDR RXE A receive interrupt occurred.: The Data is read. Master mode operation timing chart (when FIFO is used) Figure 4-6 LIN bus timing (when DATA field is transmitted and FIFO is used) SCR:LBR LIN bus Data writing in FIFO TDR Transmit FBYTE RIE,TXE RDRF(RIRQ) Start of LIN break A transmit interrupt occurred.: Transmit FIFO is written. Break field Sync Field ID Field Data field reception FDRQ(TIRQ) Sync Field (0x55) ID Field DATA1 DATA2 DATA3 FDRQ 5 4 3 2 1 0 FTIE RXE Transmit FIFO is enabled, but receive FIFO is disabled. A receive interrupt occurred.: The Data is read. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 928 MB9Axxx/MB9Bxxx Series
4. LIN Interface (Ver. 2.1) Operations Figure 4-7 LIN bus timing (when DATA field is received and FIFO is used) Receive FBYTE (display) Receive FBYTE (setting) SCR:LBR LIN bus Data writing in FIFO TDR Transmit FBYTE TXE RDRF(RIRQ) Start of LIN break A transmit interrupt occurred.: Transmit FIFO is written. Break field Sync Field ID Field Data field reception TIRQ Sync Field (0x55) ID Field FDRQ 1 FTIE 3 A receive interrupt occurred.: FIFO is read. RXE TIE TIE RIE A transmit interrupt occurred.: The ID field is set. SCR: TIE is cleared. A receive interrupt occurred.: The Data is read. A receive interrupt occurred.: The Data is read. Receive FIFO enabled0 012 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 929 MB9Axxx/MB9Bxxx Series
4. LIN Interface (Ver. 2.1) Operations
Slave mode operations
Selecting slave mode
To operate the LIN interface as a sl ave, set the SCR:MS bit to 1.
Break field reception-sy nc field reception
1. If the break field is input, the break field is detected (SSR:LBD = 1) at the 11th bit.
If the ESCR:LBIE bit is set to 1 then, a receive interrupt occurs.
2. Enable ICU interrupts then to detect both edges.
3. The LIN interface (ver. 2.1), u pon the detection of the first falling edge in the sync field, sets the internal
signal (LSYN) input to ICU to HIGH to start the ICU. This internal signal (LSYN) turns to LOW at the
fifth falling edge.
4. The internal signal (LSYN) input to ICU is a value that the HIGH period multiplies the baud rate by
eight. The baud rate set value is obtained as follows:
If the free run timer is not overflowed:
BGR value = (b - a) x Fe/(8 x ) ) - 1
If the free run timer is overflowed:
BGR value = (max + 1 + b - a) x Fe/(8 x ) - 1
where, max : Maximum value of the free run timer
a : The ICU data register value after the first interrupt
b : The ICU data register value after the second interrupt
: Bus clock frequency (MHz)
Fe : External clock frequency (MHz). When the internal clock is used (EXT = 0),
Fe = is assumed.
To ope
rate the break field the sync field, disable the reception (SCR:RXE = 0).
Figure 4-8 Break field reception-sync field reception
LIN bus
Break Field
LSYN
SSR:LBD
Synch Field
(1) (2) (3),(4)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051
MN706-00002-1v0-E
930
MB9Axxx/MB9Bxxx Series
4. LIN Interface (Ver. 2.1) Operations ID field reception-DATA fi eld transmission/reception After reception of the ID field, whether to transmit or to receive the DATA field can be selected. (To transmit the DATA field) After reception of the ID field, wr ite data to the Transmit Data Register (TDR). Enable transmit interrupts (SCR:TIE = 1) during this time. Figure 4-9 ID field reception-DATA field transmission LIN bus Data field transmissionID field reception Data reading from RDR SSR:RDRF Sync Field SSR:TDRE SCR:TIE Data writing in TDR (To receive the DATA field) Every time the DATA field is received, SSR:RDRF is set to 1. If receive interrupts are enabled (SCR:RDRF = 1) then, a receive interrupt occurs. A start bit is detected when a falling edge is detected after data passes the noise filter (with the majority value applied after sampling serial data input three times with the bus clock) and a LOW level is detected for the data passing the sampling point. Figure 4-10 ID field reception-DATA field reception LIN bus Data field reception ID field reception Data reading from RDR SSR:RDRF Sync Field The LIN interface (Ve r . 2.1) in cludes noise filter (with the majority value applied after sampling serial data input three times with the bus clock). However, design the board so as not to allow noise to pass through this filter or perform communications so that any noise that has passed does not cause any problems (e.g., by adding a data checksum to the end and resending the data if any error occurs). During reception, if a falling edge of the serial data is detected concur rently with, or 1 to 2 bus clocks before the sampling po int of the stop bit, the edge is ignored and the next data cannot be received successfully. To output frames continuously, adequate intervals should be considered between frames. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 931 MB9Axxx/MB9Bxxx Series
4. LIN Interface (Ver. 2.1) Operations Slave mode operation timing chart Figure 4-11 LIN bus timing (when DATA field is transmitted and FIFO is not used) LSYN (ICU input) LIN bus ICU(IRQ) RXE TIE TXE RDRF(RIRQ) A status interrupt occurred.: LBD is cleared. Transmit interrupt enabled (TIE=1) Transmission enabled (TXE=1) A transmit interrupt occurred.: The Data is set. Baud rate setting Receive interrupt enabled (RIE=1) Receive enabled (RXE=1) Break field Sync Field ID Field Data field transmission LBIE LBD RIE TDRE(TIRQ) IRQ(ICU) IRQ is cleared. A receive interrupt occurred.: The Data is read. Figure 4-12 LIN bus timing (when DATA field is received and FIFO is not used) LSYN (ICU input) LIN bus ICU(IRQ)RXE TIE TXE RDRF(RIRQ) A status interrupt occurred.: LBD is cleared. Baud rate setting Receive interrupt enabled (RIE=1) Receive enabled (RXE=1) Break field Sync Field ID Field Data field reception LBIE LBD RIE TDRE(TIRQ) IRQ(ICU) IRQ is cleared. A receive interrupt occurred.: The Data is read. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 932 MB9Axxx/MB9Bxxx Series
4. LIN Interface (Ver. 2.1) Operations If FIFO is used Figure 4-13 LIN bus timing (when DATA field is transmitted and FIFO is used) Data writing in transmit FIFO Transmission enabled (TXE=1) Receive FIFO disabled Break field Data writing in transmit FIFO LSYN (ICU input) LIN bus ICU(IRQ)RXE TIE TXE RDRF(RIRQ) A status interrupt occurred.: LBD is cleared. Baud rate setting Receive interrupt enabled (RIE=1) Receive enabled (RXE=1) Sync Field ID Field Data field transmission LBIE LBD RIE TDRE(TIRQ) IRQ(ICU) IRQ is cleared. A receive interrupt occu rred.: The Data is read. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 933 MB9Axxx/MB9Bxxx Series
4. LIN Interface (Ver. 2.1) Operations Figure 4-14 LIN bus timing (when DATA field is received and FIFO is used) Reading from receive data Receive FIFO enabledReading from receive FIFO Break field Data reading from receive FIFO LSYN (ICU input) LIN bus ICU(IRQ)RXE TIE TXE RDRF(RIRQ) A status interrupt occurred.: LBD is cleared. Baud rate setting Receive interrupt enabled (RIE=1) Receive enabled (RXE=1) Sync Field ID Field Data field reception LBIE LBD RIE TDRE(TIRQ) IRQ(ICU) IRQ is cleared. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 934 MB9Axxx/MB9Bxxx Series