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Fujitsu Series 3 Manual

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3. Operations of USB Function 
 
 Operation of each register in  response to a write command 
The following explains the case of Se tDescripter and class vendor commands. 
Figure 3-7 Operation of Each Register in Response to a write Command 
 
  
FUJITSU SEMICONDUCTOR LIMITED 
 
  Setup sequence 
Upon the receipt of the setup stage, DRQO change s to 1. Immediately when DRQO has changed to 
1, enter the CPU interrupt and ch eck the SETP flag. If the flag is 1, read required bits of the 
command in the receive buffer. (Not necessarily r ead all the eight bytes.)Subsequently, decode the 
command, configure required settings. 
In preparation of 0-byte response in the status stage, do not write data to the send buffer, and set DRQI 
to 0 (as the DRQI interrupt cause is initially set to 1).Set the DRQIIE to 1 to check a successful 
completion of the status stage. Clear the SETP flag  and the DRQO interrupt cause to return from the 
interrupt. 
   Data stage sequence 
DRQO is set when the data packed to OUT direc tion has finished. Immediately when DRQO is set, 
enter the CPU interrupt and check SIZE in the EP0  Status Register.Use DMA limited to received data, 
or use CPU read access to read data from the send  buffer.Subsequently, clear interrupt cause DRQO to 
return from the interrupt. 
   Command end sequence 
DRQI is set when the status stage to the IN directio n has finished. Immediately when DRQI is set, enter 
the CPU interrupt and check that th e status stage has finished successfully. Subsequently, clear interrupt 
cause DRQI, and return. 
Host   Device SETUP 
SETP 
DRQI 
Device   
HostACK
Setup stage Status stage Data stage
OUT 
DRQO 
DRQIIE 
DRQOIE 
ACK
DATA0
 DATA0OUT
DATA1 INACK
DATA1 ACK
Cleared by 
software .
DATA1 
DATA0 
Cleared by 
CommandCleared by 
read
readreadsoftware . .
software
 ) 
(1 Setup stage 
sequence
 
(2 ) Data stage 
sequence (3 ) Command end 
sequence
 
CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
3.4. Suspend function 
Depending on the bus power configuration, USB devices must drop the power consumption to 
500 A or less in suspend state. The following explains the sequence a device makes 
transition to suspend state, and then stop mode or timer mode. 
  Suspend sequence 
When the USB device core detects a suspend state, SUSP in the UDCS is enabled. 
The following provides  an example sequence. 
Figure 3-8 Suspend operation 
 
  
Suspend state 
FUJITSU SEMICONDUCTOR LIMITED 
 
   Suspend sequence 
When there is a 3 ms or longer period of inactivity on the USB bus, the USB function detects a suspend 
state, and sets the SUSP interrupt cause in the UDCS register.For devices supporting remote wake-up, 
the USB function waits 2 ms more * and sets stop mode or timer mode. 
*:  This period is required to block remote wake-up. 
 
 
Before stock mode or timer mode is entered, set UDCIE.SUSPIE = 0 and UDCC.USTP = 1 in this order. 
 
 
Host 
Device
 SOF 
1ms 1ms 3ms
SOF SOF
STP
 
If remote wake-up is  supported: 2mS
SUSP Set by software 
USTP 
CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
3.5. Wake-up function 
To recover a USB device from suspend state to wake-up state, the USB protocol provides two 
ways. 
- Remote wake-up from the device 
- Wake-up from the host 
 Remote wake-up 
Figure 3-9 Remote wake-up operation 
 
  
FUJITSU SEMICO NDUCTOR LIMITED 
 
The device must be processed  in the following sequence: 
1.  Recover the device from stop mode or timer mode by an external interrupt. 
2.  Check that the USB generation clock is stable. 
3.  Clear the SUSP bit in the UDCS register. 
4.  Perform a dummy read in the UDCS register. 
5.  Clear the USTP bit of the UDCC register. 
6.  Perform a dummy read of the UDCC register. 
7.  Set the RESUM bit in the UDCC register. 
8.  Clear the RESUM bit in the UDCC register. 
 
Host  
Device 
RESUME
STP 
20ms 1ms 1ms
Suspend state
SOF SOFRESUME
Device   Oscillation 
Host stabilization 
period
 
INT pin 
RESUM 
External interrupt
10ms
RESUM set and cleared by software
USTP 
SUSP Cleared by software .
CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
 Wake-up from the host 
Figure 3-10 Wake-up operation from the host 
 
  
Suspend state
FUJITSU SEMICONDUCTOR LIMITED 
 
Process the USB device in the following sequence. 
1. Set the oscillation stabilization time so that it will not exceeds 10 ms. 
2.  Check that the USB clock is stable. 
3.  Clear SUSP in the UDCS regi ster, and USTP in the UDCC register in this order. 
4.  Clear WKUP in the UDCS register. 
 
STP 
1ms 1ms
20 ms or more 
SOF SOF
WKUP 
RESUMEHost 
Device
 
Oscillation SUSP, USTP, WKUP
stabilization period flags cleared by softwar
e
SUSP 
USTP 
CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
3.6.  DMA transfer function 
Data handled by the USB function can be transferred via DMA between the send/receive 
buffer and internal RAM. The following two modes are available for the DMA transfer. 
- Packet transfer mode that transfers each packet according to the configured data size   
- Automatic data size transfer mode that transfers the configured data size by a single 
transfer. 
 Packet transfer mode 
The packet transfer mode transfers each packet accord ing to the data size set in DMA and, each time the 
transfer of a packet finished, clears the interrupt cause for the next packet transfer.This transfer mode can 
access buffers of Endpoints 1 to 5. Before using DMA,  set the interrupt output destination by the DREQ 
Select Register. (Connect the in terrupt output to CPU.NVIC. For details, see Chapter DMAC.) 
The following shows th e timing to access buffers in each OUT direction and IN direction. 
 Transfer in the OUT direction (Host -> Device) 
Figure 3-11 OUT packet transfer 
 
  
FUJITSU SEMICONDUCTOR LIMITED 
 
In the OUT direction transfer, the device must be processed in the following sequence:  1. Once the DRQ flag is set and the interrupt hand ling is entered, check the transfer data size. 
2.  Configure the DMA register setting relevant to the number of transfers and block size corresponding 
to the transfer data size, and then  enable DMA to start the transfer. 
3.  After the transfer, clear the per tinent DRQ flag in the EP1S to EP5S registers and the pertinent 
interrupt source flag in the DMAC status register, and return from the interrupt handling. 
 
SIZE DRQ
DRQ flag 
cleared by 
CPU
DMA operation enable bit 
0 Disables DMA operation 1 Enables DMA operation Reads from DMA 
receive buffer
(DATA0)
Host   
Device  
OUT packet
Device 
Host 
OUT packet 
OUT
ACK
OUTDATA0 DATA1
ACK
DRQIE 
DMAE 
DRQ flag 
cleared by 
CPU
 
Reads from DMA 
receive buffer (DATA1) 
CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
 Transfer in the IN direction (Host -> Device) 
Figure 3-12 IN packet transfer 
 
  
FUJITSU SEMICO NDUCTOR LIMITED 
 
In the IN direction transfer, the device mu st be processed in the following sequence: 
1.  Once the DRQ flag is set and the interrupt handlin g is entered, configure the DMA register settings 
relevant to the number of transfers and block size corresponding to the data size to be transferred in 
the next IN packet, and then enable DMA to start the transfer. 
2.  After the DMA transfer, clear the pertinent DRQ flag in the EP1S to EP5S registers and the pertinent 
interrupt cause flag in the DMAC status register, and return from the interrupt handling. 
 
DRQ 
DRQ flag 
cleared by 
CPU
Host  
Device
 
IN packet 
Device   
Host 
IN packet
INACK 
DRQIE 
DATA1 
DMAE 
DATA0
ACKIN
DRQ flag 
cleared by  CPU
DMA operation enable bit 0 Disables DMA operation
1 Enables DMA operation Writes to DMA send  Writes to DMA send 
buffer buffer
(DATA0 (DATA1)
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3. Operations of USB Function 
 
 Automatic data size transfer mode 
This mode can transfer even bytes. To transfer od d bytes, a CPU transfer sequence is required. (See  Figure 
3-14 ) Before using DMA, set 
the interrupt output destination by the DREQ Select Register.(Connect the 
interrupt  ou

tput to DMAC.) For details, see Chapter DMAC.Configure in DMA the total data size to 
transfer, and also set the transfer enable bit previous ly.If DRQ is set after transfer from the host while 
DMAE is enabled, the interrupt cause is automatically  cleared when the data size corresponding to PKS in 
the EP1 to EP5 Control Registers (EPxC) has been transferred. Afterward, the same sequence is repeated 
after transfer from the host until the transfer data size configured prev iously in DMA is reached.Meanwhile, 
configuration by the CPU is not required at all. Thus th is mode can transfer data automatically by a single 
setting. The CPU interrupt is entered after the transfer  of the last data. To perform the next transfer, 
therefore, reconfigure DMAC then  to enable DMA and return from the interrupt. The automatic data size 
transfer mode uses DMAE as 1, buffer access to Endpoints 1 to 5 is only enabled. The following shows 
the timing to access the buffer in  each of the OUT and IN directions. 
 Transfer in the OUT direction (Host -> Device) 
Figure 3-13 Transfer in the OUT direction (Host -> Device) 
 
  
FUJITSU SEMICONDUCTOR LIMITED 
 
In the OUT direction transfer, the device must be processed in the following sequence:  1. Configure the DMA register setting relevant to the number of transfers and block size corresponding 
to the total data size, and then enable DMA to start the transfer. 
2.  Enable DMAE and DRQIE. 
3.  After the transfer, reconfigure the DMAC using an in terrupt generated by the interrupt cause pertinent 
to the DMAC status register, and clear the fl ag to return from the interrupt handling. 
 
To transfer the data size corresponding to the odd  bytes via DMA, either of the following methods are 
available: 
  Use the CPU transfer only for the last data, and read the low-order byte (EPxDTL). 
   Transfer all the data + 1 byte via DMA, and discard the last data after an endian conversion. 
 
SIZE  
DRQ
Last OUT packet 
DRQ flag 
cleared 
automatically
Reads PKS data from 
DMA receive buffe
r
ACK 
OUTDATA1
Reads the rest data from 
DMA receive buffe
r
DRQ flag 
cleared 
automaticallyHost   Device
OUT packet
OUT DATA0
ACKDevice   Host
DMAE
DRQIE
DATA1 DATA0
DMA operation enable bit 0 Disables DMA operation 1 Enables DMA operation 
CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
Figure 3-14 Example odd bytes transfer in the OUT direction   
 
150 150
To transfer the last data via the CPU
EPxDTH/SPxDTL
DMA 
transfer
(Read)
15 0 15
0
11H(1st byte)
The data is discarded
To transfer all data via DMA
EPxDTH/SPxDTL Undefined
Transfer EPxDTL data via CPU (Read)
33H(3rd byte)
55
H(5th byte)
77
H(7th byte)99
H(9th byte)
22
H(2nd byte)
44
H(4th byte)
66
H(6th byte)
88
H(8th byte)
DMA 
transfer
(Read)
11H(1st byte)
Undefined
33H(3rd byte) 55
H(5th byte)
77
H(7th byte)99
H(9th byte)
22
H(2nd byte)
44
H(4th byte)
66
H(6th byte)
88
H(8th byte) 11
H(1st byte)
Undefined
33H(3rd byte)
55
H(5th byte)
77
H(7th byte)99
H(9th byte)
22
H(2nd byte)
44
H(4th byte)
66
H(6th byte)
88
H(8th byte) 11
H(1st byte)
33
H(3rd byte)
55
H(5th byte)
77
H(7th byte)
22
H(2nd byte)
44
H(4th byte)
66
H(6th byte)
88
H(8th byte)
  
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
 Transfer in the IN direction (Host -> Device) 
Figure 3-15 Transfer in the IN direction (Device -> Host) 
 
  
FUJITSU SEMICO NDUCTOR LIMITED 
 
In the IN direction transfer, the device mu st be processed in the following sequence: 
1.  Configure the DMA register setting relevant to the number of transfers and block size corresponding 
to the total data size, and then enable DMA to start the transfer. 
2.  Enable DMAE and DRQIE. 
3.  After the transfer, reconfigure the DMAC using an in terrupt generated by the interrupt cause pertinent 
to the DMAC status register, and clear the fl ag to return from the interrupt handling. 
 
To transfer the data size corresponding to the odd  bytes via DMA, use the CPU transfer only for byte 
writing to the last data. 
 
Figure 3-16 Example odd bytes transfer in the IN direction   
15 0
EPxDTH/EPxDTL
22H(2nd byte)
DMA transfer (Write)
Transfer data to EPxDTL via CPU (Write)
To transfer the last data via the CPU
44H(4th byte)
66
H(6th byte)88
H(8th byte) 11
H(1st byte)
33
H(3rd byte) 55
H(5th byte)77
H(7th byte)
99
H(9th byte)
 
 
Data
DRQ flag 
cleared 
automatically
 
Writes PKS data to 
DMA send buffer 
ACKIN
DATA1 
Writes the rest data to DMA send buffer 
DRQ flag 
cleared 
automatically
Host  
Device
 
Device   
Host DATA0
Last data
ACK IN
DMAE
DRQIE 
DRQDATA0 DATA1
DMA operation enable bit
 0 Disables DMA operation 1 Enables DMA operation 
CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
3.7.  NULL transfer function 
If data sent from the USB function is the last packet and satisfies the maximum packet size, 
then the 0-byte can be automatically transferred via the next packet transfer. DMAE must be 
enabled to use this function. This function is valid only in IN transfer. 
  NULL transfer mode 
NULL transfer mode sends 0-byte in reply to the next ho sts data request in the IN direction after the last 
data in the IN direction has been transferred. 
NULL transfer mode works when the following conditions are met: 
   Automatic buffer transfer mode is set (DMAE = 1) 
   The last data transfer writes the maximum packet size to the DMA buffer 
   DMA data units are counted as 0 by writing the last data 
 
After the last data has been written to buffer via DM A, the DRQ interrupt flag is not set until the 0-byte 
data is read from the host. The followi ng shows the timing to access the buffer. 
Only the transfer in the IN direction (Device -> Host) is explained. 
Figure 3-17 NULL data transfer operation 
 
  
FUJITSU SEMICO NDUCTOR LIMITED 
 
The device must be processed as follows: 
1. Enable DMAE, DRQIE, and NULE. 
 
DRQ
0-byte data 
NULE 
Interrupt cause 
is not set
Device   
Host 
DMAE 
DRQIE 
ACK 
Host  
Device 
DATA0
ACK
Last data
ININ 
Pre-last data
INACK
DRQ flag 
cleared 
automatically
 
Writes max . 
packet size to 
DMA send buffe
r 
DATA0 DATA1
Last data
DATA1 DMA operation enable bit 
0 Disables DMA operation
1 Enables DMA operation
CHAPTER  20-2: USB Function 
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