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Figure 4-2 I2C flowchart example (FIFO not used) when DMA mode is disabled   
(SSR:DMA=0) 2/3 
Slave mode
IBSR:RSA=0?
IBSR:TRX=0?
IBSR:FBT=0?
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE)
Clear the interrupt flag. (IBCR:INT=0)
IBSR:RACK=0?
Write the send data. (TDR)
Set the waiting. (IBCR:WSEL)
Clear the interrupt flag. (IBCR:INT=0)
Clear the interrupt flag. (IBCR:INT=0) 
End
Yes
Yes Yes
No
No No
Yes
A
IBSR:FBT=1 ?
Yes
Read the received data. (RDR)
Slave mode 
operation?
IBSR:TRX=1 ?
Write the send data. (TDR)
Set the waiting. (IBCR:WSEL) Set an ACK. (IBCR:ACKE=0)
Clear the interrupt flag. (IBCR:INT=0)
A
Set the waiting. (IBCR:WSEL)Set an ACK. (IBCR:ACKE=1)
Clear the interrupt flag. (IBCR:INT=0)
Yes
Yes NoSet an ACK. (IBCR:ACKE=0)
Clear the interrupt flag. (IBCR:INT=0)
End
No
IBSR:FBT=1 ?
Read the received data. (RDR)
No
Yes
Yes
No
 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
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Figure 4-3 I2C flowchart example (FIFO not used) when DMA mode is disabled   
(SSR:DMA=0) 3/3 
Reserved 
address
IBSR:FBT=1 ?
Multiple Master 
mode?
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL=1) Set an ACK. (IBCR:ACKE=1)
Clear the interrupt flag. (IBCR:INT=0)
A
Yes
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL) Set an ACK. (IBCR:ACKE)
Clear the interrupt flag. (IBCR:INT=0)
No
No
Yes
IBSR:TRX=1?
SSR:RDRF=1? 
Read the received data. (RDR)
Write the send data. (TDR)
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE=0)
Clear the interrupt flag. (IBCR:INT=0)
IBSR:RACK=0?
B
A
Set the waiting. (IBCR:WSEL=1) Set an ACK. (IBCR:ACKE=1)
Clear the interrupt flag. (IBCR:INT=0)
Completed to  send?
Completed to receive?
Read the received data. (RDR)Yes
Yes
Yes Yes
No No
No
No
A
Yes (NACK response)
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE=0)
No
 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
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 I2C flowchart examples (FIFO not used) when DMA mode is enabled 
(SSR:DMA=1) 
Figure 4-4 I2C flowchart example (FIFO not used) when DMA mode is enabled   
(SSR:DMA=1) 1/4 
Start
Initial settings:
Baud rate (BGR)
Slave address (ISBA)
Slave mask (ISMK)
I
2C enabling (ISMK:EN=1)
Master mode?
SSR:TBI=1?
Write the send data. (TDR)Set the Master mode. (IBCR:MSS=1)
IBCR:INT=1?
IBCR:BER=0?
IBCR:ACT=1?
IBCR:RSA=0?
A
Bus error processing
Arbitration Lost processing
End
Slave mode
Reserved address
IBSR:FBT=0?
Read the received data. (RDR)
Completed to receive
Set the waiting. (IBCR:WSEL=1)
Set an ACK. (IBCR:ACKE=1)
Write the dummy data. (TDR)Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE=0)
Start to iterate?
Write the send data. (TDR)
Set the iteration start.
(IBCR:MSS=SCC=1)
Set an ACK. (IBCR:ACKE)
Clear the interrupt flag. (IBCR:INT=0)
Set to stop. (IBCR:MSS=0)
Set an ACK. (IBCR:ACKE)
Clear the interrupt flag. (IBCR:INT=0)
End
Yes No
Yes No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes Yes
Yes No
No
IBSR:RACK=0?
IBCR:MSS=1?
IBCR:TRX=1?
Completed to send?
Write the send data. (TDR)Set the waiting. (IBCR:WSEL)Set an ACK. (IBCR:ACKE)
Clear the interrupt flag.
(IBCR:INT=0)
Yes
Yes
Yes
No
No
No
BNoYes
Master mode (TBI interrupt)
 
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Figure 4-5 I2C flowchart example (FIFO not used) when DMA mode is enabled   
(SSR:DMA=1) 2/4 
Master mode (TBI interrupt)
IBCR:TRX=1?
Completed to send?
Yes No
A
No
Yes
Read the received data. (RDR)
Completed to receive
Set the waiting. (IBCR:WSEL=1)
Set an ACK. (IBCR:ACKE=1)
Write the dummy data. (TDR)
NoWrite the send data. (TDR)
Set the waiting.
(IBCR:WSEL)
Set an ACK. (IBCR:ACKE)
A
Start to iterate?
Write the send data . (TDR)
Set the iteration start .
(IBCR:MSS=SCC=1)
Set an ACK. (IBCR:ACKE)
Clear the interrupt flag .
(IBCR:INT=0)
End
No
Yes
Set to stop. (IBCR:MSS=0)
Set an ACK.(IBCR:ACKE)
Clear the interrupt flag. (IBCR:INT=0)Set an interrupt flag. (IBCR:INT)
IBCR:INT=1?
Error processing
End
A
Yes
No Receive the master data.
Send the master data. Yes
 
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Figure 4-6 I2C flowchart example (FIFO not used) when DMA mode is enabled   
(SSR:DMA=1) 3/4 
Slave mode
IBCR:INT=1?
IBSR:TRX=0?
IBSR:FBT=0?
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE)
Clear the interrupt flag.
(IBCR:INT=0)
IBSR:RACK=0?
Read the received data. (RDR)
Write the send data. (TDR) 
Set the waiting. (IBCR:WSEL)
Clear the interrupt flag.
(IBCR: INT=0) 
IBSR:RSA=0?
SSR:RDRF=1?
A
Clear the interrupt flag.
(IBCR:INT=0)
End
IBSR:FBT=1?
Read the received data. (RDR)
Slave mode operation?
IBSR:TRX=1?
Write the send data. (TDR) 
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE)
Clear the interrupt flag.
(IBCR:INT=0)IBSR:FBT=1?
Read the received data. (RDR)
Set the waiting.  (IBCR:WSEL)
Set an ACK. (IBCR:ACKE)
Clear the interrupt flag.
(IBCR:INT=0)
A
Set an ACK. (IBCR:ACKE=0)
Clear the interrupt flag. (IBCR:INT=0)
End
Yes No
Yes
Yes
Yes
Yes
Yes
Yes Yes Yes
No
No
No
No No
No No
NoIBSR:TRX=0?
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE)
Read the received data. (RDR)
SSR:TBI=1?
Set the waiting. (IBCR:WSEL)
Write the send data. (TDR) 
A
No No
Yes Yes
Send the slave data.
Receive the slave data. No
Yes
 
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Figure 4-7 I2C flowchart example (FIFO not used) when DMA mode is enabled   
(SSR:DMA=1) 4/4 
Reserved 
address
IBSR:FBT=1 ?
Multiple Master  mode?
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL=1) Set an ACK. (IBCR:ACKE=1)
Clear the interrupt flag. (IBCR:INT=0)
A
Yes
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL) Set an ACK. (IBCR:ACKE)
Clear the interrupt flag. (IBCR:INT=0)
No
No
Yes
IBSR:TRX=1?
SSR:RDRF=1? 
Read the received data. (RDR)
Write the send data. (TDR)
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE=0)
Clear the interrupt flag. (IBCR:INT=0)
IBSR:RACK=0? 
B
A
Set the waiting. (IBCR:WSEL=1) Set an ACK. (IBCR:ACKE=1)
Clear the interrupt flag. (IBCR:INT=0)
Completed to  send?
Completed to receive?
Read the received data. (RDR)Yes
Yes
Yes Yes
No No
No
No
A
Yes (NACK response)
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE=0)
No
 
 
 
The flow sho w

s an outline of operation settings in I
2C mode. To perform the appropriate operations, take 
into account error processing based on applications. 
 
 
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5. I2C Interface Registers 
The following lists the I2C interface registers. 
 List of I2C interface registers 
Table 5-1 List of I2C interface registers 
 bit 15                              bit 8 bit 7                               bit 0
IBCR (I2C Bus Control Register) SMR (Serial Mode Register) I2C 
IBSR (I
2C Bus Status Register) 
SSR (Serial Status Register) 
-  RDR/TDR (Transmit/Receive Data Register) 
BGR1 (Baud Rate Generator Register 1)  BGR0 (Baud Rate Generator Register 0) 
ISMK (7-bit Slave Address Mask Register

) ISBA (7-b it Slave Address Register) 
FCR1 (FIFO Control Register 1)  FCR0 (FIFO Control Register 0) FIFO 
FBYTE2 (FIFO2 Byte Register)  FBYTE1 (FIFO1 Byte Register) 
 
Table 5-2 I2C Interface bit assignment 
 Bit 15  Bit 14 Bit 13 Bit 12  Bit 11 Bit 10 Bit 09Bit 08 Bit 07 Bit 06Bit 05 Bit 04Bit 03  Bit 02  Bit 01Bit 00
IBCR/ 
SMR  ACT/ 
MSS  ACKEWSEL CNDE INTEBERINTMD2MD1MD0WUCRRIE TIE ITST1ITST0
SCC 
SSR/ 
IBSR  REC TSET DMATBIE ORE RDRFTDRETBIFBTRACKRSATRXAL RSC SPCBB
TDR1/ 
TDR0  - - - - - - - - D7 D6D5 D4D3 D2 D1 D0
BGR1/ 
BGR0  - B14 B13B12 B11 B10B9 B8B7 B6 B5 B4 B3 B2 B1 B0
ISMK/ 
ISBA  EN SM6 SM5SM4 SM3 SM2SM1SM0SAENSA6SA5SA4SA3 SA2 SA1SA0
FCR1/ 
FCR0  FTST1 FTST0 - FLSTE FRIIE FDRQFTIE
FSEL- FLSTFLDFSETFCL2 FCL1 FE2FE1
FBYTE2/ 
FBYTE1  FD15 FD14 FD13FD12 FD11 FD10FD9FD8FD7FD6FD5FD4FD3 FD2 FD1FD0
 
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5.1. I2C Bus Control Register (IBCR) 
The I2C Bus Control Register (IBCR) is used to select master or slave mode, generate an 
iteration start condition, enable an acknowledgement, enable an interrupt, and display an 
interrupt flag. 
 
bit 15 14 13 12 11 10 9 8 7 ... 0 
Field MSS  ACT/ 
SCC  ACKE WSELCNDEINTEBER INT (SMR) 
Attribute 
R/W R/W R/W  R/W R/W R/W R R/W     
Initial 
value  0 0 0 0 0 0 0 0    
 
[bit 15] MSS: Master/slave select bit 
 If this bit is set to 1 when the I2C bus is in idle state (ISMK:EN= 1, IBSR:BB=0), master mode is 
selected. 

 If this bit is set to 1 when the BB bit of IBSR regi ster is 1, the occurrence of start condition is waited 
until the IBSR:BB bit is set to 0. If the slave address matches and the slave operation is started during 
waiting, this bit is set to 0 and the AL bit of IBSR register is set to 1. 

 When master mode is selected (MSS=1, ACT=1) an d the interrupt flag (INT) is 1, a stop condition 
is generated when this bit is set to 0. 
 
The MSS bit is cleared in any of the following conditions. 
1.
 When the I2C interface operation is disabled (ISMK:EN bit=0) 
2.
 When an arbitration lost occurs 
3.
 When a bus error is detected (BER bit=1) 
4.
 When the MSS bit is set to 0 if INT=1 
5.
 When DMA mode is enabled (SSR:DMA=1), SSR:TBI=1, and when the MSS bit is set to 0 
 
The following provides the relation between MSS and ACT bits. 
MSS bit  ACT bit  State 
0 0 Idle 
0 1 The slave address matching or the reserved address is 
acknowledged (*1), and slave mode is selected. 
1 
0 The master operation is waited. 
1  1 During master mode operation (in master mode) 
*1) Acknowledgment: The SDA is LOW on the I2C bus during acknowledgement. 
 
Bit Description 
0 Selects  slave mode. 
1 Selects  master mode. 
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 
 If DMA mode is disabled (SSR:DMA=0) and the MSS bit is set to 1, the MSS bit must be set to 0 
only when the MSS bit is 1 and the INT bit is 1. If  the MSS bit is set to 0 when the ACT bit is 1, 
the INT bit is also cleared to 0. 

 If DMA mode is enabled (SSR:DMA=1) and the MSS bit is set to 1, the MSS bit must be set to 0 
only when the MSS bit is 1 and the INT bit is 1, or  the SSR:TBI bit is 1. If the MSS bit is set to 0 
when the ACT bit is 1, the INT bit is also cleared to 0. 

 When master mode is selected, the MSS bit is read to be 1 even when it is set to 0 while the ACT bit 
is 1. 
 
[bit14] ACT/SCC : Operation flag/iteration start condition generation bit 
This bit setting has a different meaning when it is written and read. 
During reading  During writing 
ACT bit  SCC bit 
The ACT bit indicates the current operation in master or slave mode. 
The ACT bit is set when: 
1.
 The start condition is output onto the I2C bus (master mode) 
2.
 The slave address matches the address sent  from the master device (slave mode) 
3.
 The reserved address is detected and it is acknowl edged (If MSS is 0, slave mode is selected.) 
 
The ACT bit is reset when: 
 1.
 The stop condition is detected. 
2.
 An arbitration lost is detected. 
3.
 A bus error is detected 
4.
 The I2C interface operation is disabled (ISMK:EN bit=0) 
 
 1.
 The (iteration) start condition is detected 
2.
 The stop condition is detected. 
3.
 The reserved address is detected (IBSR:RSA=1) but not acknowledged 
4.
 The I2C interface operation is disabled (ISMK:EN bit=0) 
5.
 When a bus error is detected (BER bit=1) 
 
If this bit is set to 1 in master mode, the iteration start is executed. This bit is disabled to set to 0. 
Description Bit  During writing During reading 
0  No effect  No operation 
During the I2C operation 
1  Generates an iteration start condition. 
 
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 
 The SCC bit must be set to 1 during an interrupt of master mode (when MSS=1, ACT=1 and 
INT=1) only. If the SCC bit is set to 1 when th e ACT bit is 1, the INT bit is cleared to 0. 

 This bit must not be set to 1 in slave mode (when MSS=0 and ACT=1). 

 If the SCC bit is set to 1 and if the MSS bit is set to 0 simultaneously, the MSS bit setting is 
preceded. 

 When data is read by a read-modify-wr ite instruction, the SCC bit is read. 

 If both of the following conditions are satisfied, the INT bit is set to 1 and the I2C bus is waited 
(SCL=LOW). To generate an iteration start condition,  clear the INT bit by setting the SCC bit to 1 
again. 

 The SCC bit is set to 1 during master mode interrupt at bit 8 (MSS=1, ACT=1, INT=1 and  WSEL=1). 

 A negative acknowledgement (NACK) is received at bit 9. 

 When DMA is enabled (SSR:DMA=1), the SSR:TBI bit  is 1 and the IBCR:INT bit is 0, follow the 
steps below to issue the iteration start condition.  1.
 Set the IBCR:INT bit to 1. 
2.
 Check that the IBCR:INT bit is set to 1. 
3.
 Write the slave address in the TDR. 
4.
 Set this bit to 1. 
 
[bit 13] ACKE: Data byte acknowledge enable bit 
 If this bit is set to 1, LOW is output when acknowledged. 

 This bit must be changed if any of the following conditions has occurred: 

 If DMA mode is disabled (SSR:DMA=0), the ACT bit is 1, and the INT bit is 1 

 If DMA mode is enabled (SSM:DMA=1), the AC T bit is 1, and the SSR:TBI bit is 1 

 If DMA mode is enabled (SSM:DMA=1), the ACT bit  is 1, the slave reception is selected, and the 
SSM:RDRF is 1 

 If the ACT bit is 0 
 
This bit is invalid in the following conditions. 
1.
 During acknowledgement to an address field other than the reserved address (automatic generation) 
2.
 During data transmission (IBSR:RSA= 0, IBSR:TRX=1, IBSR:FBT=0) 
3.
 If the receive FIFO is enabled and the slave mode  reception is selected (FCR0:FE=1, MSS=0, 
ACT=1), an ACK is returned. 
4.
 If the receive FIFO is enabled, the  WSEL bit is 0, the master mode reception is selected (FCR0:FE=1, 
MSS=1, ACT=1, WSEL=0), and the SSR:TDRE bi t is 0, an ACK is always returned. If the 
SSR:TDRE bit is 1, a NACK is returned. 
5.
 If the receive FIFO is enabled, WSEL=0, the reserved  address is detected and the slave transmission is 
selected (IBSR:RSA=1, IBSR:TRX=1, IBSR:FBT= 1), an ACK is always returned. To respond 
with a NACK, disable the receive FI FO and set the ACKE bit to 0 during interrupt after detection of 
the reserved address. 
6.
 The receive FIFO is enabled, the WSEL bit is 1,  the master mode reception is selected, and the 
Transmit Data Register has data (FCR0:FE=1,  MSS=1, ACT=1, WSEL=1, SSR:TDRE=0) 
 
Bit Description 
0 Disables  acknowledgment. 
1 Enables acknowledgement. 
 
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