Fujitsu Series 3 Manual

							    2. Configuration of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   6 
 Explanation of Block Diagram  
  DMAC  
DMAC is in 8 -ch configuration. Each channel performs independent transfer. The priority controller 
controls the transfer  operations of these channels, when there is a conflict among them.  
 Connection to the system  
The diagram of the system configuration in the figure has been simplified for explanation purposes. For 
more details, see the chapter "Overview of System". DMAC is  connected to CPU , Flash, RAM and 
Peripheral s via the system bus. It has its own bus that is independent from the CPU bus, allowing for 
transfer operation at CPU bus access. It accesses any address area in the system by specifying the address of 
transfer destination and transfer source for each channel in order to transfer data between the memory and 
Peripheral. Since some areas cannot be accessed from DMAC, check the memory map.  
 Connection of the hardware transfer request signal  
The interrupt signal from the Peripheral supporting hardware transfer is selected in the interrupt controller 
block (indicated as DRQSEL  in the figure) either to be used as the interrupt signal to CPU or the DMA 
transfer request signal to DMAC.  
When performing DMA transfer by hardwa re request, connect the interrupt signal from each Peripheral as 
the transfer request signal to DMAC. The interrupt signal from the Peripheral that does not support 
hardware transfer cannot be used as the DMA transfer request signal. When the interrupt sig nal is used as 
the transfer request to DMAC, it cannot be used as the interrupt to CPU. See the chapter " Interrupts". 
There are 32 DMA transfer request signals to be input to DMAC. For the correspondence between each 
signal and Peripheral, see  Table 2-1 in the next chapter.  
(This may vary depending on the model. It should be noted that for a Peripheral with multiple channels and 
multiple interrupt factors, some interrupts support DMA transfer, while others don ’t.  
In the case of hardware transfer, each channel of DMAC selects one transfer request signal out of the above 
32 transfer request signals in its operation.  
 Connection of the hardware transfer request clear signal  
Some of the Peripherals that support hardware transfer are required to clear the transfer request signal 
(interrupt signal) after the completion of the transfer. Although it is not illustrated in the figure, the transfer 
request signal is cleared for such Peripherals via DMAC by selecting it by  DRQSEL.  
 Connection of the hardware transfer stop request signal  
The multifunction serial unit (hereinafter abbreviated as "MFS") outputs the DMA transfer stop request 
signal. Although it is not illustrated in the figure, MFS ’s transfer stop request signal is connected to DMAC, 
when MFS is selected by DRQSEL . When the transfer stop request signal is asserted, DMAC stops the 
transfer operation. It is configured to mask the succeeding transfer request signals.  
 Interrupt signal from DMAC  
Although it is not illustrated in the figure,  an interrupt signal used to give notification of transfer completion 
is connected to NVIC. Each channel has 8 interrupt outputs.  
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2.2.  I/O Signals of DMAC 
This section describes the I/O signals of DMAC. 
 Transfer Request Signals to be Input to DMAC  
Table 2-1 shows a list of the transfer request signals to be input to DMAC and the interrupt signals from the 
corresponding Peripherals.  
Table 2-1 List of Transfer Request Signals and Interrupt Signals from Corresponding Peripherals  
IDREQ No. Interrupt Signal of Corresponding Peripheral 
0 Interrupt signal from EP1 DRQ of USB ch.0 
1 Interrupt signal from EP2 DRQ of USB ch.0 
2 Interrupt signal from EP3 DRQ of USB ch.0 
3 Interrupt signal from EP4 DRQ of USB ch.0 
4 Interrupt signal from EP5 DRQ of USB ch.0 
5 Scan conversion interrupt signal from A/D converter unit0 
6 Scan conversion interrupt signal from A/D converter unit1 
7 Scan conversion interrupt signal from A/D converter unit2 
8 Interrupt signal from IRQ0 of base timer ch.0 
9 Interrupt signal from IRQ0 of base timer ch.2 
10 Interrupt signal from IRQ0 of base timer ch.4 
11 Interrupt signal from IRQ0 of base timer ch.6 
12 Receiving interrupt signal from MFS ch.0 
13 Sending interrupt signal from MFS ch.0 
14 Receiving interrupt signal from MFS ch.1 
15 Sending interrupt signal from MFS ch.1 
16 Receiving interrupt signal from MFS ch.2 
17 Sending interrupt signal from MFS ch2 
18 Receiving interrupt signal from MFS ch.3 
19 Sending interrupt signal from MFS ch.3 
20 Receiving interrupt signal from MFS ch.4 
21 Sending interrupt signal from MFS ch.4 
22 Receiving interrupt signal from MFS ch.5 
23 Sending interrupt signal from MFS ch.5 
24 Receiving interrupt signal from MFS ch.6 
25 Sending interrupt signal from MFS ch.6 
26 Receiving interrupt signal from MFS ch.7 
27 Sending interrupt signal from MFS ch.7 
28 Interrupt signal from external interrupt unit ch.0 
29 Interrupt signal from external interrupt unit ch.1 
30 Interrupt signal from external interrupt unit ch.2 
31 Interrupt signal from external interrupt unit ch.3 
 
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 Interrupt Signals Output from DMAC  
Table 2-2 shows a list of the interrupt signals output from DMAC.  
Table 2-2 List of Interrupt Signals from DMAC  
Name of 
Interrupt Signal 
Interrupt Factor 
Register 
Interrupt Enable 
Register Interrupt Type 
DIRQ0  DMACB0.SS[2:0]  DMACB0.CI ch.0 successful transfer completion interrupt 
DMACB0.EI ch.0 unsuccessful transfer completion interrupt 
DIRQ1  DMACB1.SS[2:0]  DMACB1.CI ch.1 successful transfer completion interrupt 
DMACB1.EI ch.1 unsuccessful transfer completion interrupt 
DIRQ2  DMACB2.SS[2:0]  DMACB2.CI ch.2 successful transfer completion interrupt 
DMACB2.EI ch.2 unsuccessful transfer completion interrupt 
DIRQ3  DMACB3.SS[2:0]  DMACB3.CI ch.3 successful transfer completion interrupt 
DMACB3.EI ch.3 unsuccessful transfer completion interrupt 
DIRQ4  DMACB4.SS[2:0]  DMACB4.CI ch.4 successful transfer completion interrupt 
DMACB4.EI ch.4 unsuccessful transfer completion interrupt 
DIRQ5  DMACB5.SS[2:0]  DMACB5.CI ch.5 successful transfer completion interrupt 
DMACB5.EI ch.5 unsuccessful transfer completion interrupt 
DIRQ6  DMACB6.SS[2:0]  DMACB6.CI ch.6 successful transfer completion interrupt 
DMACB6.EI ch.6 unsuccessful transfer completion interrupt 
DIRQ7  DMACB7.SS[2:0]  DMACB7.CI ch.7 successful transfer completion interrupt 
DMACB7.EI ch.7 unsuccessful transfer completion interrupt 
 
Reference: Interrupt Generation Factors and Clearing (For details, see "4  DMAC Control".)  
  Interrupt from each channel is generated by the following factors:  
⋅   Upon the successful completion of channel transfer, " 101" is set to SS o f each channel. If the above value 
is set to SS with  CI=1 (successful transfer completion interrupt enabled), a successful transfer completion 
interrupt occurs.  
⋅   Upon the unsuccessful completion of channel transfer, " 001",  "010 ",  "011 " and  "100"  are set to SS of 
each channel. If the above value is set to SS with E I=1 (unsuccessful transfer completion interrupt 
enabled), an unsuccessful transfer completion interrupt occurs.  
⋅   The successful transfer completion interrupt and the unsuccessful transfer completion interrupt undergo 
logic OR; therefore, if either of the interrupts occurs, an interrupt occurs from the channel.  
 
Interrupt from each channel can be cleared by writing " 000" to SS.  
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3. Functions and Operations of DMAC  
This chapter describes the operations of D MAC in each transfer mode. 
 
3.1 Software -Block Transfer  
3.2  Software -Burst Transfer  
3.3  Hard ware-Demand Transfer  
3.4  Hardware- Block Transfer & Burst Transfer  
3.5  Channel Priority Control  
 
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3.1.  Software- Block Transfer  
This section describes Software -Block transfer.  
Figure 3-1 shows an example of the operation of Software -Block transfer. In this example, the following 
settings apply.  
⋅   Transfer mode  : Software request Block transfer (ST=1, IS=000000, MS=00)  
⋅   Transfer sour ce start address   : SA(DMACSA=SA)  
⋅   Transfer source address control   : Increment and reload available (FS=0, RS=1)  
⋅   Transfer destination start address   : DA(DMACDA=DA)  
⋅   Transfer destination address control   : Increment and reload not available (FD=0, RD=0)  
⋅   Transfe r data size  : Half -word (16bit), the number of blocks = 2,   
   the number of transfers = 3 (TW=01, BC=1, TC=2)  
⋅   BC/TC  reload  : reload available (RC=1)  
 
Figure  3-1 Example of Operation of Software- Block Transfer 
 
SA+0
SA+2
SA+4
SA+6
SA+8
SA+10
DA +0
DA+2
DA+4
DA+6
DA+8
DA+10
CPU
Start request
(Transfer Gap )
SA+0
SA+2
SA+4
SA+6
SA+8
SA+10
DA +12
DA+14
DA+16
DA+18
DA+20
DA+22
DMAC
End report
Start request
End report (
Transfer Gap )
( Transfer Gap )
( Transfer Gap )
BC+1
TC+1
BC +1
BC+1
BC+1
TC+1
BC +1
BC+1
Block transfer mode   
 
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DMAC performs the following operation, when the transfer content is set from CPU and then the start of 
the transfer is instructed.  
⋅   Due to the specification of the transfer data width, each transfer is performed by half -word (16bit) . 
⋅   According to the start addresses of the transfer source and transfer destination, the data width and the 
incremented/fixed specification, the transfer is performed in the area from the address SA to address DA, 
for the number of blocks (=BC+1) . 
⋅   In the case of Block transfer, a Transfer Gap occurs every time transfer of one block is completed.  
⋅   DMAC performs data transfer for the number of blocks (=BC+1)  by the number of trans fers (=TC+1) . 
The size of data to be transferred by each transfer request from CPU is " Data width (TW) x Number of 
blocks  (BC+1)  x Number of transfers (TC+1) ". 
⋅   Once the transfer is completed, DMAC notifies CPU of the completion.  
⋅   If the start of transfer is  instructed again after the completion of the transfer, the transfer is restarted from 
the previous transfer start address (SA+0) , because the transfer source address has been set to be reloaded 
(RS=1) . As the transfer destination address has not been specified to be reloaded (RD=0) , the transfer is 
started from the next address (DA+12)  after the previous transfer end address. Also, as the reload of 
BC/TC has been specified, the same values as for the previous transfer are reloaded for the number of 
blocks  and the number of transfers for the next transfer.  
 
Transfer Gap  is a time period during which no transfer is performed, and it is inserted to prevent one of the 
DMAC channels from taking the possession of the system access right. If multiple channels have  transfer 
requests, DMAC switches the channels that will perform the transfer operation at the timing of the Transfer 
Gap. The frequency of Transfer Gap generation can be controlled by adjusting the settings of BC and TC. 
Moreover, the bus access right is also passed on to CPU at the Transfer Gap timing. System buses in this 
model are in Multi -layered configuration with a special system bus dedicated to DMA. For this reason, if 
there is no conflict between CPU and the destination of access, transfer can be performed at the same time 
as the CPU operation. Even if there is a conflict between CPU and the destination of access, the CPU 
operation is little affected, as long as the DMAC transfer is in a different address area group (RAM and 
Peripheral, or Flash and RAM, etc). However, if the transfer is in the same address area group (RAM and 
RAM, etc.), the CPU operation and/or system performance may be affected, depending on the number of 
blocks used; therefore, attention must be paid.  
(" Address area group " menti oned above refers to a group of address areas that are connected on the AHB 
system bus with the same bus bridge.) 
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3.2.  Software -Burst Transfer  
This section describes Software- Burst transfer. 
Figure 3-2 shows an example of the operatio n of Software -Burst  transfer. In this example, the following 
settings apply.  
⋅   Transfer mode  : Software request B urst transfer  (ST=1, IS=000000,  MS=01)  
⋅   Transfer source start address   : SA(DMACSA=SA)  
⋅   Transfer source address   : Fixed, reload available (FS=1, RS= 1) 
⋅   Transfer destination start address   : DA(DMACDA=DA)  
⋅   Transfer destination address   : Increment and reload not available (FD=0, RD=0)  
⋅   Transfer data size  : Word (32bit) , the number of blocks = 3, the number of transfers = 2   
   (TW= 10,  BC=2,  TC=1)  
⋅   Reload of t he number of transfers   : Number of transfers to be reloaded (RC=1)  
 
Figure  3-2 Example of Operation of Software-B urst Transfer  
 
CPU
Start request
DMAC
End report
Blurst transfer mode 
SA+0
SA+0
SA+0
SA+0
SA+0
SA+0
DA+0
DA+4
DA+8
DA+12
DA+16
DA+20
BC+1
TC+1
BC+1
  
 
DMAC performs t he following operation, when the transfer content is set from CPU and then the start of 
the transfer is instructed.  
⋅   Due to the specification of the transfer data width, each transfer is performed by word (32bit).  
⋅   According to the start addresses of the transfer source and transfer destination, the data width and the 
incremented/fixed specification, the transfer is performed in the area from the address SA to address DA, 
for the number of blocks (=BC+1).  As the transfer source address is specified to be fixed, it is the same 
as the transfer source start address (SA+0) . 
⋅   In the case of Burst transfer, the transfer is executed continuously wit hout generating Transfer Gaps. 
⋅   DMAC performs data transfer for the number of blocks (=BC+1) by the number of transfers (=TC+1). 
The size of data to be transferred by each transfer request from CPU is " Data width (TW) x Number of 
blocks (BC+1) x Number of t ransfers (TC+1)". 
⋅   When the transfer is completed, DMAC notifies CPU of the completion.  
 
In the case of Burst transfer, no Transfer Gap is generated, unlike the Block transfer. As the channel to be 
controlled takes the possession of the system bus access ri ght, it can be used to put the priority on that 
particular channel.  
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3.3.  Hardware-Demand Transfer  
This section describes Hardware-Demand transfer. 
Hardware-Demand transfer is used when performing DMA transfer by the transfer request signal from the 
Peripherals  of  USB, MSF  and ADC . 
Hardware- Demand transfer is a method used to receive the transfer request signal from Peripherals on a 
signal level. If the transfer request signal is on High level, transfer is executed. If the transfer request signal 
is on Low level, no transfer is executed. Transfer is executed by setting the output of the interrupt signal 
from each Peripheral to High level (with interrupt request) when transfer data exists, or to Low level 
(without transfer request) when no transfer data exists.  
In  the case of Hardware -Demand transfer, always specify "1"  (BC=0) as the number of blocks.  
Figure  3-3 shows an example of the operation of  Hardware -Demand  transfer. In this example, the following 
settings apply.  The settings of the  addresses of the transfer source and transfer destination as well as the 
transfer data width are omitted.  
⋅   Transfer mode  :  Hardware-Demand transfer   
   (ST=0, IS=  Peripheral at the transfer request source,  MS=10) 
⋅   Transfer data size  :  Number of blocks = 1, Number of transfers  = 3 (BC=0,  TC=2)  
 
Figure  3-3 Example of Operation of  Hardware- Demand Transfer  
 
Hardware-Demand transfer mode
Transfer action
TC(reload)210
BC(reload)
0
Start request  from CPU
Transfer normal end
Transfer request
1st Transfer request from Peripheral
2
0
  
 
The operation of Hardware-
Demand transfer is as follows:  
The start of the operation is instructed by specifying the transfer content from CPU. DMAC waits  for a 
transfer request from the Peripheral. After receiving the transfer request, it performs one transfer and then 
waits for the next transfer request. During the wait period, a Transfer Gap is generated. Every time a 
transfer request is received, it per forms the same operation for the number of transfers (TC+1) . The total 
number of transfers to be performed is (TC+1) . Add the number of transfer requests from the Peripheral and 
the number of DMAC transfers ( TC+1). Once all of the transfers are completed, DMAC notifies CPU of the 
completion.  
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3.4.  Hardware-Block Transfer & Burst Transfer 
This section describes Hardware- Block transfer and Burst transfer. 
Hardware-Block transfer or Hardware -Burst transfer is used when performing DMA transfer by the transfer 
reques t signal from the Peripheral of the base timer or external interrupt.  
Hardware- Block transfer and Hardware- Burst transfer are methods used to receive the transfer request 
signal at the rising edge of the signal. Transfer is executed, when the rising edge o f the transfer request 
signal is detected. DMAC ’s transfer start timing can be specified by the output of the interrupt signal from 
each Peripheral.  
Figure  3-4 shows an example of the operation of Hardware -Block transfer. In this example, the following 
settings apply.  The settings of the addresses of the transfer source and transfer destination as well as the 
transfer data width are omitted.  
⋅   Transfer mode  :  Hardware-Block transfer   
   (ST=0, IS=  Peripheral at the transfer request so urce, MS=00)  
⋅   Transfer data size  :  Number of blocks = 4, Number of transfers = 3 (BC=3,  TC=2)  
 
Figure  3-4 Example of Operation of  Hardware- Block Transfer  
 
Transfer action
TC(reload)210
BC(reload)
3
T ransfer normal end
T
ransfer request
1st Transfer request from Peripheral
2
Hardware-Block transfer mode
Start request  from CPU
210321032103
  
 
The operation of H ardware-Block transfer is as follows:  
The start of the operation is instructed by specifying the transfer content from CPU. DMAC waits for a 
transfer request from the Peripheral. After receiving the transfer request, it performs transfer s for the 
number of blocks (=BC+1) and then wait s for th e next transfer request. During the wait period, a Transfer 
Gap is generated. Every time a transfer request is received, it performs the same operation for the number of 
transfers (TC+1). The total number of transfers to be performed is (BC+1)  x  (TC+1). Ad d the number of 
transfer requests from the Peripheral and the number of DMAC transfers (TC+1). Once all of the transfers 
are completed, DMAC notifies CPU of the completion.    
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Figure  3-5 shows an example of the oper ation of Hardware-Burst transfer.. In this example, the following 
settings apply. The settings of the addresses of the transfer source and transfer destination as well as the 
transfer data width are omitted.  
⋅   Transfer mode  :  Hardware-Burst transfer   
   (ST=0 , IS= Peripheral at the transfer request source,  MS=01) 
⋅   Transfer data size  :  Number of blocks =4, Number of transfers = 5  (BC=3, TC=4)  
 
Figure  3-5 Example of Operation of Hardware-B urst Transfer  
 
Transfer action
TC(reload)432
BC(reload)
3
T ransfer normal end
T
ransfer request
1st Transfer request from Peripheral
1
Hardware-Burst transfer mode
21032102103
Start request  from CPU
32102103
04
3
  
 
The operation  of  Hardware- Burst transfer is as follows:  
The start of the operation is instructed by specifying the transfer content from CPU. DMAC waits for a 
transfer request from the Peripheral. After receiving the  first transfer request,  it performs all of the trans fers 
for the number of times calculated by (BC+1)  x  (TC+1) . During the Hardware -Burst transfer, no Transfer 
Gap is generated. Once all of the transfers are completed, DMAC notifies CPU of the completion.  
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