Fujitsu Series 3 Manual
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5. Registers
[Bit 12 or 11, or bit 4 or 3] CS1, CS0: PPG DOWN Counter Operation Clock Select bits
Sets an operation clock of PPGs DOWN Counter.
Bit 12 or 4 Bit 11 or 3 Function
0 0 PCLK [Initial value]
0 1 PCLK/4
1 0 PCLK/16
1 1 PCLK/64
[Bit 10 or 9, or bit 9 or 1] MD1, MD0: PPG Operation Mode Set bits PPG output value can be set to be reversed.
Bit 10 or 9 Bit 9 or 1 Function
0 0 Sets 8-bit operation mode. [Initial value]
0 1 Sets 8+8-bit operation mode.
1 0 Sets 16-bit...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-677.png "Page 678
5. Registers
[Bit 12 or 11, or bit 4 or 3] CS1, CS0: PPG DOWN Counter Operation Clock Select bits
Sets an operation clock of PPGs DOWN Counter.
Bit 12 or 4 Bit 11 or 3 Function
0 0 PCLK [Initial value]
0 1 PCLK/4
1 0 PCLK/16
1 1 PCLK/64
[Bit 10 or 9, or bit 9 or 1] MD1, MD0: PPG Operation Mode Set bits PPG output value can be set to be reversed.
Bit 10 or 9 Bit 9 or 1 Function
0 0 Sets 8-bit operation mode. [Initial value]
0 1 Sets 8+8-bit operation mode.
1 0 Sets 16-bit...")
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5. Registers
[Bit 1] STRGn: Select trigger bit n (where, n=0, 4, 8, or 12) Selects an operation trigger signal for PPGn.
Bit Function
0 Start by the TRG Register setting. [Initial value]
1 Start by GATE signal from the multifunction timer.
[Bit 0] EDGEn: Start Effective Level Sele ct bit n (where, n=0, 4, 8, or 12)
Sets an effective level of GATEn signal from the multifunction timer.
Bit Function
0 Start at HIGH level. [Initial value]
1 Start at the LOW level.
FUJITSU SEMICONDUCTOR...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-682.png "Page 683
5. Registers
[Bit 1] STRGn: Select trigger bit n (where, n=0, 4, 8, or 12) Selects an operation trigger signal for PPGn.
Bit Function
0 Start by the TRG Register setting. [Initial value]
1 Start by GATE signal from the multifunction timer.
[Bit 0] EDGEn: Start Effective Level Sele ct bit n (where, n=0, 4, 8, or 12)
Sets an effective level of GATEn signal from the multifunction timer.
Bit Function
0 Start at HIGH level. [Initial value]
1 Start at the LOW level.
FUJITSU SEMICONDUCTOR...")
5. Registers 16+16-bit operation mode combination 15 87 0 PRLH0 PRLL0 Sets the HIGH width of PPG0. PRLH1 PRLL1 Sets the LOW width of PPG0. PRLH2 PRLL2 Sets the HIGH width of PPG0-pri. PRLH3 PRLL3 Sets the LOW width of PPG0-pri. Settings of PPGn channel (n=0, 4, 8, or 12) and PPGn+1 channels, PPGn+1 channel, or PPGn+2 channel The 16-bit length that combined PRLH with PRLL bits of PPGn set the HIGH width of PPGn. The 16-bit length that combined PRLH with PRLL bits of PPGn+1 set the LOW width of PPGn. The 16-bit length that combined PRLH with PRLL bits of PP Gn+2 set the HIGH pulse of PPGn prescaler. The 16-bit length that combined PRLH with PRLL bits of PPGn+3 set the LOW pulse of PPGn prescaler. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 645 MB9Axxx/MB9Bxxx Series
5. Registers 5.8. PPG Gate Function Control Registers (GATEC0/GATEC4/GATEC4/GATEC8/GATEC12) The GATEC Registers specify the start of the PPG using a GATE signal sent from the multifunction timer. GATEC Register configuration list 15 8 7 0 Initial value Access Corresponding PPG Reserved GATEC0 0x00 R/W PPG2, PPG0 Reserved GATEC4 0x00 R/W PPG6, PPG4 Reserved GATEC8 0x00 R/W PPG10, PPG8 Reserved GATEC12 0x00 R/W PPG14, PPG12 Register configuration (n=0, 4, 8, or 12) Bit 7 6 5 4 3 2 1 0 Field Reserved STRGn+2EDGEn+2 Reserved STRGn EDGEn Attribute - R/W R/W - R/W R/W Initial value - 1b0 1b0 - 1b0 1b0 Register functions [Bits 7:6] RES: Reserved bits 0b00 is read from these bits. Set these bits to 0b00 when writing. [Bit 5] STRGn+2: Select trigger bit 2 (n=0, 4, 8, or 12) Selects an operation trigger signal for PPGn+2. Bit Function 0 Start by the TRG Register setting. [Initial value] 1 Start by GATE signal from the multifunction timer. [Bit 4] EDGEn+2: Start Effective Level Select bit n+2 (where, n=0, 4, 8, or 12) Sets an effective level of GATEn+2 signal from the multifunction timer. Bit Function 0 Start at HIGH level. [Initial value] 1 Start at the LOW level. [Bits 3:2] RES: Reserved bits 0b00 is read from these bits. Set these bits to 0b00 when writing. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 646 MB9Axxx/MB9Bxxx Series
5. Registers [Bit 1] STRGn: Select trigger bit n (where, n=0, 4, 8, or 12) Selects an operation trigger signal for PPGn. Bit Function 0 Start by the TRG Register setting. [Initial value] 1 Start by GATE signal from the multifunction timer. [Bit 0] EDGEn: Start Effective Level Sele ct bit n (where, n=0, 4, 8, or 12) Sets an effective level of GATEn signal from the multifunction timer. Bit Function 0 Start at HIGH level. [Initial value] 1 Start at the LOW level. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 647 MB9Axxx/MB9Bxxx Series
6. Notes FUJITSU SEMICONDUCTOR LIMITED Chapter: PPG FUJITSU SEMICONDUCTOR CONFIDENTIAL 31 6. Notes This section explains the notes when using the PPG. PPG output operations When the PPG is operating, the pulses of LOW period and HIGH level period are continuously output. Once the pulse output has started, the PPG does not stop the output until PPG operation is stopped. A reset signal must be entered or the PPG stop setting must be set to stop the operation. The following explains PPG stop conditions. Start triggered by the Timing Generator Circuit Disable the start trigger by setting PPGC.TRGnO=0. Start triggered by GATE signal from the multifunction timer Disable the start trigger by setting GATE=0 (at HIGH edge detection) which is sent from the Multifunction timer. Start triggered by TRG Register writing Disable the start trigger by setting PEN=0. PPG operation mode setting The mode startup setting is selected by the MD bit setting of each PPGC Register. The MD bits must always be set to select the desired operation mode before the PPG is started. Other module settings PPG pulses are output via the I/O port of multifunctio n timer. The multifunction timer settings are explained in Chapter Multifunction Timer. For details on pulse output to I/O ports, see Chapter I/O Ports. Also, for details on interrupts, see Chapter Interrupts. Interrupts In 8-bit operation mode or 8+8-bit operation mode, when an underflow occurs on each counter, an interrupt request is issued for each of them. However, in 16-bit operation mode or 16+16-bit operation mode, when an underflow occurs on a 16-bit counter, the PUF(m) and PUF(m+1) bits are set simultaneously. Therefore, it is recommend to enable either of PIE(m) and PIE(m+1) bits to use a single interrupt source. Also, it is recommend to clear both PU F(m) and PUF(m+1) bits simultaneously to clear the cause of the interrupt (m=0, 2, 4, 6, 8, 10, 12, 14). CHAPTER 16-2: PPG MN706-00002-1v0-E 648 MB9Axxx/MB9Bxxx Series
1. Overview Chapter: Quad Position & Revolution Counter This chapter explains the functions and operations of the Quad Position & Revolution Counter (QPRC). 1. Overview 2. Configuration 3. Operations 4. Registers CODE: FX13-E02.1 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 649 MB9Axxx/MB9Bxxx Series
1. Overview 1. Overview The Quad Position & Revolution Counter is used to measure the position of Position Encoder. Also, it can be used as an up/down counter by its setting. The Quad Position & Revolution Counter contains a 16-bit position counter, a 16-bit revolution counter, two 16-bit compare registers, a control register, and its control circuit. Features of Quad Positi on & Revolution Counter The position counter can be operated in one of the following 3 counting modes: PC_Mode1 : Up/down count mode PC_Mode2 : Phase difference count mode (supporting the 2-time and 4-time frequency multiplication) PC_Mode3 : Count mode with direction The revolution counter can be operated in one of the following 3 counting modes: RC_Mode1 : The revolution counter can count up or down at a ZIN active edge only. RC_Mode2 : The revolution counter can count up or down with an output value of position counter only. RC_Mode3 : The revolution counter can count up or down both with an output value of position counter and a signal at ZIN active edge. A signal edge detection can be set fo r detecting an input event from three AIN, BIN and ZIN external pins Detection of falling edge Detection of rising edge Detection of both rising and falling edges The following two functions can be selected for input in ZIN pin Counter clear function Gate function An interrupt request can be generated if: The position counter value matches the Position Compare Register, The position counter value matches the Position an d Revolution Compare Register value, or the revolution counter value matches the Position and Revolution Compare Register value, The position counter underflows, The position counter overflows (that is, the positio n counter value matches the value of the QPRC Maximum Position Register), The position counter is reset at a ZIN active edge, The counting of position counter is inverted, The position counter matches the Position Compare Register value, and the revolution counter matches the Position and Revolution Compare Register value, or An outrange revolution counter value is detected. The following useful functions are provided for counting Swap function of AIN and BIN external pins Mask reset function of the position counter Count direction check function during position counter operation or during overflow/underflow occurrence FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 650 MB9Axxx/MB9Bxxx Series
2. Configuration 2. Configuration The following shows the configuration of Quad Position & Revolution Counter. Figure 2-1 Block diagram of Quad Position & Revolution Counter QPRC Maximum Position Register Interrupt Generator Circuit Peripheral buses Interrupt request Position Compare Register Position counter Control register/QPRC Extension Control Register Interrupt Control Register Revolution counter Position and Revolution Compare register Pin swapping Comparator Overflow/underflow Reset Comparator Edge detection Edge detection AIN BIN ZIN FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 651 MB9Axxx/MB9Bxxx Series
3. Operations 3. Operations This section explains the operation of Quad Position & Revolution Counter. Operation of position counter The position counter receives an input signal from AIN or BIN external pin as an event of count clock, and increments or decrements the counter. As listed in Table 3-1, the position counter can select a counting mode by setting of the position counter mode bits (QCR:PCM[1:0]) of a control register. The counting conditions depend on the selected count mode. The position counter is counted up or down in the following ZIN conditions only. If the ZIN function is set to the count clear function (QCR:CGSC=0) If the ZIN function is set to the Gate function (QCR:CGSC=1), the ZIN low-level detection (QCR:CGE[1:0]=01) is set, and the ZIN is logical low If the ZIN function is set to the Gate function (QCR:CGSC=1), the ZIN high-level detection (QCR:CGE[1:0]=10) is set, and the ZIN is logical high If the ZIN function is set to the Gate function (QCR:CGSC=1) and if a level other than ZIN high- or low-level detection (QCR:CGE[1:0]=00 or 11) is se t, the position counter is not counted up or down. Also, if the AIN and BIN configuration is swapped by SWAP bits of a control register, the AIN and BIN pins are swapped and the position counter is counted up or down. For example, if PC_Mode1 (QCR:PCM[1:0]=01) and AES[1:0]=10 (rising edge) and BES[1:0]=01 (falling edge) are set, the following occurs. If QCR:SWAP=0 and when a rising edge of AIN signal is detected, the position counter is counted up. If a falling edge of BIN signal is detected, the position counter is counted down. If QCR.SWAP=1, the position counter is counted down at a falling edge of AIN signal but it is counted up at a rising edge of BIN signal. Table 3-1 Counting conditions of AIN and BIN pin position counter Position count mode (PC_MODE) AIN counting conditions BIN counting conditions Count disable PC_Mode0:QCR:PCM[1:0]=00 Position counter disable Position counter disable Up/down counting PC_Mode1: QCR:PCM[1:0]=01 AIN Active edge BIN Active edge Phase difference count PC_Mode2:QCR:PCM[1:0]=10 AIN Active edge or high/low levelHigh/low level or BIN active edge Counting with direction PC_Mode3:QCR:PCM[1:0]=11 High/low level BIN Active edge The activ e edge of AIN signal and the active edge of BIN signal mean a rising edge, a falling edge, or both of the respectiv e si gnal if they are set by the AIN Detection Edge Select bits (QCR:AES[1:0]=01 or 10 or 11) or by the BIN Detection Edge Select bits (QCR:BES[1:0]=01 or 10 or 11). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 652 MB9Axxx/MB9Bxxx Series
3. Operations PC_Mode1: Up/down count mode An external signal entered from AIN or BIN external pin is receive d as the counting clock, and the position counter is counted up or down. In this mode, the position counter is counted up when an active edge of AIN signal is detected. When an active edge of BIN signal is detected, the position counter is counted down. Figure 3-1 Operations in up/down count mode (QCR:AES[1:0]=10, QCR:BES[1:0]=10, QCR:SWAP=0) 23432 +1 +1 +1 -1 -1 AIN BIN QPCR FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 653 MB9Axxx/MB9Bxxx Series
3. Operations PC_Mode2: Phase difference count mode (supporting the 2-time and 4-time frequency multiplication) This mode is useful for counting the difference between phases A and B of encoder output signal. If the phase-A and phase-B outputs are re spectively connected to the AIN and BIN pins and if phase A is leading phase B, the counter is counted up . If delayed, the counter is counted down. In this mode, when an active edge of AIN signal is detected, the BIN signal level is checked and the position counter counts it. In the opposite case, the position counter also counts it. Counting in the 4-time or 2-time frequency multiplication can be made by setting the AES and BES bits of QPRC Control Register (QCR). The counting in these frequency multiplication modes allows more accurate position measurement as its counting resolution is very high. Table 3-2 AES and BES bit settings in frequency multiplication mode Frequency multiplication mode AES[1:0] setting BES[1:0] setting 01 00 10 00 00 01 1-time frequency multiplication mode 00 10 11 00 2-time frequency multiplication mode 00 11 4-time frequency multiplication mode 11 11 Table 3-3 Counting in 2-time frequency multiplication mode (QCR:AES[1:0]=00, QCR:BES[1:0]=11, QCR:SWAP=0) Edge detection pin Detection edge Level Check pin Input level Counting direction Figure 3-2 Timing Rising edge High Up (1) Rising edge Low Down (2) Falling edge High Down (3) BIN Falling edge AIN Low Up (4) Figure 3-2 Operation in 2-time frequency multiplication mode (QCR:AES[1:0]=00, QCR:BES[1:0]=11, QCR:SWAP=0) 234 56 5 4 2 3 +1 +1 +1 +1 +1 -1 -1 -1 -1 AIN BIN QPCR (4) (1) (4) (1) (2) (3) (2) (3) (4) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 654 MB9Axxx/MB9Bxxx Series