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6. LIN Interface (ver. 2.1) Registers 
 
6.2.  Serial Mode Register (SMR) 
The Serial Mode Register (SMR) is used to set an operation mode, to select a transmission 
direction, data length, and stop bit length, and enable or disable an output of serial data to 
their pins. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SCR) MD2 MD1 MD0 WUCRSBL - - SOE 
Attribute     R/W R/W R/W  R/W R/W - - R/W 
Initial 
value     0 0 0 0 0 - 0 0 
 
[bit 7:5] MD2, MD1, MD0: Operation mode setting bits  These bits set an operation mode. 
0b000: Sets operation mode 0 (async normal mode). 
0b001: Sets operation mode 1 (async multiprocessor mode). 
0b010: Sets operation mode 2 (clock sync mode). 
0b011: Sets operation mode 3 (LIN communication mode). 
0b100: Sets operation mode 4 (I
2C mode). 
This section explains the registers and their operation in operation mode 3 (LIN communication mode). 
Bit 7  Bit 6Bit 5  Description 
0 0 0 Operation mode 0 (async normal mode) 
0  0 1 Operation mode 1 (async multiprocessor mode) 
0  1 0 Operation mode 2 (clock sync mode) 
0  1 1 Operation mode 3 (LIN communication mode) 
1 0 0  Operation mode 4 (I2C mode) 
* This section explains the registers in operation mode 3. 
 
  Any  b

it setting other than above is inhibited. 
   To switch th e cu

rrent operation mode, issue a programmable clear in struction (SCR:UPCL=1) and switch 
the operation mode continuously. 
   After the operation mode has been switched, set each register correctly. 
 
[bit 4] WUCR: Wake-up control bit  Selects a pin to be  

used for an external interrupt. 
If this bit is set to 0: The INT pin is set as an external interrupt pin. 
If set to 1: The SIN pin is set as an external interrupt pin. 
Bit Description 
0  Disables the Wake-up function. 
1  Enables the Wake-up function. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 3] SBL: Stop bit length select bit 
This bit sets a stop bit length (the frame end mark of the transmit data). 
If SBL=0 and ESCR:ESBL=0 are set: One (1) stop bit is set. 
If SBL=1 and ESCR:ESBL=0 are se t: Two (2) stop bits are set. 
If SBL=0 and ESCR:ESBL=1 are se t: Three (3) stop bits are set. 
If SBL=1 and ESCR:ESBL=1 are se t: Four (4) stop bits are set. 
Bit Description 
ESCR.ESBL=0 1  bit 0 
ESCR.ESBL=1 3 bits 
ESCR.ESBL=0 2  bits 1 
ESCR.ESBL=1 4 bits 
 
 
  In receive ope r

ation, only the first 
 bit of the stop bit data is detected. 
   Always set this bit when transmission is disabled (SCR:TXE=0). 
 
[bit 2:1] Reserved bit  This is an und e

fined bit. The read value is 0. Be sure to write 0. 
 
[bit 0] SOE: Serial data output enable bit  This bit enables or disables a serial data output. 
Bit Description 
0  Disables a serial data output. 
1  Enables a serial data output. 
 
 
If this 

bit is used as the SOUT pin, the GPIO must also be set. 
  
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6. LIN Interface (ver. 2.1) Registers 
 
6.3.  Serial Status Register (SSR) 
The Serial Status Register (SSR) is used to check the current transmission/reception state, 
check the Receive Error flag, detect an LIN Break field, and clear the Receive Error flag. 
 
bit 15 14 13 12 11 10 9 8 7 ... 0 
Field REC - LBD FRE ORE RDRFTDRETBI (ESCR) 
Attribute  R/W - R/W  R R  R R R    
Initial 
value  0 - 0 0 0 0 1 1    
 
[bit 15] REC: Receive Error flag clear bit  This bit clears the FRE and ORE flags of  the Serial Status Register (SSR). 
   If this bit is set to 1, the error flag is cleared. 
   This bit has no effect if set to 0. 
 
0 is always read during reading. 
Description Bit  During writing During reading 
0 No  effect. 
1 Clears the Receive Error flag (FRE, ORE).  0 is always read. 
 
[bit 14] Unused bit  This bit value is undefined when read. 
This bit has no effect when written. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 13] LBD: LIN Break field detection flag bit 
This bit shows a detection of LIN Break field. 
When 11-bit wide or more of serial input (SIN) are LOW , the LBD bit is set to 1. If the LIN Break field 
interrupt enable bit (LBIE) is 1 during this time, a status interrupt occurs. 
When read: 
If this bit is 1: An LIN Break field has been detected. 
If this bit is 0: An LIN Break field has not been detected. 
When written: 
If this bit is set to 0: The LBD bit is cleared to 0. 
If this bit is set to 1: No effect. 
Description Bit  During writing During reading 
0 Clears the LBD flag.  A Break field was not detected. 
1 No effect.  A Break field was detected. 
 
 
If a rea d

-modify-write instruction is issued, 1 is read. 
 [bit 12] FRE: Framing error flag bit    If a frami ng err

or occurs during data reception, this  bit is set to 1. If the REC bit of Serial Status 
Register (SSR) is set to 1, this flag is cleared. 
   If the FRE and RIE bits are 1, a r eceive interrupt request is output. 
   If this flag is set, data of the R eceive Data Register (RDR) is invalid. 
   If this flag is set when receive FIFO is used, the recei ve FIFO enable bit is cleared and the receive data is 
not stored in receive FIFO. 
 
Bit Description 
0  No framing error occurred. 
1  A framing error occurred. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 11] ORE: Overrun error flag bit 
  If an overrun occurs during data receptio n, this bit is set to 1. If the REC bit of Serial Status Register 
(SSR) is set to 1, this flag is cleared. 
   If the ORE and RIE bits are 1, a receive interrupt request is output. 
   If this flag is set, data in the R eceive Data Register (RDR) is invalid. 
   If this flag is set when receive FIFO is used, the recei ve FIFO enable bit is cleared and the receive data is 
not stored in receive FIFO. 
 
Bit Description 
0  No overrun error occurred. 
1 An overrun error occurred. 
 
[bit 10] RDRF: Receive data full flag bit    This flag shows the state of  Receive Data Register (RDR). 
   When the receive data is loaded in  the RDR, this bit is set to 1. When the Receive Data Register (RDR) 
is read, this bit is cleared to 0. 
   If the RDRF and RIE bits are 1, a  receive interrupt request is output. 
   If receive FIFO is used, the RDRF bit  is set to 1 when the preset amount of data is received in receive 
FIFO. 
   If receive FIFO is used, this bit is cleared to 0 when receiv e FIFO is emptied. 
 
Bit Description 
0  The Receive Data Register (RDR) is empty. 
1 The Receive Data Register (RDR) contains data. 
 
[bit 9] TDRE: Transmit data empty flag bit    This flag shows the state of  Transmit Data Register (TDR). 
   If the transmit data is written in the TDR, this bit is se t to 0 to indicate that the TDR contains valid data. 
When the data is loaded to the transmit shift register an d when the transmission is started, this bit is set to 
1 to indicate that the TDR does not contain the valid data. 
   If the TDRE and TIE bits are 1, a transmit interrupt request is output. 
   When the UPCL bit of Serial Control Register (SCR) is set to 1, the TDRE bit is set to 1. 
   For the TDRE bit set/clear timing wh en transmit FIFO is used, see 2.4 Interrupt and flag set timing when 
trans mit FIFO is used
. 
 
Bit Description 
0  The Transmit Data Register (TDR) contains data. 
1  The Transmit Data Register (TDR) is empty. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 8] TBI: Transmit bus idle flag bit 
  This bit indicates that the LIN interface (ver. 2.1) is not transmitting data. 
   When transmit data is written in the Transmit Data Register (TDR), this bit is set to 0. 
   When the LIN Break field is set (SMR :LBR=1), this bit is set to 0. 
   If the Transmit Data register (TDR) is empty (TDRE=1) an d if no transmission is started, this bit is set to 
1. 
   If the Transmit Data Register is emptied after the LIN Break field has been transmitted, this bit is set to 
1. 
   If this bit is 1 and if a transmit bus idle interrupt  is enabled (SCR:TBIE=1), a transmit interrupt request 
is output. 
 
Bit Description 
0  Data being transmitted 
1  No data transmission 
 
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6. LIN Interface (ver. 2.1) Registers 
 
6.4.  Extended Communication Control Register (ESCR) 
The Extended Communication Control Register (ESCR) is used to enable/disable an LIN 
Break field interrupt, detect an LIN Break field, set an LIN Break field length and a Break 
delimiter length, and select a stop bit length. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SSR) - ESBL- LBIE LBL1LBL0 DEL1 DEL0
Attribute      -  R/W  - R/W R/W R/W  R/W R/W 
Initial 
value     0 0 - 0 0 0 0 0 
 
[bit 7] Reserved bit  This is an undefined bit. The read value is 0. Be sure to write 0. 
 
[bit 6] ESBL: Extended stop bit length select bit  This bit sets a stop bit length (the frame end mark of the transmit data). 
If SBL=0 and ESCR:ESBL=0 are set: One (1) stop bit is set. 
If SBL=1 and ESCR:ESBL=0 are se t: Two (2) stop bits are set. 
If SBL=0 and ESCR:ESBL=1 are se t: Three (3) stop bits are set. 
If SBL=1 and ESCR:ESBL=1 are se t: Four (4) stop bits are set. 
Bit Description 
SMR.SBL=0 1  bit 0 
SMR.SBL=1 2 bits 
SMR.SBL=0 3  bits 1 
SMR.SBL=1 4 bits 
 
 
  In receive ope r

ation, only the first 
 bit of the stop bit data is detected. 
   Always set this bit when transmission is disabled (TXE=0). 
 
[bit 5] Unused bit  This bit  val

ue is undefined when read. 
This bit has no effect when written. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 4] LBIE: LIN Break field detect interrupt enable bit 
This bit enables or disables an LIN Break field detect interrupt. 
If the LIN Break field detect flag (LBD) is 1, a r eceive interrupt occurs when an interrupt is enabled 
(LBIE=1). 
Bit Description 
0  Disables an LIN Break field detect interrupt. 
1  Enables an LIN Break field detect interrupt. 
 
[bit 3:2] LBL1/0: LIN Break field length se lect bits (valid in master mode only) 
   These bits set an LIN Break field generation time (in number of bits). 
   This bit must be set before the LBR bit of Serial Control Register (SCR) is set to 1 (for LIN Break field 
transmission). 
   An LIN Break field is always detected at the 11th bit in the slave mode operation regardless of this bit 
setting. 
 
Bit 3  Bit 2 Description 
0 0  13 bits long 
0 1  14 bits long 
1 0  15 bits long 
1 1  16 bits long 
 
 
This  b

it setting is valid in the master mode operation only (SMR:MS=0). 
 [bit 1:0] DEL1/0: LIN Break delimiter length select bits (valid in ma ster mod
 e only) 
   These bits set an LIN Break delim iter length (in number of bits). 
   These bits must be set before the LBR bit of Serial Control Register (SCR) is set to 1 (for LIN Break 
field transmission). 
 
Bit 1  Bit 0 Description 
0 0  1 bit long 
0 1 2 bits long 
1 0 3 bits long 
1 1 4 bits long 
 
 
This  b

it setting is valid in the master mode operation only (SMR:MS=0). 
  
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6. LIN Interface (ver. 2.1) Registers 
 
6.5.  Receive Data Register/Transmit Data Register 
(RDR/TDR) 
The Receive and Transmit Data Registers are allocated at the same address. This register 
functions as the Receive Data Register when data  is read from it. This register functions as 
the Transmit Data Register when data is written in it. 
  Receive Data Register (RDR) 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field  D7 D6 D5 D4 D3 D2 D1 D0 
Attribute        R R  R R R  R R R 
Initial 
value      0 0 0 0 0 0 0 0 
 
The Receive Data Register (RDR) is a data  buffer register for serial data reception. 
   When serial data signals are sent to the Serial Input  pin (SIN pin), they are converted by a shift register 
and stored in the Receive Data Register (RDR). 
   When the receive data is stored in the Receive Data Register (RDR), the receive data full flag bit 
(SSR:RDRF) is set to 1. If a receive interrupt is  enabled (SSR:RIE=1), a receive interrupt request is 
generated. 
   The Receive Data Register (RDR) must be read only  when the receive data full flag bit (SSR:RDRF) is 
1. When data is read from the  Serial Receive Data Register (RDR ), the receive data full flag bit 
(SSR:RDRF) is cleared to 0 automatically. 
   If a receive error occurs (when SSR:ORE or FRE is 1), data in the Receive Data Register (RDR) 
becomes invalid. 
 
 
  If receive  FIFO is 

used and if the preset amount of data is received in  receive FIFO, t
 he RDRF bit is set 
to 1. 
   If receive FIFO is used and if this buffer is  emptied, the RDRF bit is cleared to 0. 
   If a receive error occurs when receive FIFO is used  (SSR:ORE or FRE is 1), the receive FIFO enable 
bit is cleared and the receive data is not stored in receive FIFO. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
  Transmit Data Register (TDR) 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field  D7 D6 D5 D4 D3 D2 D1 D0 
Attribute        W W  W W W  W W W 
Initial 
value      1 1 1 1 1 1 1 1 
 
The Transmit Data Register (TDR) is a data bu ffer register for serial data transmission. 
   If data transmission is enabled (SCR:TXE=1) and if the transmit data is written in the Transmit Data 
Register (TDR), the transmit data is transferred to the transmit shift register. Then, the data is converted 
into serial data, and output at the serial data output pin (SOUT pin). 
   When the transmit data is written in the Transmit Da ta Register (TDR), the transmit data empty flag 
(SSR:TDRE) is cleared to 0. 
   When the transmit data is transferred to the transmit sh ift register and data transmission is started, and if 
transmit FIFO is disabled or if tr ansmit FIFO is empty, the transmit data empty flag (SSR:TDRE) is set 
to 1. 
   If the transmit data empty flag (SSR:TDRE) is 1, the next transmit data can be written in the buffer. If a 
transmit interrupt is enabled, a transmit interrupt o ccurs. The next transmit data must be written only 
after the transmit interrupt has occurred or when  the transmit data empty flag (SSR:TDRE) is 1. 
   If the transmit data empty flag (SSR:TDRE) is 0 and  transmit FIFO is disabled or transmit FIFO is full, 
no transmit data can be written in the Transmit Data Register (TDR). 
 
 
  The T r

ansmit Data Register is a write-only register . While the Receive Data Register is a 
 read-only 
register. As these two registers are  allocated at the same address, the write and read values differ from 
each other. Therefore, the INC/DEC  instruction and other read-modify-write (RMW) instructions cannot 
be used. 
   For the transmit data empty flag (SSR:TDRE)  set timing when transmit FIFO is used, see 2.4 Interrupt 
and flag set  timing when transmit FIFO is used. 
 
 
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