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Fujitsu Series 3 Manual

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5.7.  Software Watchdog Clock Prescaler Register (SWC_PSR) 
The SWC_PSR sets the frequency division and enables the output of the software watchdog 
clock. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field TESTB Reserved SWDS 
Initial value 1’bx  -  2b00 
Attribute R/W  - R/W 
 Register functions 
[bit 7] TESTB: TEST bit 
Bit Description 
0 No permitting. 
1  Always written by “1”   
 
[bit 7:2] RES: Reserved bits 
0b100000 is read from these bits. 
Set these bits to 0b100000 when writing. 
[bit 1:0] SWDS: Software watchdog clock frequency division ratio setting bit 
Bit 1  Bit 0 Description 
0 0 Sets 1/1 frequency of PCLK0. [Initial value] 
0  1 Sets 1/2 frequency of PCLK0. 
1  0 Sets 1/4 frequency of PCLK0. 
1  1 Sets 1/8 frequency of PCLK0. 
 
 
  This reg i

ster is not initialized by software reset. 
   Be sure to set the bit 7 t o

 1 when writing a value to this register. 
 
 
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5.8.  Trace Clock Prescaler Register (TTC_PSR) 
The TTC_PSR sets the trace clock frequency division. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  TTC 
Initial value - 1b0 
Attribute -  R/W 
 Register functions 
[bit 7:1] RES: Reserved bits 
0b0000000 is read from these bits. 
Set these bits to 0b0000000 when writing. 
[bit 0] TTC: Trace clock frequency division ratio setting bit 
Bit Description 
0 1/1 [Initial value] 
1 1/2 
 
  This reg i

ster is not initialized by software reset. 
  
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5.9.  Clock Stabilization Wait Time Register (CSW_TMR) 
CSW_TMR sets the oscillation stabilization wait time of the main/sub clock. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved SOWT  MOWT 
Initial value -  3b000  4b0000 
Attribute - R/W  R/W 
 Register functions 
[bit 7] RES:    Reserved bits 
0b0 is read from this bit. 
Set this bit to 0b0 when writing. 
[bit 6:4] SOWT: Sub clock stabilization wait time setup bit 
Bit 6  Bit 5Bit 4  Description 
0 0 0 210/ FCL  :  Approx. 10.3 ms *  [Initial value] 
0 0 1 211/ FCL  :  Approx. 20.5 ms * 
0 1 0 212/ FCL  :  Approx. 41 ms * 
0 1 1 213/ FCL  :  Approx. 82 ms * 
1 0 0 214/ FCL  :  Approx. 164 ms * 
1 0 1 215/ FCL  :  Approx. 327 ms * 
1 1 0 216/ FCL  :  Approx. 655 ms * 
1 1 1 217/ FCL  :  Approx. 1.31 s * 
*: If FCL=100kHz 
[bit 3:0] MOWT: Main clock stabilization wait time setup bit 
Bit 3  Bit 2Bit 1 Bit 0  Description 
0 0 0 0 21 / FCH    :    Approx. 500 ns * [Initial value] 
0 0  0 1 
25 / FCH  :  Approx. 8  s * 
0 0  1 0 
26 / FCH  :  Approx. 16  s * 
0 0  1 1 
27 / FCH  :  Approx. 32  s * 
0 1  0 0 
28 / FCH  :  Approx. 64  s * 
0 1  0 1 
29 / FCH  :  Approx. 128  s * 
0 1  1 0 
210/ FCH  :  Approx. 256  s * 
0 1  1 1 
211/ FCH  :  Approx. 512  s * 
1 0  0 0 212/ FCH  :  Approx. 1.0 ms * 
1 0  0 1 213/ FCH  :  Approx. 2.0 ms * 
1 0  1 0 214/ FCH  :  Approx. 4.0 ms * 
1 0  1 1 215/ FCH  :  Approx. 8.0 ms * 
1 1  0 0 217/ FCH  :  Approx. 33.0 ms * 
1 1  0 1 219/ FCH  :  Approx. 131 ms * 
1 1  1 0 221/ FCH  :  Approx. 524 ms * 
1 1  1 1 223/ FCH  :  Approx. 2.0 s * 
*: If FCH=4MHz 
 
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   Set each oscillation stabilization wait time before enab ling the oscillation enable bit of the 
 SCM_CTL. 
If you change MOWT or SOWT while waiting for osc illation stability of each oscillator, each oscillation 
stabilization wait time is not guaranteed. 
   This register is not initialized by software reset. 
 
 
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5.10.  PLL Clock Stabilization Wait Time Setup Register (PSW_TMR) 
The PSW_TMR sets the PLL clock stabilization wait time. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  PINC Reserved POWT 
Initial value  - 1b0 -  3b000 
Attribute -  R/W -  R/W 
 Register functions 
[bit 7:5] RES: Reserved bits 
0b000 is read from these bits. 
Set these bits to 0b000 when writing. 
[bit 4] PINC: PLL input clock select bit 
Bit Description 
0  Selects CLKMO (main oscillation) [Initial value] 
1 Setting disabled 
Note: This bit must not be set to 1. Always set it to 0. 
[bit 3] RES: Reserved bit  0b0 is read from this bit. 
Set this bit to 0b0 when writing. 
[bit 2:0] POWT: PLL clock stabilization wait time setup bit 
Bit 2  Bit 1Bit 0  Description 
0 0 0 
29/ FCH   :  Approx. 128 s * [Initial value] 
0 0 1 
210/ FCH  :  Approx. 256 s * 
0 1 0 
211/ FCH  :  Approx. 512 s * 
0 1 1  212/ FCH  :  Approx. 1.02 ms * 
1 0 0 213/ FCH  :  Approx. 2.05 ms * 
1 0 1 214/ FCH  :  Approx. 4.10 ms * 
1 1 0 215/ FCH  :  Approx. 8.20 ms * 
1 1 1 216/ FCH  :  Approx. 16.40 ms * 
*: FCH=4MHz  
 
  Set each oscillation stab ilizati

on wait time before enab ling the oscillation enable  bit of the 
 SCM_CTL. 
If you change POWT while waiting for oscillation stability of the PLL oscillator, the oscillation 
stabilization wait time is not guaranteed. 
   This register is not initialized by software reset. 
 
 
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5.11.  PLL Control Register 1 (PLL_CTL1) 
The PLL_CTL1 sets the PLL frequency division ratio. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field PLLK  PLLM 
Initial value 4b0000  4b0000 
Attribute R/W  R/W 
 Register functions 
[bit 7:4] PLLK: PLL input clock frequency division ratio setting bit 
Bit 7:4  Description 
0000 
0001 
 
 
1111  The frequency division is 1/(PLLK+1). 
Example: PLLK=0000 +1 => 1/1 frequency [Initial value] 
 
[bit 3:0] PLLM: PLL VCO clock frequency division ratio setting bit 
Bit 3:0  Description 
0000 
0001 
 
 
1111 The frequency division is 1/(PLLM+1). 
Example: PLLM=0000 +1 => 1/1 frequency [Initial value] 
 
 
  Set each frequency di vision ratio be

fore enabling the PLL oscillation ena b
 le bit of the SCM_CTL. 
   This register is not initialized by software reset. 
 
 
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5.12.  PLL Control Register 2 (PLL_CTL2) 
The PLL_CTL2 sets the PLL frequency division ratio. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  PLLN 
Initial value   5b00000 
Attribute -  R/W 
 Register functions 
[bit 7:5] RES: Reserved bits 
0b000 is read from these bits. 
Set these bits to 0b000 when writing. 
[bit 4:0] PLLN: PLL feedback frequency division ratio setting bit 
Bit 4:0  Description 
00000 
00001 
・ 
・ 
11111  The frequency division is 1/(PLLN+1). 
Example: PLLN=00000 +1 => 1/1 division [Initial value] 
 
 
  Set the freq u

ency division ratio before enabling the PLL oscillation enable bit of the SCM_CTL. 
   This register is no t in

itialized by software reset. 
 
 
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5.13.  Debug Break Watchdog Timer Control Register (DBWDT_CTL) 
The DBWDT_CTL sets the watchdog timer count operation for debug mode tool break. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field DPHWBE  Reserved DPSWBE Reserved 
Initial value 1b0 1b0 1b0   
Attribute R/W - R/W   
 Register functions 
[bit 7] DPHWBE: HW-WDG debug mode break bit 
Bit Description 
0  HW-WDG stops counting at the tool break [Initial value] 
1 HW-WDG continues counting at the tool break 
 
[bit 6] RES: Reserved bit  0b0 is read from this bit. 
Set this bit to 0b0 when writing. 
[bit 5] DPSWBE: SW-WDG debug mode break bit 
Bit Description 
0  SW-WDG stops counting at the tool break [Initial value] 
1 SW-WDG continues counting at the tool break 
 
[bit 4:0] RES: Reserved bits  0b00000 is read  from these bits. 
Set these bits to 0b00000 when writing. 
 
This reg i

ster is not initialized by software reset. 
  
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5.14.  Interrupt Enable Register (INT_ENR) 
The INT_ENR enables/disables interrupts. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field  Reserved FCSE  Reserved PCSE SCSE MCSE 
Initial value     1b0    1b0 1b0 1b0 
Attribute     R/W    R/W R/W R/W 
 Register functions 
[bit 7:6] RES: Reserved bits 
0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 5] FCSE: Anomalous frequency detection interrupt enable bit   
Bit Description 
0 Disables FCS interrupts 
1  Enables FCS interrupts 
[bit 4:3] RES: Reserved bits 
0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 2] PCSE: PLL oscillation stabili zation completion interrupt enable bit 
Bit Description 
0 Disables PLL oscillation stabilization completion interrupts 
1 Enables PLL oscillation stabilization completion interrupts 
 
[bit 1] SCSE: Sub oscillation stabiliza tion completion interrupt enable bit   
Bit Description 
0 Disables sub oscillation stabilization completion interrupts 
1 Enables sub oscillation stabilization completion interrupts 
 
[bit 0] MCSE: Main oscillation stabilization completion interrupt enable bit   
Bit Description 
0  Disables main oscillation stabilization completion interrupts 
1 Enables main oscillation stabilization completion interrupts 
 
 
For Anom a

lous frequency detection, see Chapter Clock supervisor. 
After each clock oscillation enable turn ON, then stabilization c o

mpletion interrupt is available. 
  
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5.15.  Interrupt Status Register (INT_STR) 
The INT_STR indicates the status of interrupts. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field  Reserved FCSI  Reserved PCSI SCSI MCSI 
Initial value     1b0    1b0 1b0 1b0 
Attribute     R    R R R 
 Register functions 
[bit 7:6] RES: Reserved bits 
0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 5] FCSI: Anomalous frequency detection interrupt status bit 
Bit Description 
0  No FCS interrupt has been asserted. 
1 An FCS interrupt has been asserted. 
 
[bit 4:3] RES: Reserved bits  0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 2] PCSI: PLL oscillation stabiliza tion completion interrupt status bit 
Bit Description 
0 No PLL oscillation stabilization completion interrupt has been asserted. 
1 A PLL oscillation stabilization completion interrupt has been asserted. 
 
[bit 1] SCSI: Sub oscillation stabiliza tion completion interrupt status bit   
Bit Description 
0 No sub oscillation stabilization completion interrupt has been asserted. 
1 A sub oscillation stabilization completion interrupt has been asserted. 
 
[bit 0] MCSI: Main oscillation stabilization completion interrupt status bit   
Bit Description 
0  No main oscillation stabilization completion interrupt has been asserted. 
1 A main oscillation stabilization completion interrupt has been asserted. 
 
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