Fujitsu Series 3 Manual
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3. I/O Mode I/O mode 2 (Shared external trigger mode) This mode shares the input signals (ECK/TGIN/ TIN) of the base timer between two channels. Ta b l e 3 - 8 shows the external pins used when this mode is selected. Table 3-8 External pins used when I/O mode 2 is selected. Even channel Odd channel Number of input pins 1 (shared by two channels) Number of output pins 1 1 Ta b l e 3 - 9 shows the internal signals to which the external pins connect, and signals input or output. Table 3-9 External pin connections and input/output signals when I/O mode 2 is selected. External pin I/O Connected to (internal signal) Signal input/output TIOAn Output Even channel TOUT Outputs the even channel waveform TIOAn+1 Output Odd channel TOUT Outputs the odd channel waveform TIOBn Input ECK/TGIN/TIN of even and odd channels * Input to both the even and odd channels (synchronized by the peripheral clock (PCL K)) and used as one of the following signals: External clock (ECK signal) External startup trigger (TGIN signal) Waveform to be measured (TIN signal) TIOBn+1 - - Not used n : Even * : The usage of input signals (ECK/TGIN/TIN) differs depending on the Timer Control Register (TMCR) setting of the base timer. Figure 3-3 shows the block diagram of I/O mode 2 (Shared external trigger mode). Figure 3-3 I/O mode 2 (Shared external trigger mode) block diagram ECK TGIN TIN TOUT ECK TGIN TIN TOUT Base timer Ch.n+1 Base timer Ch.nTIOBn+1 TIOAn+1 TIOBn TIOAn COUT n: Even Table 3-10 shows signal connections in I/O mode 2. Table 3-10 I/O mode 2 signal connections Signal Connected to Remarks Ch.n TOUT signal Output from the TIOAn pin Input signal from the TIOBn pin Input to Ch.n and Ch.n+1 as ECK/TGIN/TIN signals Output to another channel as a COUT signal Synchronized by the peripheral clock (PCLK) Ch.n+1 TOUT signal Output from the TIOAn+1 pin n : Even FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 395 MB9Axxx/MB9Bxxx Series
3. I/O Mode If two channels above the channels set to this mode (n+2, n+3) are set to I/O mode 3 (Shared channel signal trigger mode) , the input signals (ECK/TGIN/TIN) can be input to the 4 channels simultaneously. (Example: If channels 0 and 1 are set to this mode, and channels 2 and 3 are set to I/O mode 3, input signals (ECK/TGIN/TIN) can be input to four channels of 0 to 3 simultaneously.) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 396 MB9Axxx/MB9Bxxx Series
3. I/O Mode I/O mode 3 (Shared channel signal trigger mode) This mode inputs the COUT signal from channels below the two channels as a CIN signal, and uses it as ECK/TGIN/TIN signals. Ta b l e 3 - 11 shows the external pins used when this mode is selected. Table 3-11 External pins used when I/O mode 3 is selected. Even channel Odd channel Number of input pins Not used Number of output pins 1 1 Table 3-12 shows the internal signals to which the external pins connect, and signals input or output. Table 3-12 External pin connections and input/output signals when I/O mode 3 is selected. External pin I/O Connected to (internal signal) Signal input/output TIOAn Output Even channel TOUT Outputs the even channel waveform TIOAn+1 Output Odd channel TOUT Outputs the odd channel waveform TIOBn TIOBn+1 - - Not used n : Even Figure 3-4 shows the block diagram of I/O mode 3 (Shared channel signal trigger mode). Figure 3-4 I/O mode 3 (Shared channel signal trigger mode) block diagram ECK TGIN TIN TOUT ECK TGIN TIN TOUT Base timer Ch.n+1 Base timer Ch.nTIOBn+1 TIOAn+1 TIOBn TIOAn COUT CIN n: Even Table 3-13 shows signal connections in I/O mode 3. Table 3-13 I/O mode 3 signal connections Signal Connected to Ch.n TOUT signal Output from the TIOAn pin CIN signal * Input to Ch.n and Ch.n+1 as ECK/TGIN/TIN signals Output to another channel as a COUT signal Ch.n+1 TOUT signal Output from the TIOAn+1 pin n : Even * : The COUT signal from another channel is input as a CIN signal. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 397 MB9Axxx/MB9Bxxx Series
3. I/O Mode The following shows Ch.n-2/n-1 signals that can be input to ECK/TGIN/TIN of Ch.n/n+1. Signal that the peripheral clock generates by synchronizing TIOBn-2 input in I/O mode 2. Trigger signal input from Ch.n-4/n-3 in I/O mode 3. TIOAn-2 output in I/O mode 4. TIOAn-2 output in I/O mode 6. TIOAn-2 output in I/O mode 7. Trigger signal input from Ch.n-4/n-3 in I/O mode 8. Select t he rising edge as a trigger input edge using the EGS1 and EGS0 bits in the Timer Control Register (TMCR) of the base t imer. (Set EGS1 and EGS0 to 0b01.) The channels set to this mode use the COUT signal from lower two channels (n-2 and n-1) as a CIN signal. (Example: If channels 2 and 3 are set to this mode, they use the COUT signal from channels 0 and 1.) Therefore, channels 0 and 1 cannot be set to this mode. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 398 MB9Axxx/MB9Bxxx Series
3. I/O Mode I/O mode 4 (Timer start/stop mode) This mode can control the start/stop of the odd channel using the even channel. The odd channel starts on the rising edge of output waveform (TOUT signal) of the even channel, and stops on the falling edge. Table 3-14 shows the external pins used when this mode is selected. Table 3-14 External pins used when I/O mode 4 is selected. Even channel Odd channel Number of input pins 1 Not used Number of output pins 1 1 Table 3-15 shows the internal signals to which the external pins connect, and signals input or output. Table 3-15 External pin connections and input/output signals when I/O mode 4 is selected. External pin I/O Connected to (internal signal) Signal input/output TIOAn Output Even channel TOUT Outputs the even channel waveform TIOAn+1 Output Odd channel TOUT Outputs the odd channel waveform TIOBn Input ECK/TGIN/TIN of even channel * Input to the even channel and used as one of the following signals: External clock (ECK signal) External startup trigger (TGIN signal) Waveform to be measured (TIN signal) TIOBn+1 - - Not used n : Even * : The usage of input signals (ECK/TGIN/TIN) differs depending on the Timer Control Register (TMCR) setting of the base timer. Figure 3-5 shows the block diagram of I/O mode 4 (Timer start/stop mode). Figure 3-5 I/O mode 4 (Timer start/stop mode) block diagram DTRG ECK TGIN TIN TOUT ECK TGIN TIN TOUT Base timer Ch.n+1 Base timer Ch.nTIOBn+1 TIOAn+1 TIOBn TIOAn COUT n: Even FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 399 MB9Axxx/MB9Bxxx Series
3. I/O Mode Table 3-16 shows signal connections in I/O mode 4. Table 3-16 I/O mode 4 signal connections Signal Connected to Ch.n TOUT signal Output from the TIOAn pin Input to Ch.n+1 as ECK/TGIN/TIN and DTRG signals Output to another channel as a COUT signal Input signal from the TIOBn pin Input to Ch.n as ECK/TGIN/TIN signals Ch.n+1 TOUT signal Output from the TIOAn+1 pin n : Even Select the risi ng edge as a trigger input edge of the odd channel using the EGS1 and EGS0 bits in the Time r C ontrol Register (TMCR) of the base timer. (Set EGS1 and EGS0 to 0b01.) The odd channel stops operating when a fallin g edge is detected in the DTRG signal. Figure 3-6 shows example operation when I/O mode 4 (T imer start/stop mode) is selected , and when channels 0 and 1 are used as PWM timer. Base timer Ch.0 Set value Base timer Ch.1 Set value Cycle Setup Register (PCSR) 0x0010Cycle Setup Register (PCSR) 0x0002 Duty Setup Register (PDUT) 0x0009Duty Setup Register (PDUT) 0x0001 Timer Control Register (TMCR) 0x0013Timer Control Register (TMCR) 0x0112 Figure 3-6 I/O mode 4 (Timer start/stop mode) block diagram Peripheral clock (PCLK) TIOA0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 TIOA1 Ch.1 is operatingCh.1 starts Ch.1 stops Ch.1 retains the timer value when it stops FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 400 MB9Axxx/MB9Bxxx Series
3. I/O Mode I/O mode 5 (Software-based simultaneous startup mode) This mode starts up multiple channels simultaneously using the Software-based Simultaneous Startup Register (BTSSSR). All the channels corresponding to the Software-based Simultaneous Star tup Register (BTSSSR) bits that have been set to 1 start up simultaneously. Table 3-17 shows the external pins used when this mode is selected. Table 3-17 External pins used when I/O mode 5 is selected. Even channel Odd channel Number of input pins Not used Number of output pins 1 1 Table 3-18 shows the internal signals to which the external pins connect, and signals input or output. Table 3-18 External pin connections and input/output signals when I/O mode 5 is selected. External pin I/O Connected to (internal signal) Signal input/output TIOAn Output Even channel TOUT Outputs the even channel waveform TIOAn+1 Output Odd channel TOUT Outputs the odd channel waveform TIOBn TIOBn+1 - - Not used n : Even Figure 3-7 shows the block diagram of I/O mode 5 (Software-based simultaneous startup mode). Figure 3-7 I/O mode 5 (Software-based simultaneous startup mode) block diagram ECK TGIN TIN TOUT ECK TGIN TIN TOUT Base timer Ch.n+1 Base timer Ch.nTIOBn+1 TIOAn+1 TIOBn TIOAn Software startup signal (SSSRn + 1 bit) Software startup signal (SSSRn bit) n: Even Table 3-19 shows signal connections in I/O mode 5. Table 3-19 I/O mode 5 signal connections Signal Connected to Ch.n TOUT signal Output from the TIOAn pin Software startup signal (Write 1 to the SSSRn bit in the BTSSSR) Input to Ch.n as ECK/TGIN/TIN signals Ch.n+1 TOUT signal Output from the TIOAn+1 pin Software startup signal (Write 1 to the SSSRn+1 bit in the BTSSSR) Input to Ch.n+1 as ECK/TGIN/TIN signals n : Even BTSSSR : Software-based Simultaneous Startup Register FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 401 MB9Axxx/MB9Bxxx Series
3. I/O Mode When 1 is written to a Software-based Simultaneous Startup Register (BTSSSR) bit, a rising edge is input (ECK/TGIN/TIN signals) to the channel corresponding to the bit. Select t he rising edge as a trigger input edge using the EGS1 and EGS0 bits in the Timer Control Register (TMCR) of the base tim e r. (Set EGS1 and EGS0 to 0b01.) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 402 MB9Axxx/MB9Bxxx Series
3. I/O Mode I/O mode 6 (Software-based startup and timer start/stop mode) This mode can control the start/stop of the odd channel using the even channel. The even channel can be started by writing 1 to the Software-based Simultaneous Startup Register (BTSSSR). The odd channel starts when the rising edge is detected in output waveform (TOUT signal) of the even channel, and stops when the falling edge is detected. Table 3-20 shows the external pins used when this mode is selected. Table 3-20 External pins used when I/O mode 6 is selected. Even channel Odd channel Number of input pins Not used Number of output pins 1 1 Table 3-21 shows the internal signals to which the external pins connect, and signals input or output. Table 3-21 External pin connections and input/output signals when I/O mode 6 is selected. External pin I/O Connected to (internal signal) Signal input/output TIOAn Output Even channel TOUT Outputs the even channel waveform TIOAn+1 Output Odd channel TOUT Outputs the odd channel waveform TIOBn TIOBn+1 - - Not used n : Even Figure 3-8 shows the block diagram of I/O mode 6 (Software-based startup and timer start/stop mode). Figure 3-8 I/O mode 6 (Software-based startup and timer start/stop mode) block diagram DTRG ECK TGIN TIN TOUT ECK TGIN TIN TOUT Base timer Ch.n+1 Base timer Ch.nTIOBn+1 TIOAn+1 TIOBn TIOAn COUT Software startup signal (SSSRn bit) n: Even FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 403 MB9Axxx/MB9Bxxx Series
3. I/O Mode Table 3-22 shows signal connections in I/O mode 6. Table 3-22 I/O mode 6 signal connections Signal Connected to Ch.n TOUT signal Output from the TIOAn pin Input to Ch.n+1 as EC K/TGIN/TIN/DTRG signals Output to another channel as a COUT signal Software startup signal (Write 1 to the SSSRn bit in the BTSSSR) Input to Ch.n as ECK/TGIN/TIN signals Ch.n+1 TOUT signal Output from the TIOAn+1 pin n : Even BTSSSR : Software-based Simultaneous Startup Register When 1 is written to the Software-based Simultane ous Startup Register (BTSSSR) bit corresponding to the even channel you want to start up, a rising edge is input (ECK/TGIN/TIN signals) to the channel. The start/stop timing of Ch.n is the same as that for I/O mode 4. Select t he rising edge as a trigger input edge using the EGS1 and EGS0 bits in the Timer Control Register (TMCR) of the base t imer. (Set EGS1 and EGS0 to 0b01.) The odd channel stops operating when a fallin g edge is detected in the DTRG signal. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 404 MB9Axxx/MB9Bxxx Series