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    							 FUJITSU SEMICONDUCTOR LIMITED 
 If FIFO is used 
Figure 6-3 An example flowchart for master/slave type communications (if FIFO buffer is used) 
 
(Master CPU)
Start
Set the operation mode.
(Set to mode 1.)
- Enable the transmit/
receive FIFO.
- Setting FBYTE 
No
Set the AD bit to 1.
Set the AD bit to 0.
Read and process  the FBYTE data.
Set the D8 bit to 0.  
Yes (Slave CPU)
Start
Set the operation mode. (Set to mode 1.)
RDRF=1
Set FBYTE to N.
AD = 1 and the 
slave address  match.
No
No
Yes
Yes
Set a slave address to 
transmit FIFO and set  the FDRQ bit to 0.
Set N bytes in transmit 
FIFO, and set the FDRQ bit  to 0.
RDRF=1
Enable the transmit/ receive FIFO.
Set FBYTE to 1.
No
Yes
Receive FIFO full
Read and process the FBYTE data.
Set N bytes in transmit FIFO, and set the FDRQ bit to 0.
Transmits the slave  address.  
Send data.
Send data.
  
 
 
CHAPTER  19-2: UART  \050Async  Serial Interface\051 
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7. UART (Async Serial Interface) Registers 
 
7.  UART (Async Serial Interface) Registers 
This section provides a list of UART (Async Serial Interface) registers. 
 UART (Async Serial Interface) registers list 
 
Table 7-1 UART (Async Serial Interface) register list 
 bit 15                           bit 8bit 7                            bit 0
SCR (Serial Control Register)  SMR (Serial Mode Register) 
SSR (Serial Status Register) ESCR (Extended Communication Control Register)
TDR1/RDR1 (Transmit/Receive Data Register 1)TDR0/RDR0 (Transmit/Receive Data Register 0)
BGR1 (Baud Rate Generator Register 1) BGR0 (Baud Rate Generator Register 0) 
UART 
- - 
FCR1 (FIFO Control Register 1)  FCR0 (FIFO Control Register 0) FIFO 
FBYTE2 (FIFO2 Byte Register)  FBYTE1 (FIFO1 Byte Register) 
 
Table 7-2 UART (Async Serial Interface) bit assignment 
 Bit 15  Bit 14 Bit 13Bit 12  Bit 11 Bit 10 Bit 09Bit 08 Bit 07 Bit 06Bit 05 Bit 04 Bit 03 Bit 02  Bit 01Bit 00
SCR/ 
SMR  UPCL - - RIE TIE TBIERXETXEMD2MD1MD0WUCRSBL BDS - SOE
SSR/ 
ESCR  REC - PEFRE ORE RDRFTDRETBIFLWENESBLINVPENP L2 L1 L0
TDR/ 
(RDR)  - D8
(AD) D7 D6D5D4 D3 D2 D1 D0
BGR1/ 
BGR0  EXT B14 B13B12 B11 B10B9 B8B7 B6 B5 B4 B3 B2 B1 B0
- - 
- 
FCR1/ 
FCR0 FTST1 FTST0 - FLSTE FRIIE FDRQFTIE
FSEL- FLSTFLDFSETFCL2 FCL1 FE2FE1
FBYTE2/ 
FBYTE1 FD15 FD14 FD13FD12 FD11 FD10FD9FD8FD7FD6FD5FD4FD3 FD2 FD1FD0
 

 Operation mode 
UART (Async Serial Interface) operates in two different modes. The Serial Mode Register (SMR) 
determines the mode to be enabled, depending on its setting, MD2, MD1 or MD0. 
Table 7-3 UART (Async Serial Interface) operation modes 
Operation mode  MD2 MD1 MD0 Type 
0 0 0 0 UART0 (async normal mode) 
1  0 0 1 UART1 (async multiprocessor mode) 
 
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7. UART (Async Serial Interface) Registers 
 
7.1.  Serial Control Register (SCR) 
The Serial Control Register (SCR) can perform transmit/receive enable/disable, 
transmit/receive interrupt enable/disable, transmit bus idle interrupt enable/disable and UART 
reset operations. 
 bit 15 14 13 12 11 10 9 8 7 ... 0 
Field UPCL - - RIE TIE TBIE RXE TXE (SMR) 
Attribute  R/W - - R/W R/W  R/W R/W R/W    
Initial 
value  0 - - 0 0 0 0 0    
 
[bit 15] UPCL: Programmable Clear bit  Initializes the UART internal state. 
If set to 1, 
  UART is reset directly (software  reset). However, the current register settings are maintained. The 
transmit or receive state is  disconnected immediately. 
   The baud rate generator reloads the BGR1/0 register value and restarts operation. 
   All of transmit/receive interrupt  causes (SSR:PE, FRE, ORE, RDRF , TDRE and TBI) are initialized 
(to 0b000011). 
  
RTS  signal is cleared to LOW. 
 
If set to 0, it has no effect. 
0 is always read during reading. 
Description Bit  During writing During reading 
0 No  effect. 
1 Programmable  clear 0 is always read. 
 
 
  Disable an i n

terrupt first, and then execute the progra mmable clear inst
 ruction. 
   If the FIFO operation is used, disable it (FCR0:FE2,  FE1=0) first and then execute Programmable Clear. 
 
[bit 14, 13] Unused bits  This bit val u

e is unknown when read. 
This bit has no effect when written. 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 12] RIE: Receive interrupt enable bit   This bit enables or disables an output  of receive interrupt request to the CPU. 
   If the RIE bit and the receive data flag bit (SSR:RDRF) are 1, or if any of the  error flag bits (SSR:PE, 
ORE or FRE) is 1, a receive  interrupt request is output. 
 
Bit Description 
0  Disables the receive interrupt. 
1  Enables the receive interrupt. 
 
[bit 11] TIE: Transmit interrupt enable bit    This bit enables or disables an output of Transmit Interrupt Request to the CPU. 
   If the TIE and SSR:TDRE bits are 1, a Transmit Interrupt Request is output. 
 
Bit Description 
0  Disables a transmit interrupt. 
1  Enables a transmit interrupt. 
 
[bit 10] TBIE: Transmit bus idle interrupt enable bit    This bit enables or disables an output of tr ansmit bus idle interrupt request to the CPU. 
   If the TBIE bit and TBI bit are 1, a tran smit bus idle interrupt request is output. 
 
Bit Description 
0 Disables the transmit bus idle interrupt. 
1 Enables the transmit bus idle interrupt. 
 
[bit 9] RXE: Receive operation enable bit  Enables or disables UART receive operation. 
  If set to 0, receive operation is disabled. 
   If set to 1, receive operation is enabled. 
 
Bit Description 
0  Disables data reception. 
1  Enables data reception. 
 
 
  Reception is not started un less the falling edge of the sta

rt bit 
 (in NRZ format, when ESCR:INV=0) is 
input even if reception is enabled (RXE=1). (In th e inverted NRZ format (ESCR:INV=1), reception is 
not started unless the falling edge is input. 
   If data reception is disabled (RXE=0), the cu rrent data reception is stopped immediately. 
   When receive operation is disabled (RXE=0), 
RTS  signal is fixed to LOW. 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 8] TXE: Transmit operation enable bit Enables or disables UART transmit operation. 
  If set to 0, transmit operation is disabled. 
   If set to 1, transmit operation is enabled. 
 
Bit Description 
0  Disables the transmission. 
1  Enables the transmission. 
 
 
If data  t

ransmission is disabled (TXE=0), the current data transmission is stopped immediately. 
  
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7. UART (Async Serial Interface) Registers 
 
7.2.  Serial Mode Register (SMR) 
The Serial Mode Register (SMR) is used to set operation mode, transfer direction data length 
and to select the stop bit length as well as to enable/disable output of serial data to their pins. 
 bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SCR) MD2 MD1 MD0 WUCRSBL BDS - SOE 
Attribute     R/W R/W R/W  R/W R/W R/W  - R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7:5] MD2, MD1, MD0: Operation mode set bit  Sets operation mode of the Async Serial Interface. 
0b000 : Sets operation mode 0 (async normal mode). 
0b001 : Sets operation mode 1 (async multiprocessor mode). 
0b010 : Sets operation mode 2 (clock sync mode). 
0b011 : Sets operation mode 3 (LIN communication mode). 
0b100 : Sets operation mode 4 (I
2C mode). 
This section explains the registers and their operation in operation mode 0 (async normal mode) and in 
operation mode 1 (async multiprocessor mode). 
Bit 7  Bit 6Bit 5  Description 
0 0 0 Operation mode 0 (async normal mode) 
0  0 1 Operation mode 1 (async multiprocessor mode) 
0  1 0 Operation mode 2 (clock sync mode) 
0  1 1 Operation mode 3 (LIN communication mode) 
1 0 0  Operation mode 4 (I2C mode) 
* This section explains the registers and their operation in Operation mode 0 and in operation mode 1. 
 
  Any b it settin

g other than above is inhibited. 
   To switch the cu rren

t operation mode, issue a programmable clear in struction (SCR:UPCL=1) and switch 
the operation mode continuously. 
   After the operation mode has been switched, set each register correctly. 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 4] WUCR: Wake-up control bit Selects a pin to be used for an external interrupt. 
If set to 0, the INT pin is set as an external interrupt pin. 
If set to 1, the SIN pin is set as an external interrupt pin. 
Bit Description 
0  Disables the Wake-up function. 
1  Enables the Wake-up function. 
 
[bit 3] SBL: Stop bit length select bit  This bit sets a stop bit length (the frame end mark of the transmit data). 
If set to SBL=0 and ESCR:ESBL=0, the stop bit length is set to one bit. 
If set to SBL=1 and ESCR:ESBL=0, the stop bit length is set to two bits. 
If set to SBL=0 and ESCR:ESBL=1, the stop bit length is set to three bits. 
If set to SBL=1 and ESCR:ESBL=1, the  stop bit length is set to four bits. 
Bit Description 
ESCR.ESBL=0 1  bit 0 
ESCR.ESBL=1 3 bits 
ESCR.ESBL=0 2  bits 1 
ESCR.ESBL=1 4 bits 
 
 
  In receive operation, only the first bit of the
  stop bit data is detected. 
   Always set this bit when transmission is disabled (SCR:TXE=0). 
 
[bit 2] BDS: Transfer direction select bit  Specifies to transmit th e least sig

nificant bit of the transmit serial data first (LSB first; BDS=0) or the most 
significant bit first (MSB first; BDS=1). 
Bit Description 
0  LSB first (The least significant bit is first transferred.) 
1 MSB first (The most significa nt bit is first transferred.) 
 
 
Set this b it when

 transmission and recep tion are di
 sabled (SCR:TXE=0, SCR:RXE=0). 
 
[bit 1] Reserved bit  This is an unde fin

ed bit. The read value is 0. Be sure to write 0. 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 0] SOE: Serial data output enable bit This bit enables or disables a serial data output. 
Bit Description 
0  Disables a serial data output. 
1  Enables a serial data output. 
 
 
If this  b

it is used as the SOUT pin, the GPIO must also be set. 
  
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7. UART (Async Serial Interface) Registers 
 
7.3.  Serial Status Register (SSR) 
The Serial Status Register (SSR) is used to check the current transmission/reception state, 
check the receive error flag, and clears the receive error flag. 
 bit 15 14 13 12 11 10 9 8 7 ... 0 
Field REC - PE FRE ORE RDRFTDRETBI (ESCR) 
Attribute  R/W - R R  R R R R    
Initial 
value  0 - 0 0 0 0 1 1    
 
[bit 15] REC: Receive error flag clear bit  This bit clears the PE, FRE and ORE flags  of the Serial Status Register (SSR). 
   If this bit is set to 1, the error flag is cleared. 
   This bit has no effect if set to 0. 
 
0 is always read during reading. 
Description Bit  During writing During reading 
0 No  effect. 
1 Clears the receive error flag (PE, FRE, ORE). 0 is always read. 
 
[bit 14] Unused bit  This bit value is undefined when read. 
This bit has no effect when written. 
 
[bit 13] PE: Parity error flag bit (only functions in operation mode 0)    If a parity occurs during data reception with SMR:PEN=1,  this bit is set to 1. This is cleared if the REC 
bit of Serial Status Register (SSR) is set to 1. 
   If the PE bit and SCR:RIE bit are 1,  a receive interrupt request is output. 
   If this flag is set, data in the R eceive Data Register (RDR) is invalid. 
   If this flag is set when receive FIFO is used, the recei ve FIFO enable bit is cleared and the receive data is 
not stored in receive FIFO. 
 
Bit Description 
0  No parity error occurred. 
1 No parity error occurred. 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 12] FRE: Framing error flag bit   If a framing error occurs during data reception, this b it is set to 1. This is cleared if the REC bit of 
Serial Status Register (SSR) is set to 1. 
   If the FRE bit and SCR:RIE bit are 1, a receive interrupt request is output. 
   If this flag is set, data in the R eceive Data Register (RDR) is invalid. 
   If this flag is set when receive FIFO is used, the recei ve FIFO enable bit is cleared and the receive data is 
not stored in receive FIFO. 
 
Bit Description 
0  No framing error occurred. 
1  A framing error occurred. 
 
[bit 11] ORE: Overrun error flag bit    If an overrun occurs during data receptio n, this bit is set to 1. This is cleared if the REC bit of Serial 
Status Register (SSR) is set to 1. 
   If the ORE and SCR:RIE bits are 1, a receive interrupt request is output. 
   If this flag is set, data in the R eceive Data Register (RDR) is invalid. 
   If this flag is set when receive FIFO is used, the recei ve FIFO enable bit is cleared and the receive data is 
not stored in receive FIFO. 
 
Bit Description 
0  No overrun error occurred. 
1 An overrun error occurred. 
 
[bit 10] RDRF: Receive data full flag    This flag shows the state of  Receive Data Register (RDR). 
   When the receive data is loaded in  the RDR, this bit is set to 1. When data is read from the Receive 
Data Register (RDR), this bit is cleared to 0. 
   If the RDRF bit and SCR:RIE  bit are 1, a receive interrupt request is output. 
   If the receive FIFO is used and if a certain count of  data is received by the receive FIFO, the RDRF bit is 
set to 1. 
   If receive FIFO is used, if both of the following co nditions are satisfied, and if the Receive Idle state 
continues more than 8 baud rate clocks, the RDRF bit is set to 1. 
  The receive FIFO idle detection  enable bit (FCR1:FRIIE) is 1. 
   The preset data amount is not received an d some data remains in receive FIFO. 
If the RDR data is read during counting of 8 clocks, this counter is reset to 0, and counting for 8 
clocks is restarted. 
   If the receive FIFO is used and if this buffer  is emptied, this bit is cleared to 0. 
 
Bit Description 
0 The Receive Data Register (RDR) is empty. 
1 The Receive Data Register (RDR) contains data. 
 
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