Fujitsu Series 3 Manual
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5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 41
5.2. Entire DMAC Configuration Register (DMACR )
This section describes entire DMAC configuration re gister (DMACR).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field DE DS - PR DH[3:0] - - - - - - - -
Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-255.png "Page 256
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 41
5.2. Entire DMAC Configuration Register (DMACR )
This section describes entire DMAC configuration re gister (DMACR).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field DE DS - PR DH[3:0] - - - - - - - -
Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...")
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5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 42
[bit29] Reserved
[bit28] PR : Priority Rotation This bi t controls the order of transfer priority among channels.
When this bit is set to "0" , the priority order is fixed for all of the channels.
When this bit is set to "1" , the priority order is determined in a rotation method for all of the channels.
bit28 Function
0 Fixes the priority order....](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-256.png "Page 257
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 42
[bit29] Reserved
[bit28] PR : Priority Rotation This bi t controls the order of transfer priority among channels.
When this bit is set to \"0\" , the priority order is fixed for all of the channels.
When this bit is set to \"1\" , the priority order is determined in a rotation method for all of the channels.
bit28 Function
0 Fixes the priority order....")
![Page 258
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 43
5.3. Configuration A Register (DMACA )
This section describes configuration A register (DMACA ).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field EB PB ST IS[5:0] - - - BC[3:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field TC[15:0]
Attribute R/W
Initial
Va l...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-257.png "Page 258
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 43
5.3. Configuration A Register (DMACA )
This section describes configuration A register (DMACA ).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field EB PB ST IS[5:0] - - - BC[3:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field TC[15:0]
Attribute R/W
Initial
Va l...")
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5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAP TER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 44
This bit can be used to put a transfer on pause without resetting the configuration register of the relevant
channel.
bit30 Function
0 Cancels the pause of the transfer of the relevant channel.
1 Puts the transfer of the relevant channel on pause.
[bit29] ST : Software Trigger
This bit is used to generate a software transfer request for an individual channel.
When this bit is set...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-258.png "Page 259
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAP TER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 44
This bit can be used to put a transfer on pause without resetting the configuration register of the relevant
channel.
bit30 Function
0 Cancels the pause of the transfer of the relevant channel.
1 Puts the transfer of the relevant channel on pause.
[bit29] ST : Software Trigger
This bit is used to generate a software transfer request for an individual channel.
When this bit is set...")
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5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 45
bit28:23 Function
110100 IDREQ[20]
110101 IDREQ[21]
110110 IDREQ[22]
110111 IDREQ[23]
111000 IDREQ[24]
111001 IDREQ[25]
111010 IDREQ[26]
111011 IDREQ[27]
111100 IDREQ[28]
111101 IDREQ[29]
111110 IDREQ[30]
111111 IDREQ[31]
Setting other
than above Setting prohibited
[bit22:20] : Reserved
[bit19:16] BC : Block Count
These bits specify the number of blocks for...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-259.png "Page 260
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 45
bit28:23 Function
110100 IDREQ[20]
110101 IDREQ[21]
110110 IDREQ[22]
110111 IDREQ[23]
111000 IDREQ[24]
111001 IDREQ[25]
111010 IDREQ[26]
111011 IDREQ[27]
111100 IDREQ[28]
111101 IDREQ[29]
111110 IDREQ[30]
111111 IDREQ[31]
Setting other
than above Setting prohibited
[bit22:20] : Reserved
[bit19:16] BC : Block Count
These bits specify the number of blocks for...")
![Page 261
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 46
5.4. Configuration B Register (DMACB)
This section describes configuration B register ( DMACB).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field - MS[1:0] TW[1:0] FS FD RC RS RD EI CI SS[2:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field - - - - - - -...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-260.png "Page 261
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 46
5.4. Configuration B Register (DMACB)
This section describes configuration B register ( DMACB).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field - MS[1:0] TW[1:0] FS FD RC RS RD EI CI SS[2:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field - - - - - - -...")
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5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 47
[bit24] FD : Fixed Destination
This bit specifies whether to increment or fix the transfer destination address.
bit24 Function
0 Increments the transfer destination address according to TW. (Initial value)
1 Fixes the transfer destination address.
[bit23] RC : Reload Count (BC/TC reload)
This bit controls the reload function of BC and TC.
When this bit is set to "1" , the...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-261.png "Page 262
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 47
[bit24] FD : Fixed Destination
This bit specifies whether to increment or fix the transfer destination address.
bit24 Function
0 Increments the transfer destination address according to TW. (Initial value)
1 Fixes the transfer destination address.
[bit23] RC : Reload Count (BC/TC reload)
This bit controls the reload function of BC and TC.
When this bit is set to \"1\" , the...")
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5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 48
[bit20] EI :Error Interrupt (unsuccessful transfer completion interrupt enable)
This bit enables or disables the notification of an interrupt when a transfer has been unsuccessfully
completed.
When this bit is set to "1", an interrupt is issued if SS is in the following status upon completion of the
transfer.
⋅ Address overflow
⋅ Stop by transfer stop request from a...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-262.png "Page 263
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 48
[bit20] EI :Error Interrupt (unsuccessful transfer completion interrupt enable)
This bit enables or disables the notification of an interrupt when a transfer has been unsuccessfully
completed.
When this bit is set to \"1\", an interrupt is issued if SS is in the following status upon completion of the
transfer.
⋅ Address overflow
⋅ Stop by transfer stop request from a...")
![Page 264
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 49
If various errors occur simultaneously, the termination code is indicated according to the following priority.
Highest
priority
Reset
Clearing by writing "000"
Address overflow
Stop request
Transfer source access error
Transfer destination access error
Lowest
priority
[bit15: 8] Reserved
When writing, always write " 0". "0" is always read....](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-263.png "Page 264
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 49
If various errors occur simultaneously, the termination code is indicated according to the following priority.
Highest
priority
Reset
Clearing by writing \"000\"
Address overflow
Stop request
Transfer source access error
Transfer destination access error
Lowest
priority
[bit15: 8] Reserved
When writing, always write \" 0\". \"0\" is always read....")
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5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 50
5.5. Transfer Source Address Register ( DMACSA)
This section describes transfer source address register (DMACSA ).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field DMACSA[31:16]
Attribute R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field DMACSA[15:0]
Attribute R/W
Initial
Va l u e 0 0 0 0 0 0 0...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-264.png "Page 265
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 50
5.5. Transfer Source Address Register ( DMACSA)
This section describes transfer source address register (DMACSA ).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field DMACSA[31:16]
Attribute R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field DMACSA[15:0]
Attribute R/W
Initial
Va l u e 0 0 0 0 0 0 0...")
![Page 266
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 51
5.6. Transfer Destination Address Register (DMACDA )
This section describes transfer destination address register ( DMACDA).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field DMACDA[31:16]
Attribute R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field DMACDA[15:0]
Attribute R/W
Initial
Va l u e 0 0 0 0...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-265.png "Page 266
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 51
5.6. Transfer Destination Address Register (DMACDA )
This section describes transfer destination address register ( DMACDA).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field DMACDA[31:16]
Attribute R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field DMACDA[15:0]
Attribute R/W
Initial
Va l u e 0 0 0 0...")
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 46 5.4. Configuration B Register (DMACB) This section describes configuration B register ( DMACB). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field - MS[1:0] TW[1:0] FS FD RC RS RD EI CI SS[2:0] Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0 Initial Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field - - - - - - - - - - - - - - - EM Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [bit31:30] Reserved [bit29:28] MS : Mode Select These bits select the transfer mode. bit29:28 Function 00 Block transfer mode (Initial value) 01 Burst transfer mode 10 Demand transfer mode 11 Reserved [bit27:26] TW : Transfer Width These bits specify the bit width of transfer data. bit27:26 Function 00 Byte (8bit) (Initial value) 01 Half-word (16bit) 10 Word (32bit) 11 Reserved [bit25] FS : Fixed Source This bit s pecifies whether to increment or fix the transfer source address. bit25 Function 0 Increments the transfer source address according to TW. (Initial value) 1 Fixes the transfer source address. CHAPTER 8: DMAC MN706-00002-1v0-E 225 MB9Axxx/MB9Bxxx Series
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 47 [bit24] FD : Fixed Destination This bit specifies whether to increment or fix the transfer destination address. bit24 Function 0 Increments the transfer destination address according to TW. (Initial value) 1 Fixes the transfer destination address. [bit23] RC : Reload Count (BC/TC reload) This bit controls the reload function of BC and TC. When this bit is set to "1" , the value set when the transfer started is reloaded to BC and TC upon completion of the transfer. bit23 Function 0 Disables the reload function of BC/TC. (Initial value) 1 Enables the reload function of BC/TC. [bit22] RS : Reload Source This bit controls the reload function of the transfer source address. When this bit is set to "1" , the value set when the transfer started is reloaded to DMACSA upon completion of the transfer. bit22 Function 0 Disables the reload function of the transfer source address. (Initial value) 1 Enables the reload function of the transfer source address. [bit21] RD : Reload Destination This bit controls the reload function of the transfer destination address (DMACDA) . When this bit is set to "1" , the value set when the transfer started is reloaded to DMACDA upon completion of the transfer. bit21 Function 0 Disables the reload function of the transfer destination address. (Initial value) 1 Enables the reload function of the transfer destination address. CHAPTER 8: DMAC MN706-00002-1v0-E 226 MB9Axxx/MB9Bxxx Series
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 48 [bit20] EI :Error Interrupt (unsuccessful transfer completion interrupt enable) This bit enables or disables the notification of an interrupt when a transfer has been unsuccessfully completed. When this bit is set to "1", an interrupt is issued if SS is in the following status upon completion of the transfer. ⋅ Address overflow ⋅ Stop by transfer stop request from a Peripheral, or the disabling of transfer by the EB/DE bit ⋅ Transfer source access error ⋅ Transfer destination access error bit20 Function 0 Disables an interrupt to be issued upon unsuccessful completion of transfer. (Initial value) 1 Enables an interrupt to be issued upon unsuccessful completion of transfer. [bit19] Completion Interrupt : (successful trans fer completion interrupt enable) This bit enables or disables the notification of an interrupt when a transfer has been successfully completed. When this bit is set to "1" , an interrupt is generated, if SS is set to successful completion upon completion of the transfer. bit19 Function 0 Disables an interrupt to be issued upon successful completion of transfer. (Initial value) 1 Enables an interrupt to be issued upon successful completion of transfer. [bit18:16] SS : Stop Status (stop status notification) These bits represent a code that indicates the stop status or completion status of a transfer. The following table shows the available codes. If a successful transfer completion interrupt or unsuccessful transfer completion interrupt is issued, the inte rrupt signal is deasserted by writing " 000" to these bits. bit18:16 Description 000 Initial value 001 Termination by transfer error (address overflow) 010 Termination by transfer stop request (stop by transfer stop request for Peripheral or the disabling of transfer by the EB/DE bit) 011 Termination by transfer error (transfer source access error) 100 Termination by transfer error (transfer destination access error) 101 Successful transfer completion 110 Reserved 111 Transfer on pause CHAPTER 8: DMAC MN706-00002-1v0-E 227 MB9Axxx/MB9Bxxx Series
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 49 If various errors occur simultaneously, the termination code is indicated according to the following priority. Highest priority Reset Clearing by writing "000" Address overflow Stop request Transfer source access error Transfer destination access error Lowest priority [bit15: 8] Reserved When writing, always write " 0". "0" is always read. [bit7:1] Reserved [bit0] EM : Enable bit Mask (EB bit clear mask) This bit is used to mask the clear of the EB bit (DMACA[31]) from DMAC upon completion of the transfer. In the case of EM=0 , DMAC clears the EB bit (DMACA[31]) to "0" upon completion of the transfer. In the case of EM=1 , it does not clear the EB bit upon completion of the transfer. This function allows transfers to be repeat ed without instruction from CPU. This function can only be used for hardware transfer. To use the function , enable the reload function of RC, RS and RD. bit0 Function 0 Clears EB upon completion of the transfer. (Initial value) 1 Does not clear EB upon completion of the transfer. CHAPTER 8: DMAC MN706-00002-1v0-E 228 MB9Axxx/MB9Bxxx Series
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 50 5.5. Transfer Source Address Register ( DMACSA) This section describes transfer source address register (DMACSA ). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field DMACSA[31:16] Attribute R/W Initial Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field DMACSA[15:0] Attribute R/W Initial Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [bit31:0] DMACSA : DMAC Source Address These bits specify the transfer start address of the transfer source. I t is not possible to set unaligned address to transfer data width (TW). The value of these bits can be read during the transfer. In the case of FS=1 , the transfer source address is set to a fixed value and no change occurs. In the cases of FS=0 and RS=0 , the value is incremented according to TW. Upon successful transfer completion, it is the next address after the transfer completion address. Upon unsuccessful transfer completion, it is the value set during the suspension. In the cases of FS=0 and RS=1 , it is incremented according to TW during the transfer. Upon completion of the transfer, the value set when the transfer started is reloaded. bit31:0 Function 32’hxxxxxxxx Specifies the transfer source address from which the transfer starts. (Initial value : 32’h00000000) CHAPTER 8: DMAC MN706-00002-1v0-E 229 MB9Axxx/MB9Bxxx Series
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 51 5.6. Transfer Destination Address Register (DMACDA ) This section describes transfer destination address register ( DMACDA). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field DMACDA[31:16] Attribute R/W Initial Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field DMACDA[15:0] Attribute R/W Initial Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [bit31:0] DMACDA : DMAC Destination Address These bits specify the transfer start address of the transfer destination . It is not possible to set unaligned address to transfer data width (TW). The value of these bits can be read during the transfer. In the case of FD=1 , the transfer destination address is set to a fixed value and no change occurs. In the cases of FD=0 and RD=0 , the value is incremented according to TW. Upon successful transfer completion, it is the next address after the transfer completion address. Upon unsuccessful transfer completion, it is the value set during the suspension. In the cases of FD=0 and RD=1 , it is incremented according to TW durin g the transfer. Upon completion of the transfer, the value set when the transfer started is reloaded. bit31:0 Function 32’hxxxxxxxx Transfer destination address from which DMA transfer starts (Initial value: 32’h00000000) CHAPTER 8: DMAC MN706-00002-1v0-E 230 MB9Axxx/MB9Bxxx Series
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 52 5.7. Notes on Register Setting Care must be taken on the following matters when setting the DMAC registers. ⋅ The DMACR, DMACA, DMACB, DMACSA and DMACDA registers can be accessed by byte, half -word and word. ⋅ The register address in DMAC cannot be set to the DMACSA or DMACDA register. ⋅ Channel setting registers cannot be changed during DMA transfer, except the DE/DH bits of DMACR , the EB/PB bits of DMACA and the EM bit of DMACB . CHAPTER 8: DMAC MN706-00002-1v0-E 231 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 232 MB9Axxx/MB9Bxxx Series
1. Overview CHAPTER: I/O PORT This chapter explains the I/O port. 1. Overview 2. Configuration, Block Diagram, and Operation 3. Setup Procedure Example 4. Register List 5. Usage Precautions CODE: 9BFGPIO-E02.3 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 233 MB9Axxx/MB9Bxxx Series
1. Overview 1. Overview This section provides an overview of the I/O port. The I/O port of this series provides the following features. The I/O port of this series shares the following functions. GPIO General-purpose I/O ports, which can read an inpu t level and set an output level from the CPU. Peripheral input/output Digital input/output signal ports of peripheral functions. Special I/O ports Analog input port An analog input port of an A/D converter. USB port Oscillation port The followings settings can be made for each pin. You can set whether the I/O port will be used as a GPIO, a digital pin of peripheral functions, or a special pin. You can set whether the I/O port will be used as an input port or an output port. You can enable or disable pull-up. Peripheral functions are assigned to two or more I/O ports with input/output of the same function. You can set to which I/O port the function can be allocated (relocation function). By setting registers, you can set the I/O port to Hi-Z status while the CPU is in standby mode. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MB9Axxx/MB9Bxxx Series MN706-00002-1v0-E 234