Fujitsu Series 3 Manual
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![Page 1086
FUJITSU SEMICONDUCTOR LIMITED
[bit 3] FCL2: FIFO2 reset bit
This bit resets the FIFO2 value.
If this bit is set to 1, the FIFO2 buffer is initialized.
Only the FCR0:FLST bit is initialized, but the other bits of FCR1/0 registers are kept.
Description Bit
During writing During reading
0 No effect. 0 is always read.
1 FIFO2 is reset.
Disable the FIFO2 operation first, and then reset the FIFO2 buffer.
Set the transmit FIFO interrupt enable bit to 0 before the execution.
The...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1085.png "Page 1086
FUJITSU SEMICONDUCTOR LIMITED
[bit 3] FCL2: FIFO2 reset bit
This bit resets the FIFO2 value.
If this bit is set to 1, the FIFO2 buffer is initialized.
Only the FCR0:FLST bit is initialized, but the other bits of FCR1/0 registers are kept.
Description Bit
During writing During reading
0 No effect. 0 is always read.
1 FIFO2 is reset.
Disable the FIFO2 operation first, and then reset the FIFO2 buffer.
Set the transmit FIFO interrupt enable bit to 0 before the execution.
The...")
![Page 1087
FUJITSU SEMICONDUCTOR LIMITED
[bit 1] FE2: FIFO2 operation enable bit
This bit enables or disables the FIFO2 operation.
To use the FIFO2 operation, set this bit to 1.
If receive FIFO is selected by the FCR1:FSEL bit and if a receive error has occurred, this bit is cleared to
0. This bit cannot be set to 1 until the receive error is cleared.
To use FIFO2 as transmit FIFO, this bit must be set to 1 or 0 when the transmit data is empty
(SSR:TDRE=1).
To use FIFO2 as receive FIFO, this...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1086.png "Page 1087
FUJITSU SEMICONDUCTOR LIMITED
[bit 1] FE2: FIFO2 operation enable bit
This bit enables or disables the FIFO2 operation.
To use the FIFO2 operation, set this bit to 1.
If receive FIFO is selected by the FCR1:FSEL bit and if a receive error has occurred, this bit is cleared to
0. This bit cannot be set to 1 until the receive error is cleared.
To use FIFO2 as transmit FIFO, this bit must be set to 1 or 0 when the transmit data is empty
(SSR:TDRE=1).
To use FIFO2 as receive FIFO, this...")
![Page 1088
FUJITSU SEMICONDUCTOR LIMITED
[bit 0] FE1: FIFO1 operation enable bit
This bit enables or disables the FIFO1 operation.
To use the FIFO1 operation, set this bit to 1.
If receive FIFO is selected by the FCR1:FSEL bit and if a receive error has occurred, this bit is cleared to
0. This bit cannot be set to 1 until the receive error is cleared.
To use FIFO1 as transmit FIFO, this bit must be set to 1 or 0 when the transmit data is empty
(SSR:TDRE=1).
To use FIFO1 as receive FIFO, this...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1087.png "Page 1088
FUJITSU SEMICONDUCTOR LIMITED
[bit 0] FE1: FIFO1 operation enable bit
This bit enables or disables the FIFO1 operation.
To use the FIFO1 operation, set this bit to 1.
If receive FIFO is selected by the FCR1:FSEL bit and if a receive error has occurred, this bit is cleared to
0. This bit cannot be set to 1 until the receive error is cleared.
To use FIFO1 as transmit FIFO, this bit must be set to 1 or 0 when the transmit data is empty
(SSR:TDRE=1).
To use FIFO1 as receive FIFO, this...")
1. Overview FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generati on FUJITSU SEMICONDUCTOR CONFIDENTIAL 2 Chapter: USB Clock Generation This chapter explains USB clock generation. 1. Overview 2. Configuration and Block Diagram 3. Explanation of Operation 4. Setup Procedure Example 5. Register List 6. Usage Precautions CODE: 9BFUSBPRE -E01. 2 CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1055 MB9Axxx/MB9Bxxx Series
1. Overview FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generation FUJITSU SEMICONDUCTOR CONFIDENTIAL 3 1. Overview This section provides an overview of the USB operating clock. The USB clock runs at 48 MHz and is used by USB macro for commu nication. An external 48 MHz clock can be used for the USB clock, or a 48 MHz clock can be generated with USB PLL. The USB clock generation unit is responsible for the following functions: ⋅ Enables or stops output of the USB clock. ⋅ Selects the USB clock. ⋅ En ables or stops oscillation of PLL macro. ⋅ Selects the input clock of PLL macro. ⋅ Sets the input clock frequency division of PLL macro. ⋅ Sets the input clock multiplication of PLL macro. ⋅ Sets the stabilization wait time of PLL macro. ⋅ Stops the USB clock in sta ndby mode. CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1056 MB9Axxx/MB9Bxxx Series
2. Configuration and Block Diagram FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generation FUJITSU SEMICONDUCTOR CONFIDENTIAL 4 2. Configuration and Block Diagram This section explains the configuration and block diagram of the USB operating clock generation unit. Figure 2-1 Block diagram of USB operating clock generation unit Operating Clock Control Register (UPLLEN) ⋅ The control register can enable oscillation. Input Clock Select Register (UPINC) ⋅ Be sure to select the main clock. USB- PLL ⋅ Frequency division setting (UPLLK, UPLLN) To generate a 48 MHz clock used for USB operation, the PLL clock output must be set to 96 MHz. By configuring the K frequency division and N frequency division, the USB -PLL clock must be set to 48 MHz. ⋅ Oscillation stabilization wait time setting (UPOWT) Oscillation stabilization wait time for USB -PLL can be specified. Output clock ⋅ Output Clock Select Register (UCSEL) Can be selected from the main clock and USB -P LL clo c k. ⋅ PLL Clock Output Enable Register (UCEN) Can enable the output of the USB -PLL clock. Standby mode setting ⋅ The Standby -Mode signal shown in Figure 2-1 turns to be active in the following modes. The USB clock stops in the following standby modes. ⋅ Stop mode ⋅ TIMER mode: ⋅ The Main Clock stable signal shown in Figure 2-1 is an oscillation stabilization signal for each mode. USB Clock 0 0 48MHz 1 1 Setting disable UCSEL UCEN Main Clock UPLLK 1/K PLL 1/2 UPINC 1/N Standby-Mode INT_UPLL UPOW T UPLLN Main Clock stable PLL Stable W ait Counter UPLLEN RST_N Fin 96MHz CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1057 MB9Axxx/MB9Bxxx Series
3. Explanation of Operation FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generation FUJITSU SEMICONDUCTOR CONFIDENTIAL 5 3. Explanation of Operation This section explains the operation of the USB operating clock generation unit. Selecting the USB operating clock The following two types of clocks can be selected for the USB operating clock. Selecting the main clock Select the main clock to use the main oscillation clock (CLKMO) directly as the USB clock. In this case, CLKMO must be input externally at 48 MHz, or must oscillate at 48 MHz. Enable the output of the USB clock after confirming stabilization of the CLKMO oscillation. Selecting the USB -PLL clock Select the USB -PLL clock to use it as the USB clock. The PLL VCO clock output must be set to 96 MHz and divided into two to generate a 48 MHz clock used for USB operation. The following Table 3-1 shows the frequency division ratio settings when the PLL clock output is set to 96 MHz. Table 3-1 Example PLL frequency division ratio settings Fin(MHz) K N 4 1 24 8 1 12 8 2 24 16 1 6 16 2 12 16 4 24 24 1 4 24 2 8 24 4 16 24 6 24 Changing to standby mode When changing to standby mode Before changing to standby mode (Stop mode or TIMER mode), set UCCR.UCEN to "0" to stop the USB clock supply. 1. Set UCCR.UCEN to "0". 2. Read the UCCR Register to check that UCEN is set to "0". 3. Changing to standby mode. When returning from standby mode, set UCEN to "1". The supply starts when the USB clock oscillation has been stabilized. Take either of the following actions to confirm whether or not the USB clock oscillation has been stabilized. a) When PLL macro is used Check that UPRDY is "1", or use the PLL macro oscillation stable wait interrupt. b) When main clock 48 MHz is used After the main clock oscillation has been stabilized, supply the USB clock. CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1058 MB9Axxx/MB9Bxxx Series
3. Explanation of Operation FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generation FUJITSU SEMICONDUCTOR CONFIDENTIAL 6 USB- PLL macro oscillation stabilization wait settings Oscillation stabilization wait time for USB -PLL can be specified After the main clock oscillation has been stabilized, the oscillation stabilization wait time for USB -P LL begins to be counted. Before enabling the USB -PLL oscillation, configure the oscillation stabilization wait time for USB -P LL a nd the oscillation stable complete interrupt.Do not change the oscillation stabilization wait time while waiting for oscillation to stabilize. CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1059 MB9Axxx/MB9Bxxx Series
4. Setup Procedure Example FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generation FUJITSU SEMICONDUCTOR CONFIDENTIAL 7 4. Setup Procedure Example This section explains an example of setting up the USB operating clock generation unit. Figure 4-1 shows an example of setting up the USB operating clock. Figure 4-1 USB operating clock generation procedure Start the register settings Set UCEN = 0 Read the UCCR Register Set UPINC Set UPOWT = 1 Set UPLLK Set UPLLN Set UPCSE = 0 Set UPCSC = 1 Set UPCSE = 1 Set UPLLEN = 1 Set UCEN = 1 Set USBEN = 1 End the register settings W hich is the source of USB clock output? Is INT_UPLL = 1?Is UPRDY = 1? Is UCEN = 0? Set UPLLEN = 0 Set the UCSEL Is an interrupt used? YES NO PLL oscillation clock (UCSEL = 1) CLKMC 48MHz(UCSEL = 0) YES NO NONO Set UPLLEN = 1 YESYES CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1060 MB9Axxx/MB9Bxxx Series
5. Register List FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generation FUJITSU SEMICONDUCTOR CONFIDENTIAL 8 5. Register List This section explains the register list of the USB operating clock generation unit. The register list of the USB operating clock generation unit. Abbreviation Register name See UCCR USB Clock Control Register 5.1 UPCR1 USB-PLL Control Register-1 5.2 UPCR2 USB-PLL Control Register-2 5.3 UPCR3 USB-PLL Control Register-3 5.4 UPCR4 USB-PLL Control Register-4 5.5 UP_STR USB-PLL Macro Status Register 5.6 UPINT_ENR USB-PLL Interrupt Enable Register 5.7 UPINT_CLR USB-PLL Interrupt Clear Register 5.9 UPINT_STR USB-PLL Interrupt Status Register 5.8 USBEN USB Enable Request Register 5.10 CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1061 MB9Axxx/MB9Bxxx Series
5. Register List FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generation FUJITSU SEMICONDUCTOR CONFIDENTIAL 9 5.1. USB Clock Setup Register (UCCR) The UCCR selects the USB clock and enables/disables the USB clock output. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved UCSEL UCEN Initial value - 1'b0 1'b0 Attribute - R/W R/W Register functions [bit 7:2] res: Reserved bits "0b000000" is read from these bits . Set these bits to "0b000000" when writing. [bit 1] UCSEL: USB clock select bit Bit Description 0 Main clock [Initial value] 1 PLL macro oscillation clock [bit 0] UCEN: USB clock output enable bit Bit Description 0 Disables the USB clock output [Initial value] 1 Enables the USB clock output < Notes > ⋅ When selecting the main clock with UCSEL, the 48 MHz frequency must be input from an external main oscillation. ⋅ This register is not initialized by software reset. CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1062 MB9Axxx/MB9Bxxx Series
5. Register List FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generation FUJITSU SEMICONDUCTOR CONFIDENTIAL 10 5.2. USB-PLL Control Register-1 (UPCR1) The UPCR1 sets PLL for USB. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved UPINC UPLLEN Attribute - R/W R/W Initial value - 1'b0 1'b0 Register functions [bit 7:2] res: Reserved bits "0b000000" is read from these bits. Set these bits to "0b 000000" when writing. [bit 1] UPINC: PLL macro input clock select bit. Bit Description 0 Main clock input [Initial value] 1 Setting disabled [bit 0] UPLLEN: USB -PLL macro oscillation enable bit Bit Description 0 Stops USB-PLL macro [Initial value] 1 Enables the USB-PLL macro oscillation < Notes > ⋅ Be sure to set UPINC to "0". Operation is not guaranteed when UPINC is set to "1". ⋅ This register is not initialized by software reset. CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1063 MB9Axxx/MB9Bxxx Series
5. Register List FUJITSU SEMICONDUCTOR LIMITED Chapter: USB Clock Generation FUJITSU SEMICONDUCTOR CONFIDENTIAL 11 5.3. USB-PLL Control Register-2 (UPCR2) The UPCR2 sets the oscillation stability wait time of PLL macro for USB. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved UPOWT Attribute - R/W Initial value - 3'b000 Register functions [bit 7:3] res: Reserved bits "0b000000" is read from these bits. Set these bits to "0b000000" when writing. [ bit 2:0] UPOWT: USB -PLL macro oscillation stabilization wait setting bit Bit 2 Bit 1 Bit 0 Description 0 0 0 29/Fin : Approx. 128 µs * [Initial value] 0 0 1 210/Fin : Approx. 256 µs * 0 1 0 211/Fin : Approx. 512 µs * 0 1 1 212/Fin : Approx. 1.02 ms * 1 0 0 213/Fin : Approx. 2.05 ms * 1 0 1 214/Fin : Approx. 4.10 ms * 1 1 0 215/Fin : Approx. 8.20 ms * 1 1 1 216/Fin : Approx. 16.4 ms * * : When Fin = 4 MHz < Notes > ⋅ Fin is the clock (main oscillation) selecte d by UPINC. ⋅ This register is not initialized by software reset. CHAPTER 20-1: USB Clock Generation MN706-00002-1v0-E 1064 MB9Axxx/MB9Bxxx Series