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4. Registers of Multifunction Timer 
 
Figure 4-2 FRT Counter Start and Stop (Up/Down-count Mode) 
 
FUJITSU SEMICONDUCTOR LIMITED 
 
FRT counter start , clear, stop ( up-down-count mode)
0x0000 
PEAK (=TCCP) 
FRT count time
  Start FRT (STOP=0, SCLR=0 )
Stop FRT (ST O

P=1, SCLR=1, TCDT=0x0000 )   
 
 
[bit7] TCSA.BFE 
Process Value  Function 
0 Disables TCCP’s buffer function. Write 
1 Enables TCCP’s buffer function. 
Read - Reads the register setting. 
 
TCSA.BFE is a register that specifies whether to enable  or disable the buffer function of the TCCP register. 
See  4.3.3 FRT Cycle Setting Register (TCCP) . 
[bit8] TCSA.I CRE 
Process Value 
Function 
0 Does not generate interrupt when 1 is set to TCSA.ICLR. Write 
1 Generates interrupt when 1 is set to TCSA.ICLR. 
Read - Read he register setting. 
 
TCSA.ICRE is a register that specifi es whether to notify CPU of the event that TCSA.ICLR is set as an 
interrupt (enabling interrupt) or not to notify it (disabling interrupt). 
See  5.2 Treatment of Event Detect Register and Interrupt . 
[bit9] TCSA.I CLR 
Process Value 
Function 
0 Clears this register to 0. Write 
1 Does nothing. 
0 Indicates that no match has been detected between FRT’s count value and TCCP 
value. 
Read 
1 Indicates that a match has already been detected between FRT’s count value and 
TCCP value. 
Read at RMW access 
1 is always read. 
 
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4. Registers of Multifunction Timer 
 
TCSA.ICLR is a register that is set to 1 when a match is detected between FRT’s count value and TCCP 
value during FRT operation (hereinafter  referred to as Peak value detection. 
By reading this register, whether FRT’s count value ha s reached the TCCP value or not can be determined. 
This register can be cleared by writing 0. 
This register does nothing, if 1 is written. Always  write 1 to the register when rewriting to another 
register in the same address area. 
1 is always read from this register at RMW access. 
See  5.2 Treatment of Event Detect Register and Interrupt . 
[bit12:10] Re served 
Process Function 
Write 
0 must be written at write access. 
Read 0 is read. 
 
[bit13] TCSA.IRQZE 
Process Value  Function 
0 Does not generate interrupt when 1 is set to TCSA.IRQZF. Write 
1 Generates interrupt, when  1 is set to TCSA.IRQZF. 
Read - Reads the register setting. 
 
TCSA.IRQZE is a register that specifies whether to no tify CPU of the event that TCSA.IRQZF is set as an 
interrupt (enabling interrupt) or not to notify it (disabling interrupt). 
See  5.2 Treatment of Event Detect Register and Interrupt . 
[bit14] TCSA.IRQZF 
Process Value  Function 
0 Clears this register to 0. Write 
1 Does nothing. 
0 Indicates that a match between FRT’s count value and 0x0000 has not been 
detected. 
Read 
1 Indicates that a match between FRT’s count value and 0x0000 has already 
been detected. 
Read at RMW access 
1 is always read. 
 
TCSA.IRQZF is a register that is set to 1 when  a match between FRT’s count value and 0x0000 has 
been detected (hereinafter referre d to as Zero value detection). 
By reading this register, whether FRT’s count value has reached 0x0000 or not can be determined. 
This register is not set at 0x0000 from which FRT starts counting or at 0x0000 to which the counter 
value has been cleared by TCSA.SCLR. 
This register can be cleared by writing 0. 
This register does nothing, if 1 is written. Always  write 1 to the register when rewriting to another 
register in the same address area. 
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4. Registers of Multifunction Timer 
 
1 is always read from this register at RMW access. 
See 5.2 Treatment of Event Detect Register and Interrupt . 
[bit15] TCSA.ECKE 
Process Value  Function 
0 Uses the internal clock (PCLK) as FRT’s count clock. Write 
1 Uses an external input clock (FRCK) as FRT’s count clock. 
Read - Reads the register setting. 
 
TCSA.ECKE is a register that selects the clock signal to be used as FRT’s count clock. 
Change the setting of this register while FRT is stopping. 
To select the internal clock, the clock division ratio must be set by TCSA.CLK[3:0]. 
To select an external input clock, the FRCK pin to be used in the GPIO block must be predetermined. 
To operate it with an external input clock, the count operation is performed both at the rising edge and 
falling edge of an external input clock signal. 
To operate it with an external input clock, the first edge from the external input clock after FRT operation 
starts (writing 0 to TCSA.STOP) is ignored, irre spective of the rising or falling edge, and the count 
operation starts from the next edge. 
Figure 4-3 Selection of External Input Clock 
 
 
External Input clock (FRCK)
TCSA.STOP reg.
FRT counter value
0x00000x00010x00020x0003
After STOP  ↓, 1st FRCK edge is ignored  
 
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4. Registers of Multifunction Timer 
 
4.3.2. FRT Control Register B (TCSB) 
TCSB is a 16-bit register that controls FRT. 
Each mounted channel has three registers: TCSB0, TCSB1 and TCSB2. 
TCSB0 controls FRTch0. 
TCSB1 controls FRTch1. 
TCSB2 controls FRTch2. 
 Configuration of Register 
Bit  15 14 13  12 11 10  9 8 
Field Reserved 
Attribute - 
Initial Value  0 0 0  0 0 0 0 0 
           
Bit  7 6 5  4 3 2 1 0 
Field Reserved  AD2E AD1E AD0E 
Attribute -  R/W R/W R/W 
Initial Value  0 0 0  0 0 0 0 0 
 
  Functions of Register 
[bit0] TCSB.AD0E 
Process Value  Function 
0 Does not output AD conversion start signal to ADCunit0 upon Zero value 
detection by FRT. 
Write 
1 Outputs AD conversion start signal to ADCunit0 upon Zero value detection 
by FRT. 
Read 
- Reads the register setting. 
 
[bit1] TCSB.AD1E 
Process Value  Function 
0 Does not output AD conversion start signal to ADCunit1 upon Zero value 
detection by FRT. 
Write 
1 Outputs AD conversion start signal to ADCunit1 upon Zero value detection 
by FRT. 
Read 
- Reads the register setting. 
 
[bit2] TCSB.AD2E 
Process Value  Function 
0 Does not output AD conversion start signal to ADCunit2 upon Zero value 
detection by FRT. 
Write 
1 Outputs AD conversion start signal to ADCunit2 upon Zero value detection 
by FRT. 
Read 
- Reads the register setting. 
 
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4. Registers of Multifunction Timer 
 
TCSB.AD0E, TCSB.AD1E and TCSB.AD2E are registers that select AD conversion start signal output 
upon Zero value detection by FRT. 
These registers are used to start ADC conversion upon Zero value detection by FRT. Each of the AD 
conversion start signals for the 3 channels of FRT undergoes logic OR by ADC unit to which they are to be 
output. See the entire block diagram. 
The conversion start signal from FRT ch.0, FRTch.1 and FRTch.2 to ADCunit0 has undergone logic OR. 
The conversion start signal from FRT ch.0, FRTch.1 and FRTch.2 to ADCunit1 has undergone logic OR. 
The conversion start signal from FRT ch.0, FRTch.1 and FRTch.2 to ADCunit2 has undergone logic OR. 
Due to the above configuration, attention must be paid when starting AD conversion from multiple FRT’s to 
the same ADC. To start AD conversion at FRT’s count value other than Zero value detection, ADCMP can 
be used to output the AD conversion start signal. 
It can be selected in the ATSA block whether to use the ADC conversion start signal achieved upon Zero 
value detection by FRT and the ADC conversion start signal achieved by ADCMP for starting ADC’s scan 
conversion or priority conversion. 
[bit15:3] Reserved 
Process Function 
Write  0 must be written at write access. 
Read 0 is read. 
 
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4. Registers of Multifunction Timer 
 
4.3.3. FRT Cycle Setting Register (TCCP) 
TCCP is a 16-bit register that sets FRT’s count cycle. 
Each mounted channel has three registers: TCCP0, TCCP1 and TCCP2. 
TCCP0 sets the cycle for FRTch0. 
TCCP1 sets the cycle for FRTch1. 
TCCP2 sets the cycle for FRTch2. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
Bit  15 14 13 12  11 10 9 8 7 6 5 4 3 2 1 0 
Field TCCP[15:0] 
Attribute R/W 
Initial  Va l u e   1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 
 
  Functions of Register 
[bit15:0] TCCP.TCCP[15:0] 
Process Function 
Write  Sets FRT’s cycle. Stores the written value to the TCCP buffer register. 
Read Reads the value in the TCCP register ( not the value in the TCCP buffer register). 
 
TCCP is a 16-bit register that sets FRT’s count cycle. 
Depending on the TCCP value and FRT’s count mode, FRT’s count cycle varies, as shown below. 
In Up-count mode:   
FRT’s count cycle = (TCCP+1) x FRT’s count clock cycle 
In Up/Down-count mode:   
FRT’s count cycle = TCCP x 2 x FRT’s count clock cycle 
When data is written to this address area, the data is fi rst stored in the buffer register. And then, the data is 
transferred from the buffer register to the TCCP register under the following conditions. 
When the buffer function is disabled: 
Data is transferred immediately after  it is written to the buffer register. 
When the buffer function is enabled: 
Data is transferred, when FRT is stopped or  when FRT’s count value has reached 0x0000. 
Whether the buffer function is enabled or disabled is  determined by the value in the TCSA.BFE register. 
FRT’s count cycle can be changed by rewriting this register during FRT’s count operation. If data is read 
from this address area, the value in the TCCP register  is read, rather than the value in the buffer register. 
Therefore, it should be noted that no bit can be  rewritten by RMW access to this address area when the 
buffer function is enabled. 
It is prohibited to write 0x0000 to this register. 
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4. Registers of Multifunction Timer 
 
Figure 4-4 shows an example of changing FRT’s cy cle when the buffer fun ction is enabled. 
When TCCP’s buffer function is enabled, a value writte n to the buffer register is transferred to the TCCP 
register upon the next Zero value detection. FRT’s c ount cycle is changed in the next FRT cycle after the 
writing. 
Figure 4-4 Example of Changing FRT’s Cycle (When Buffer Function is Enabled) 
 
FRT count
0x0000
0xFFFF
time
TCSA.BFE=1, TCCP Buffer reg. enable
0xBFFF0x7FFF
0xBFFF0x7FFF
TCCP Buf.reg.
TCCP reg.
0xBFFF0x7FFF
 
  Figure 4-5  shows an example of changing FRT’s cy cle when the
  buffer function is disabled. 
When TCCP’s buffer function is disabled, the value in  the buffer register is immediately reflected on the 
TCCP register; therefore, FRT’s cycle can be changed  in the same cycle in which the value was written. In 
this case, it should be noted that if a value smaller  than FRT’s count value is written as the TCCP value at 
this point, FRT’s counter counts up to 0xFFFF. 
Figure 4-5 Example of Changing FRT’s Cycle (When Buffer Function is Disabled) 
 
TCSA.BFE=0, TCCP Buffer reg. disable
FRT count
0x0000
0xFFFF
time
0xBFFF0x7FFF
0xBFFF0x7FFF
TCCP Buf.reg.
TCCP reg.
0xBFFF0x7FFF
 
 
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4. Registers of Multifunction Timer 
 
4.3.4. FRT Count Value Register (TCDT) 
TCDT is a 16-bit register that reads and writes FRT’s count value. 
Each mounted channel has three registers: TCDT0, TCDT1 and TCDT2. 
TCDT0 is the timer count value of FRT-ch.0. 
TCDT1 is the timer count value of FRT-ch.1. 
TCDT2 is the timer count value of FRT-ch.2. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
Bit  15 14 13 12  11 10 9 8 7 6 5 4 3 2 1 0 
Field TCDT[15:0] 
Attribute R/W 
Initial  Va l u e   0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
  Functions of Register 
[bit15:0] TCDT.TCDT[15:0] 
Process Value  Function 
0x0000 Sets FRT’s count value to 0x0000 (possible only when FRT is stopped). 
Write 
Other 
than 
above  Setting prohibited 
Read 
- Reads FRT’s current value. 
 
TCDT is a 16-bit register that reads and writes FRT’s count value. 
The value read from TCDT is FRT’s count value of that point. 
Do not write any data during FRT’s operation or a value other than 0x0000. 
If FRT is operated, and then stopped, make sure to write 0x0000 to TCDT and initialize FRT’s count 
value in order to prepare for its restart. 
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4. Registers of Multifunction Timer 
 
4.3.5. OCU Connecting FRT Select Register (OCFS) 
OCFS is an 8-bit register that selects and sets FRT to be connected to OCU. 
Each mounted channel has three registers: OCFS10, OCFS32 and OCFS54. 
OCFS10 controls OCU ch1 and OCU ch0. 
OCFS32 controls OCU ch3 and OCU ch2. 
OCFS54 controls OCU ch5 and OCU ch4. 
OCFS10 and OCFS54 are located at even-numbered addresses, while OCFS32 is located at 
an odd-numbered address. Therefore, their bit positions are [7:0] and [15:8]. 
 Configuration of Register 
Bit  15/7 14/6 13/5  12/4 11/3 10/2  9/1 8/0 
Field FSO1[3:0]  FSO0[3:0] 
Attribute R/W  R/W 
Initial Value 0 0 0  0 0 0 0 0 
 Functions of Register 
[bit3:0/11:8] OCFS.FSO0[3:0] 
Process Value  Function 
0000 Connects FRT ch.0 to OCU ch.(0). 
0001 Connects FRT ch.1 to OCU ch.(0). 
0010 Connects FRT ch.2 to OCU ch.(0). 
0011 
0100  For models with multiple MFT units: Connects FRT of an external MFT. 
For models with one MFT unit: Setting prohibited Write 
Other than 
above  Setting prohibited 
Read 
- Reads the register setting. 
 
[bit7:4/15:12] OCFS.FSO1[3:0] 
Process Value  Function 
0000 Connects FRT ch.0 to OCU ch.(1). 
0001 Connects FRT ch.1 to OCU ch.(1). 
0010 Connects FRT ch.2 to OCU ch.(1). 
0011 
0100  For models with multiple MFT units: Connects FRT of an external MFT. 
For models with one MFT unit: Setting prohibited Write 
Other than 
above  Setting prohibited 
Read 
- Reads the register setting. 
 
OCFS.FSO0[3:0] is a register that  selects FRT to be connected to ch.(0) of OCU and uses it. 
OCFS.FSO1[3:0] is a register that  selects FRT to be connected to ch.(1) of OCU and uses it. 
Change the setting of this register, while the operation of the OCU to be connected is prohibited. 
For models with multiple MFT units, the connection to FRT that exists in another MFT unit can be selected. 
For related settings, see  5.1 Connection of Model Containing Multiple MFT’s . 
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4. Registers of Multifunction Timer 
 
4.3.6. OCU Control Register A (OCSA) 
OCSA is an 8-bit register that control OCU’s operation. 
Each mounted channel has three registers: OCSA10, OCSA32 and OCSA54. 
OCSA10 controls OCU ch1 and OCU ch0. 
OCSA32 controls OCU ch3 and OCU ch2. 
OCSA54 controls OCU ch5 and OCU ch4. 
 Configuration of Register 
Bit  7 6 5  4 3 
2 1 
0 
Field IOP1  IOP0 IOE1  IOE0 BDIS1  BDIS0  CST1 CST0 
Attribute  R/W R/W R/W R/W  R/W R/W R/W R/W 
Initial Value 0 0 0 0  1 1 0 0 
 
  Functions of Register 
[bit0] OCSA.CST0 
Process Value  Function 
0 Disables the operation of OCU ch.(0). 
Reflects the value written to OCSB.OTD0 on the RT(0) output pin. 
Write 
Enables the operation of OCU ch.(0). 
1  Ignores the value written to OCSB.OTD0. 
Read  - Reads the register setting. 
 
[bit1] OCSA.CST1 
Process Value  Function 
0 Disables the operation of OCU ch.(1). 
Reflects the value written to OCSB.OTD1 on the RT(1) output pin. 
Write 
1 Enables the operation of OCU ch.(1). 
Ignores the value written to OCSB.OTD1. 
Read 
- Reads the register setting. 
 
OCSA.CST0 is a register that select s the operation state of OCU-ch(0). 
OCSA.CST1 is a register that select s the operation state of OCU-ch(1). 
Each channel of OCU, when the operation is enabled,  performs the following operation according to the 
operation mode setting, at the timing when the value sp ecified in the OCCP register matches FRT’s count 
value. 
   It changes the output level of the RT0 to RT5 output pins and outputs the PWM signal. 
   It sets 1 to the OCSA.IOP0 and OCSA.IOP1 re gisters and notifies CPU of the state change. 
 
If the values don’t match and the operation is disabled, the output level of the output pins maintains the last 
state. 
For OCU’s operation modes, see  4.4 Details of OCU Output Waveform . 
If  OCU’s operation
 is en

abled, the writing to the OCSB.OTD0 and OCSB.OTD1 is ignored and not 
reflected on the level of the output pins. 
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