Fujitsu Series 3 Manual
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![Page 496
9. Descriptions of base timer functions
9.2.7. LOW Width Reload Register (PRLL)
The LOW Width Reload Register (PRLL) is a register used to set the LOW width of PPG
output waveforms. Transfer to the Timer Register is performed at detection of a start trigger or
at an underflow after the completion of HIGH width counting.
bit 15 0
Field PRLL [15:0]
Attribute R/W
Initial value 0xXXXX
This register is used to set the LOW width of PPG output waveforms. Transfer to the Timer Register is...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-495.png "Page 496
9. Descriptions of base timer functions
9.2.7. LOW Width Reload Register (PRLL)
The LOW Width Reload Register (PRLL) is a register used to set the LOW width of PPG
output waveforms. Transfer to the Timer Register is performed at detection of a start trigger or
at an underflow after the completion of HIGH width counting.
bit 15 0
Field PRLL [15:0]
Attribute R/W
Initial value 0xXXXX
This register is used to set the LOW width of PPG output waveforms. Transfer to the Timer Register is...")
![Page 498
9. Descriptions of base timer functions
9.2.9. Timer Register (TMR)
The Timer Register (TMR) reads the value of the 16-bit down counter.
bit 15 0
Field TMR [15:0]
Attribute R
Initial value 0x0000
The value of the 16-bit down counter is read.
Access the TMR register with 16-bit data.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14-2: Base Timer
MN706-00002-1v0-E
462
MB9Axxx/MB9Bxxx Series](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-497.png "Page 498
9. Descriptions of base timer functions
9.2.9. Timer Register (TMR)
The Timer Register (TMR) reads the value of the 16-bit down counter.
bit 15 0
Field TMR [15:0]
Attribute R
Initial value 0x0000
The value of the 16-bit down counter is read.
Access the TMR register with 16-bit data.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14-2: Base Timer
MN706-00002-1v0-E
462
MB9Axxx/MB9Bxxx Series")
![Page 501
9. Descriptions of base timer functions
Underflow operation
An underflow occurs when the count er value changes from 0x0000 to 0xFFFF. Therefore, an underflow
occurs at a count of [Set value in the PWM Cycle Set Register + 1].
When an underflow occurs, the contents of the PWM Cycle Set Register (PCSR) are loaded to the counter.
When the MDSE bit in the Timer Control Register (TM CR) is 0, the count operation continues. When the
MDSE bit is 1, the counter stops wh ile keeping the loaded...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-500.png "Page 501
9. Descriptions of base timer functions
Underflow operation
An underflow occurs when the count er value changes from 0x0000 to 0xFFFF. Therefore, an underflow
occurs at a count of [Set value in the PWM Cycle Set Register + 1].
When an underflow occurs, the contents of the PWM Cycle Set Register (PCSR) are loaded to the counter.
When the MDSE bit in the Timer Control Register (TM CR) is 0, the count operation continues. When the
MDSE bit is 1, the counter stops wh ile keeping the loaded...")
![Page 504
9. Descriptions of base timer functions
9.3.3. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the reload
timer is selected
The Timer Control Register (TMCR) controls timer operations.
Timer Control Register (H igh-order bytes of TMCR)
bit 15 14 13 12 11 10 9 8
Field res CKS2 CKS1 CKS0 res EGS1 EGS0
Attribute R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0b00 0 0
[bit 15] res: Reserved bit The read value is 0.
Set 0 to this bit.
[bit...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-503.png "Page 504
9. Descriptions of base timer functions
9.3.3. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the reload
timer is selected
The Timer Control Register (TMCR) controls timer operations.
Timer Control Register (H igh-order bytes of TMCR)
bit 15 14 13 12 11 10 9 8
Field res CKS2 CKS1 CKS0 res EGS1 EGS0
Attribute R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0b00 0 0
[bit 15] res: Reserved bit The read value is 0.
Set 0 to this bit.
[bit...")
![Page 505
9. Descriptions of base timer functions
[bit 9:8] EGS1, EGS0: Trigger input edge selection bits These bits select a valid edge for input waveforms as an external start cause and set the trigger condition.
When the initial value or 0b00 is set, the timer is not started by external waveforms because the setting
means that no valid edge is selected for input waveforms.
If the STRG
bit is set to 1, software triggering is enabled regardless
of the EGS1 and EGS0 settings.
Changes...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-504.png "Page 505
9. Descriptions of base timer functions
[bit 9:8] EGS1, EGS0: Trigger input edge selection bits These bits select a valid edge for input waveforms as an external start cause and set the trigger condition.
When the initial value or 0b00 is set, the timer is not started by external waveforms because the setting
means that no valid edge is selected for input waveforms.
If the STRG
bit is set to 1, software triggering is enabled regardless
of the EGS1 and EGS0 settings.
Changes...")
![Page 506
9. Descriptions of base timer functions
Timer Control Register 2 (Low-order bytes of TMCR)
bit 7 6 5 4 3 2 1 0
Field T32 FMD2 FM D1 FMD0 OSEL MDSE CTEN STRG
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] T32: 32-bit timer selection bit This bit selects the 32-bit timer function.
When the FMD2, FMD1, and FMD0 bits are set to 0b011 to select the reload timer function, setting the
T32 bit to 1 selects 32-bit timer mode.
Changes must be made...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-505.png "Page 506
9. Descriptions of base timer functions
Timer Control Register 2 (Low-order bytes of TMCR)
bit 7 6 5 4 3 2 1 0
Field T32 FMD2 FM D1 FMD0 OSEL MDSE CTEN STRG
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] T32: 32-bit timer selection bit This bit selects the 32-bit timer function.
When the FMD2, FMD1, and FMD0 bits are set to 0b011 to select the reload timer function, setting the
T32 bit to 1 selects 32-bit timer mode.
Changes must be made...")
9. Descriptions of base timer functions Underflow operation An underflow occurs when the count er value changes from 0x0000 to 0xFFFF. Therefore, an underflow occurs at a count of [Set value in the PWM Cycle Set Register + 1]. When an underflow occurs, the contents of the PWM Cycle Set Register (PCSR) are loaded to the counter. When the MDSE bit in the Timer Control Register (TM CR) is 0, the count operation continues. When the MDSE bit is 1, the counter stops wh ile keeping the loaded counter value. An underflow sets the UDIR bit in the Status Control Register (STC). In this case, an interrupt request occurs when the UDIE bit is 1. Figure 9-14 shows a timing chart of underflow operations. Figure 9-14 Underflow operation timing chart UDIR Load Count clock Count value Reload value-1 -1 0x0000 Underflow set UDIR Load Count clock Count value 0x0000 Underflow set Reload value When [MDSE = 1] When [MDSE = 0] FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 465 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Operation of the input pin function The TGIN pin can be used for trigger input. When a valid edge is input to the TGIN pin, the contents of the PWM Cycle Set Register are loaded to the counter and the count operation is started. As a time from trigger input to loading of the counter value, 2T to 3T (T: machine cycle) is required. Figure 9-15 shows a trigger input operation performed when a rising edge is specified as a valid edge. Figure 9-15 Operation caused by a trigger input Load Count clock Count value Reload value-1 -1 0x0000 TGIN 2T to 3T (External trigger) Operation of the output pin function The TOUT output pin functions as, reload mode, toggle output inverted by an underflow and, in one-shot mode, pulse output indicating that counting is in progress. The output polarity can be set with the OSEL bit in the Timer Control Register (TMCR). If OSEL = 0, t oggle output has an initial value of 0, and one-shot pulse output is 1 during counting. When OSEL is set to 1, the output waveform is inverted. Figure 9-16 shows a timing chart of output pin function operations. Figure 9-16 Output pin function operation timing chart Trigger Underflow TOUT CTEN Inverted when OSEL = 1 Trigger Underflow TOUT CTEN Inverted when OSEL = 1 Waiting for a start by a trigger When [MDSE = 0, OSEL = 0] When [MDSE = 1, OSEL = 0] FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 466 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.3.2. Reload timer operation flowchart This section provides an operation flowchart of the reload timer. Reload timer operation flowchart Reload mode selection Count clock selection Operation mode selection Interrupt flag clear Interrupt enableSettings One-shot operation Continuous operation External trigger detection TGIR flag setting Start of decrement Occurrence of an underflow UDIR flag setting MDSE = 0? No Software trigger detection TGIR flag setting Yes Stop of count operation Stop of operation Loading of the PCSR value to the counte r Loading of the PCSR value to the counte r Start by the CTEN bit FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 467 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.3.3. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the reload timer is selected The Timer Control Register (TMCR) controls timer operations. Timer Control Register (H igh-order bytes of TMCR) bit 15 14 13 12 11 10 9 8 Field res CKS2 CKS1 CKS0 res EGS1 EGS0 Attribute R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0b00 0 0 [bit 15] res: Reserved bit The read value is 0. Set 0 to this bit. [bit 14:12, TMCR2: bit 8] CKS3 to CKS0: Count clock selection bit Select the count clock for the 16-bit down counter. Changes to the count clock setting are applied immediately. For this reason, changes to CKS3 through CKS0 must be made when the counting is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. CKS3 CKS2 CKS1 CKS0 Description 0 0 0 0 0 0 0 1 /4 0 0 1 0 /16 0 0 1 1 /128 0 1 0 0 /256 0 1 0 1 External clock (rising edge event) 0 1 1 0 External clock (falling edge event) 0 1 1 1 External clock (both edge event) 1 0 0 0 /512 1 0 0 1 /1024 1 0 1 0 /2048 Others Setting disabled [bit 11:10] res : Reserved bits The read value is 0. Set 0 to this bit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 468 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions [bit 9:8] EGS1, EGS0: Trigger input edge selection bits These bits select a valid edge for input waveforms as an external start cause and set the trigger condition. When the initial value or 0b00 is set, the timer is not started by external waveforms because the setting means that no valid edge is selected for input waveforms. If the STRG bit is set to 1, software triggering is enabled regardless of the EGS1 and EGS0 settings. Changes to EGS1 or EGS0 must be made when the counting is stopped (CTEN = 0). However, it is possibl e to make changes at the same time you set 1 to the CTEN bit. Bit 9 Bit 8 Description 0 0 Trigger input disabled 0 1 External trigger (rising edge) 1 0 External trigger (falling edge) 1 1 External trigger (both edges) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 469 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Timer Control Register 2 (Low-order bytes of TMCR) bit 7 6 5 4 3 2 1 0 Field T32 FMD2 FM D1 FMD0 OSEL MDSE CTEN STRG Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 [bit 7] T32: 32-bit timer selection bit This bit selects the 32-bit timer function. When the FMD2, FMD1, and FMD0 bits are set to 0b011 to select the reload timer function, setting the T32 bit to 1 selects 32-bit timer mode. Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit (see 32-bit mode operations). Bit Description 0 16-bit timer mode 1 32-bit timer mode [bit 6:4] FMD2 to FMD0: Timer function selection bits These bits select the timer function. When the FMD2, FMD1, and FMD0 bits are set to 0b011, the reload timer function is selected. Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. Bit 6 Bit 5Bit 4 Description 0 0 0 Reset mode 0 0 1 Selection of the PWM function 0 1 0 Selection of the PPG function 0 1 1 Selection of the reload timer function 1 0 0 Selection of the PWC function Others Setting disabled FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 470 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions [bit 3] OSEL: Output polarity specification bit This bit selects whether to invert the timer output level. Used in combination with bit 2 MDSE, this bit generates the following output waveforms. MDSE OSEL Output waveforms 0 0 Toggle output at the LOW level at the start of counting 0 1 Toggle output at the HIGH level at the start of counting 1 0 Rectangular waves at the HIGH level during counting 1 1 Rectangular waves at the LOW level during counting Bit Description 0 Normal polarity 1 Inverted polarity [bit 2] MDSE: Mode selection bit When the MDSE bit is set to 0, reload mode is selected. When a value underflow from 0x0000 to 0xFFFF occurs, the reload register value is loaded to the counter at the same time, and the count operation is continued. When the MDSE bit is set to 1, one-shot mode is selected. A count value underflow from 0x0000 to 0xFFFF stops the operation. Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. Bit Description 0 Reload mode 1 One-shot mode [bit 1] CTEN: Timer enable bit This bit enables the operation of the down counter. When the counter is in operation en abled status (the CTEN bit is 1), writing 0 to this bit stops the counter. Bit Description 0 Stop 1 Operation enabled FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 471 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions [bit 0] STRG: Software trigger bit When the CTEN bit is 1, writing 1 to the STRG bit enables software triggering. The read value of the STRG bit is always 0. Soft ware triggering is also enabled when 1 is written to the CTEN and STRG bits simultaneously. If the STRG bit is set to 1, software triggering is enabled regardless of the EGS1 and EGS0 settings. Bit Description 0 Invalid 1 Start triggered by software FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 472 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Timer Control Register 2 (High-order bytes of TMCR2) bit 15 14 13 12 11 10 9 8 Field res CKS3 Attribute R/W R/W Initial value 0b0000000 0 Note: This register is placed above the STC register. [bit 15:9] res: Reserved bits The read value is 0. Set 0 to this bit. [bit 8] CKS3: Count clock selection bit See Count clock selection bit in 9.3.3 Timer Control Register (High-order bytes of TMCR). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 473 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Status Control Register (STC) bit 7 6 5 4 3 2 1 0 Field res TGIE res UDIE res TGIR res UDIR Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Note: The TMCR2 register is placed in the upper bytes of this register. [bit 7] res: Reserved bit The read value is 0. Set 0 to this bit. [bit 6] TGIE: Trigger interrupt request enable bit This bit controls interrupt requests of bit 2 TGIR. When the TGIE bit is enabled, setting bit 2 TGIR generates an interrupt request to the CPU. Bit Description 0 Disables interrupt requests. 1 Enables interrupt requests. [bit 5] res : Reserved bit The read value is 0. Set 0 to this bit. [bit 4] UDIE: Underflow interrupt request enable bit This bit controls interrupt requests of bit 0 UDIR. When the UDIE bit is enabled, setting bit0 UDIR generates an interrupt request to the CPU. Bit Description 0 Disables interrupt requests. 1 Enables interrupt requests. [bit 3] res: Reserved bit The read value is 0. Set 0 to this bit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 474 MB9Axxx/MB9Bxxx Series