Fujitsu Series 3 Manual
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3. USB host operations A device connection is detected. Figure 3-13 Resume operation by device connection (Full-speed mode) FUJITSU SEMICONDUCTOR LIMITED Connection Host pin D + Host pin D - CNNIRQ bit of HIRQ RWKIRQ bit of HIRQ (RWKIRE =1 ) ( CNNIRE = ) 1 An interrupt . occurs CSTAT bit of HSTATE 2.5 s or more : Drive by pul l- up or pull - down resistor CHAPTER 20-3: USB Host MN706-00002-1v0-E 1155 MB9Axxx/MB9Bxxx Series
3. USB host operations 3.11. Device disconnection The device disconnection timer starts when both the host pins D+ and D- are set to LOW. If LOW is detected for 2.5s or more, the CSTAT bit of the Host S tatus Register (HSTATE) is set to 0. Device disconnection If both the host pins D+ and D- remain set to LOW for 2.5 s or more regardless of the host or function mode, it is judged that the device has been disconnected. This then sets 0 to the CSTAT bit of the Host Status Register (HSTATE) and 1 to the DIRQ bit of the Host Interrupt Register (HIRQ). At this time, if the DIRE bit of Host Control Register 0 (HCNT0) is 1, an interrupt occurs. To clear this interrupt, write 0 to the DIRQ bit of the Ho st Interrupt Register (HIRQ). If the USB bus is reset, it is judged that the device has been disconnected. In this case, the CSTAT bit of the Host Status Register (HSTATE) is set to 0, but the DIRQ bit of the Host Interrupt Register (HIRQ) is not set to 1. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1156 MB9Axxx/MB9Bxxx Series
4. USB host setting procedure examples 4. USB host setting procedure examples The following shows the flowchart for each token in the USB host. Initialization and device detection Start UDCC.RST=1 HCNT0.HOST=1 // Host mode setting EP1C setting EP2C setting HIRQ.CNNIRQ=1?No // Device connection Yes HSTATE.TMODE=1?No Yes HSTATE.CLKSEL=1 // Low-speed detection // Full-speed detection HSTATE.CLKSEL = Setting value?No Yes // Bus resetting HIRQ.URIRQ=1? No Yes HIRQ.CNNIRQ=1? No Yes HSTATE.TMODE=1?No Yes HSTATE.CLKSEL=1 // Low-speed detection // Full-speed detection HSTATE.CLKSEL = Setting value?No End Yes USB Clock setting HCNT0.URST=1 UDCC.RST=0 UDCC.RST=1 HSTATE.CLKSEL=0 HSTATE.CLKSEL=0 USBEN.USBEN=1 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1157 MB9Axxx/MB9Bxxx Series
4. USB host setting procedure examples IN, OUT, or SETUP token EP1S.BFINI=0 EP2S.BFINI=0 IN token HADR setting EP1C setting EP2C setting // Select the transfer direction and specify the packet size. (*) // Select the transfer direction and specify the packet size. (*) HTOKEN setting// Toggle, endpoint, or IN setting HIRQ.CMPIRQ=1?No Yes HERR.LSTSOF=1?Yes No HERR.TOUT=1?Yes No HERR.TGERR=1?Yes No HERR.HS=00?No Yes Error processing Read the received data. (EPnDT) EPnS.DRQ=0 EP1S.BFINI=1 EP2S.BFINI=1 End // n=1 or 2 // n=1 or 2 * This setting is not required for each processing if no change is made in the initialization routine. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1158 MB9Axxx/MB9Bxxx Series
4. USB host setting procedure examples EP1S.BFINI=0 EP2S.BFINI=0 OUT token HADR setting EP1C setting EP2C setting // Select the transfer direction and specify the packet size. // Select the transfer direction and specify the packet size. HTOKEN setting // Toggle, endpoint, or OUT setting HIRQ.CMPIRQ=1?No Yes HERR.LSTSOF=1?Yes No HERR.TOUT=1?Yes No HERR.HS=00?No Yes Error processing EPnS.DRQ=0 EP1S.BFINI=1 EP2S.BFINI=1 End Write the send data. (EPnDT)// n=1 or 2 // n=1 or 2 Enumeration? No Yes// Null Frame FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1159 MB9Axxx/MB9Bxxx Series
4. USB host setting procedure examples EP1S.BFINI=0 EP2S.BFINI=0 SETUP token HADR setting EP1C setting EP2C setting // Select the transfer direction and specify the packet size. // Select the transfer direction and specify the packet size. HTOKEN setting// Toggle, endpoint, or OUT setting HIRQ.CMPIRQ=1?No Yes HERR.LSTSOF=1?Yes No HERR.TOUT=1?Yes No HERR.HS=00?No Yes Error processing EPnS.DRQ=0 EP1S.BFINI=1 EP2S.BFINI=1 End Write setup data. (EPnDT)// n=1 or 2 // n=1 or 2 Enumeration? No Yes// Null Frame FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1160 MB9Axxx/MB9Bxxx Series
4. USB host setting procedure examples SOF token HFRAME setting HEOF setting HTOKEN setting// SOF setting (TGGL and ENDPT ignored) HIRQ.CMPIRQ=1?No Yes HERR.LSTSOF=1?Yes No End Error processing SOF token FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1161 MB9Axxx/MB9Bxxx Series
5. USB host registers 5. USB host registers This section explains the configuration and functions of the registers used for the USB host. List of USB host registers Abbreviation Register name See UDCC UDC Control Register * EP1C EP1 Control Register * EP2C EP2 Control Register * EP1S EP1 Status Register * EP2S EP2 Status Register * EP1DTH EP0 Data Register high-order * EP1DTL EP0 Data Register low-order * EP2DTH EP0 Data Register high-order * EP2DTL EP0 Data Register low-order * HCNT0 Host Control Register 0 5.1 HCNT1 Host Control Register 1 5.1 HIRQ Host Interrupt Register 5.2 HERR Host Error Status Register 5.3 HSTATE Host Status Register 5.4 HFCOMP SOF Interrupt Frame Compare Register 5.5 HRTIMER Retry Timer Setup Register 5.6 HADR Host Address Register 5.7 HEOF EOF Setup Register 5.8 HFRAME Frame Setup Register 5.9 HTOKEN Host Token Endpoint Register 5.10 * : See USB Functions. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1162 MB9Axxx/MB9Bxxx Series
5. USB host registers UDCC.RST dependent register bit update timing list Register Bit FUJITSU SEMICONDUCTOR LIMITED HCNT0 HOST HSTATE CLKSEL Register bits to be updated when UDCC.RST=1 EP1C EPEN, TYPE, DIR, PKS1 EP2C EPEN, TYPE, DIR, PK S2 HCNT0 URST HIRQ TCAN, RWKIRQ, URIRQ, CMPIRQ, CNNIRQ, DIRQ, SOFIRQ Register bits initialized when UDCC.RST=1 (Update when UDCC.RST=0) HERR (All bits) LSTSOF, RERR, T OUT, CRC, TGERR, STUFF, HS HSTATE SOFBUSY, SUSP HFRAME FRAME0, FRAME1 HTOKEN (All bits) TGGL, TKNEN, ENDPT EP1S BFINI, DRQ, SPK EP2S BFINI, DRQ, SPK HCNT0 RWKIRE, URIRE, CMPIRE, CNNIRE, DIRE, SOFIRE Register bits unaf fected by UDCC.RST HCNT1 SOFSTEP, CANSEL, RETRY HIRQ CNNIRQ, DIRQ HFCOMP HFRAMECOMP HSTATE TMODE, CSTAT HRTIMER0, 1, 2RTIMER0, 1, 2 HADR Address HEOF EOF0 , 1 CHAPTER 20-3: USB Host MN706-00002-1v0-E 1163 MB9Axxx/MB9Bxxx Series
5. USB host registers 5.1. Host Control Registers 0 and 1 (HCNT0 and HCNT1) Host Control Registers 0 and 1 (HCNT0 and HCNT1) are used to specify the USB operation mode and interrupt. Host Control Register 1 (HCNT1) bit 15 14 13 12 11 10 9 8 Field Reserved Reserved Reserved ReservedReservedSOFSTEP CANCEL RETRY Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 1 Reset enabled or not* x x x x x x x x * : Enables or disables a reset with the RST bit of UDCC. x: Not to be reset. : To be reset. Host Control Register 0 (HCNT0) bit 7 6 5 4 3 2 1 0 Field RWKIRE URIRE CMPIRE CNNIRE DIRE SOFIRE URST HOST Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Reset enabled or not* x x x x x x × * : Enables or disables a reset with the RST bit of UDCC. x: Not to be reset. : To be reset. [bit 15:11] Reserved bits These are reserved bits. Always set it to 0. [bit 10] SOFSTEP (SOF STEP) This is a SOF interrupt occurrence selection bit If this bit is set to 1, the SOF interrupt flag (HIRQ. SOFIRQ) is set to 1 each time SOF is sent. If this bit is set to 0, the set value of the SOF In terrupt Frame Compare Register (HFCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (HIRQ.SOFIRQ) is set to 1. Bit Description 0 An interrupt occurred due to the HFCOMP setting. 1 An interrupt occurred. If a SOF token (TKNEN=001) is se nt by the setting of the Host Token Endpoint Register (HTOKEN), the SOF interrupt flag (HIRQ.SOFIRQ) is not set to 1 regardless of the setting of this bit. This bit is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-3: USB Host MN706-00002-1v0-E 1164 MB9Axxx/MB9Bxxx Series