Fujitsu Series 3 Manual
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![Page 446
4. Registers
[bit 11:8] SEL01_3 to SEL01_0: I/O select bits for Ch.0/Ch.1
Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit timer mode)
0
0 0 1 I/O mode 1
(Timer full mode)
0
0 1 0 I/O mode 2
(Shared external trigger mode)
0
0 1 1 I/O mode 3
(Shared channel signal trigger mode)
0
1 0 0 I/O mode 4
(Timer start/stop mode)
0
1 0 1 I/O mode 5
(Software-based simultaneous startup mode)
0
1 1 0 I/O mode 6
(Software-based startup an
d timer...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-445.png "Page 446
4. Registers
[bit 11:8] SEL01_3 to SEL01_0: I/O select bits for Ch.0/Ch.1
Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit timer mode)
0
0 0 1 I/O mode 1
(Timer full mode)
0
0 1 0 I/O mode 2
(Shared external trigger mode)
0
0 1 1 I/O mode 3
(Shared channel signal trigger mode)
0
1 0 0 I/O mode 4
(Timer start/stop mode)
0
1 0 1 I/O mode 5
(Software-based simultaneous startup mode)
0
1 1 0 I/O mode 6
(Software-based startup an
d timer...")
![Page 447
4. Registers
4.2. I/O Select Register (BTSEL4567)
This register selects the I/O mode for channels 4 to 7 of the base timer.
Register configuration
bit 15 14 13 12 11 10 9 8
Field SEL67_3SEL67_2 SEL67_1 SEL67_0SEL45_3SEL45_2 SEL45_1 SEL45_0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Register functions
[bit 15:12] SEL67_3 to SEL67_0: I/O select bits for Ch.6/Ch.7
Bit 15 Bit 14 Bit 13 Bit 12 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-446.png "Page 447
4. Registers
4.2. I/O Select Register (BTSEL4567)
This register selects the I/O mode for channels 4 to 7 of the base timer.
Register configuration
bit 15 14 13 12 11 10 9 8
Field SEL67_3SEL67_2 SEL67_1 SEL67_0SEL45_3SEL45_2 SEL45_1 SEL45_0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Register functions
[bit 15:12] SEL67_3 to SEL67_0: I/O select bits for Ch.6/Ch.7
Bit 15 Bit 14 Bit 13 Bit 12 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit...")
![Page 448
4. Registers
[bit 11:8] SEL45_3 to SEL45_0: I/O select bits for Ch.4/Ch.5
Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit timer mode)
0 0 0 1 I/O mode 1
(Timer full mode)
0 0 1 0 I/O mode 2
(Shared external trigger mode)
0 0 1 1 I/O mode 3
(Shared channel signal trigger mode)
0 1 0 0 I/O mode 4
(Timer start/stop mode)
0 1 0 1 I/O mode 5
(Software-based simultaneous startup mode)
0 1 1 0 I/O mode 6
(Software-based startup an
d timer start/stop mode)
0 1...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-447.png "Page 448
4. Registers
[bit 11:8] SEL45_3 to SEL45_0: I/O select bits for Ch.4/Ch.5
Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit timer mode)
0 0 0 1 I/O mode 1
(Timer full mode)
0 0 1 0 I/O mode 2
(Shared external trigger mode)
0 0 1 1 I/O mode 3
(Shared channel signal trigger mode)
0 1 0 0 I/O mode 4
(Timer start/stop mode)
0 1 0 1 I/O mode 5
(Software-based simultaneous startup mode)
0 1 1 0 I/O mode 6
(Software-based startup an
d timer start/stop mode)
0 1...")
![Page 449
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
Chapter: Base Timer I/O Select Function
FUJITSU SEMICONDUCTOR CONFIDENTIAL 28
4.3. Software-based Simultaneous Startup Register (BTSSSR)
This register starts up multiple base timer channels using software.
Up to 16 channels can be started simultaneously if the bits corresponding to the channel are
set to 1.
Register configuration
bit 15 - 0
Field SSSR15 to 0
Attribute W
Initial value X
Register functions
[bit 15:0] SSSR15 to...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-448.png "Page 449
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
Chapter: Base Timer I/O Select Function
FUJITSU SEMICONDUCTOR CONFIDENTIAL 28
4.3. Software-based Simultaneous Startup Register (BTSSSR)
This register starts up multiple base timer channels using software.
Up to 16 channels can be started simultaneously if the bits corresponding to the channel are
set to 1.
Register configuration
bit 15 - 0
Field SSSR15 to 0
Attribute W
Initial value X
Register functions
[bit 15:0] SSSR15 to...")
1. Overview of Base Timer Chapter: Base Timer This chapter explains the functions and operations of the base timer. 1. Overview of Base Timer 2. Block Diagram Of Base Timer 3. Operations of the Base Timer 4. 32-bit mode operations 5. Base Timer Interrupt 6. Starting the DMA Controller (DMAC) 7. Base Timer Registers 8. Notes on using the base timer 9. Descriptions of base timer functions CODE: FM10-E03.1 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 415 MB9Axxx/MB9Bxxx Series
1. Overview of Base Timer 1. Overview of Base Timer The function of the base timer can be set to either the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, or 16/32-bit PWC timer using the FMD2, 1, and 0 bits in the Timer Control Register. The following provides an overview of each selectable timer function. Relationship between mode se ttings and timer functions Settings of FMD2, FMD1, and FMD0 bits Function 0b000 Reset mode 0b001 16-bit PWM timer 0b010 16-bit PPG timer 0b011 16/32-bit reload timer 0b100 16/32-bit PWC timer Reset mode The reset mode is a status where the base timer macros are reset (with each register set to the initial value). Be sure to set this mode before switching to a differ ent timer function or T32 bit setting. However, it is not necessary to set this mode before setting the timer function or T32 bit immediately after the macros are reset. 16-bit PWM timer This timer consists of a 16-bit down counter, a 16-bit da ta register with a cycle set buffer, a 16-bit compare register with a duty set buffer, and a pin controller. The cycle and duty data is stored in a buffered register and thus can be rewritten while the timer is in operation. The counter clock of the 16-bit down counter can be selected from eight internal clocks (1, 4, 16, 128, 256, 512, 1024, and 2048 frequency divisions of the machin e clock) and three external events (detection of a rising edge, a falling edge, or both). The one-shot mode where the counting stops at an und erflow or the continuous mode where the counting is repeated after reloading can be selected. The start event of the 16-bit PWM timer can be selected from a software trigger and three external events (detection of a rising edge, a falling edge, or both). 16-bit PPG timer This timer consists of a 16-bit down counter, a 16-bit da ta register for setting the HIGH width, a 16-bit data register for setting the LOW width, and a pin controller. The count clock of the 16-bit down counter can be selected from eight internal clocks (1, 4, 16, 128, 256, 512, 1024, and 2048 frequency divisions of the machin e clock) and three external events (detection of a rising edge, a falling edge, or both). The one-shot mode where the counting stops at an und erflow or the continuous mode where the counting is repeated after reloading can be selected. The start event of the 16-bit PPG timer can be selected from a software trigger and three external events (detection of a rising edge, a falling edge, or both). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 416 MB9Axxx/MB9Bxxx Series
1. Overview of Base Timer 16/32-bit reload timer This timer consists of a 16-bit down counter, a 16-bit reload register, and a pin controller. The count clock of the 16-bit down counter can be selected from eight internal clocks (1, 4, 16, 128, 256, 512, 1024, and 2048 frequency divisions of the machin e clock) and three external events (detection of a rising edge, a falling edge, or both). The one-shot mode where the counting stops at an und erflow or the continuous mode where the counting is repeated after reloading can be selected. The start event of the 16/32-bit reload timer can be selected from a software trigger and three external events (detection of a rising edge, a falling edge, or both). 16/32-bit PWC timer This timer consists of a 16-bit up counter, a measurement input pin, and a control register. This timer measures the time between any events using an external pulse input. The reference count clock can be selected from eight internal clocks (1, 4, 16, 128, 256, 512, 1024, and 2048 frequency divisions). Measurement modes HIGH pulse width ( ↑ to ↓) / LOW pulse width ( ↓ to ↑) Rising cycle ( ↑ to ↑) / Falling cycle ( ↓ to ↓) Edge interval measurement ( ↑ or ↓ to ↓ or ↑) An interrupt request can be generated when the measurement is completed. One-time or continuous meas urement can be selected. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 417 MB9Axxx/MB9Bxxx Series
2. Block Diagram Of Base Timer 2. Block Diagram Of Base Timer Figure 2-1 to Figure 2-4 show block diagrams of the base timer in each mode. Figure 2-1 Block diagram of 16-bit PWM timer 16-bit down counter Underflow Count clock / 16 16 / Load OSEL TOUT Inversion control Match detection STRG External startup trigger (TGIN signal) EGS CTEN TGIE DTIE UDIE Trigger Timer enable / 2 PMSK POE Buffer Edge detection Count enable Interrupt cause generation Toggle generation MDSE PDUT writing PDUT / 16 Buffer PCSR Load Count enable 20 : 211 / 4 CKS External clock (ECK signal) Clock frequency circuitInternal clock Edge detection CTENTrigger interrupt request Waveform output (TOUT signal) Underflow/ duty match interrupt request PCSR : Cycle Set Register PDUT : Duty Set Register Figure 2-2 Block diagram of 16-bit PPG timer Trigger interrupt request PPG output 16 / OSEL (TOUT signal) Inversion control TGIE Reload data setting UDIEUnderflow interrupt request PMSKPOE 20 : 211 / 4 CKS External clock (ECK signal) Clock frequency circuitInternal clock Edge detectionDown counter TMR Underflow Count clock Load Count enable STRG External startup trigger (TGIN signal) CTEN Trigger Timer enableEdge detection Count enable Interrupt cause generationMDSE CTEN PRLL PRLHBuffer (PRLHB) EGS/ 2Toggle generation PRLL : LOW Width Reload Register PRLH : HIGH Width Reload Register TMR : Timer Register FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 418 MB9Axxx/MB9Bxxx Series
2. Block Diagram Of Base Timer Figure 2-3 Block diagram of 16/32-bit reload timer (ch1 and ch0) T32 / 16 CH1 CH0 Output waveform (TOUT signal)OSEL Inversion control 32-bit mode T32=1 16-bit mode T32=0 POE Trigger interrupt request TGIE UDIE PCSR Down counter TMR Underflow Count clock Load Count enable 20 : 211 / 4 CKS External clock (ECK signal) EGS / 2 Clock frequency circuitInternal clock STRGExternal startup trigger (TGIN signal) Timer enable Trigger Edge detection Count enable / 16 PCSR Down counter TMR Underflow Count clock Load Count enable MDSE Toggle generation Interrupt cause generation CTEN CTEN Edge detection Underflow interrupt request PCSR : Base Timer 1 Cycle Set Register TMR : Base Timer 1 Timer Register PCSR : Base Timer 0 Cycle Set Register TMR : Base Timer 0 Timer Register FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 419 MB9Axxx/MB9Bxxx Series
2. Block Diagram Of Base Timer Figure 2-4 Block diagram of 16/32-bit PWC timer (ch1 and ch0) CH0 / 16 CH1 Clear / 16 16-bit mode T32=0 32-bit mode T32=1 20 : 211 / 4 CKS Clock frequency circuitInternal clock STRGSignal to be measured (TIN signal) Detection of a startEdge detection Count enable Edge detectionCTEN CTENMeasurement completion interrupt request EDIE OVIEOverflow interrupt request Interrupt cause generation MDSE Up counter TMR Overflow Count clock Count enable T32 Clear Up counter TMR Overflow Count clock Count enable DTBF DTBF Detection of a stop MDSE EGS / 3 DTBF : Base Timer 1 Data Buffer Register TMR : Base Timer 1 Timer Register DTBF : Base Timer 0 Data Buffer Register TMR : Base Timer 0 Timer Register FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 420 MB9Axxx/MB9Bxxx Series
3. Operations of the Base Timer 3. Operations of the Base Timer This section explains operations of the base timer. Operations of the base timer Reset mode The reset mode is a status where the base timer macros are reset (with each register set to the initial value). Be sure to set this mode before switching to a differ ent timer function or T32 bit setting. However, it is not necessary to set this mode before setting the timer function or T32 bit immediately after the macros are reset. In a 32-bit mode, setting this mode for the even channel also resets the odd channel. It is not necessary to set the reset mode for the odd channel. 16-bit PWM timer When triggered, the 16-bit PWM timer starts decrementing from the cycle set value. First, it outputs a LOW level pulse. When the 16-bit down counter matches the value set in the PWM Duty Set Register, the output inverts to the HIGH level. Then, the output inverts again to the LOW level when a counter underflow occurs. This can generate waveforms with any cycle and duty. 16-bit PPG timer When triggered, the 16-bit PPG timer starts decrementing from the value set in the LOW Width Reload Register. First, it outputs a LOW level pulse. The outp ut inverts to the HIGH level upon an underflow. Then, it starts decrementing from the value set in the HIGH Width Reload Register. The output inverts to the LOW level when an underflow occurs. This can generate waveforms having any LOW and HIGH widths. 16-bit reload timer When triggered, the 16-bit reload timer starts decrem enting from the cycle set value. When an underflow occurs on the 16-bit down counter, an interrupt flag is set. The output is either the toggle output where the level inverts according to the MDSE bit setting as an u nderflow occurs or the pulse output where the level is HIGH at the start of counting and LOW at the occurrence of an underflow. 32-bit reload timer This timer has the same basic operations as the 16-bit reload timer. However, it uses two channels, even and odd, to operate as a 32-bit reload timer. The even channel operates as a lower 16-bit timer and the odd channel as an upper 16-bit timer. The interrupt control and output waveform control are defined by the settings for the even channel only. When setting the cycle, first write it in the upper register (odd channel) and then in the lower register (even channel). When reading the timer value, read it from the lower register (even channel) and then from the upper channel (odd channel). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 421 MB9Axxx/MB9Bxxx Series
3. Operations of the Base Timer 16-bit PWC timer The PWC timer starts the 16-bit up counter with input of the specified measurement start edge and stops the counter with detection of a measurement end edge. The value counted in between is stored as a pulse width in the data buffer register. 32-bit PWC timer This timer has the same basic operations as the 16-bit PWC timer. However, it uses two channels, even and odd, to operate as a 32-bit PWC timer. The even channel operates as a lower 16-bit counter and the odd channel as an upper 16-bit counter. The interrupt control is defined by the settings for the even channel only. When reading the measured or count va lue, read it from the lower register (even channel) and then from the upper channel (odd channel). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 422 MB9Axxx/MB9Bxxx Series
4. 32-bit mode operations 4. 32-bit mode operations Using two channels, the reload timer and PWC provide 32-bit mode operations. This section explains the basic functions and operations of the 32-bit mode functions. 32-bit mode functions This function enables the operations of a 32-bit data reload timer or 32-bit data PWC timer by combining two channels of base timers. Since the upper 16-bit timer counter value in the odd channel is read together with the lower 16-bit timer counter value in the even channel, the timer counter value can be read during operation. 32-bit mode settings First, set 0b000 to set the reset mode to reset the status of the FMD2, FMD1, and FMD0 bits in the TMCR register of the even channel. Then, as carried out for in 16-bit mode, select the reload or PWC timer and set the operation. By writing 1 also to the T32 bit in the TMCR register, the 32-bit operation mode is set. Do not change 0 for the T32 bit in the odd channel. It is also not necessary to set it to reset mode. For the reload timer, set the reload value of the upper 16 of 32 bits in the PWM Cycle Set Register of the odd channel. Then, set the reload value of the lower 16 bits in the PWM Cycle Set Register of the even channel. Because transition to 32-bit operation mode is reflected immediately after the T32 bit is written, stop the counting before changing the settings in each channel. To change from 32-bit mode to 16-bit mode, set it to reset mode by setting 0b000 for the FMD2, FMD1, and FMD0 bits in the TMCR register of the even channel. This resets the status of both even and odd channels, enabling settings in 16-bit mode in each channel. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 423 MB9Axxx/MB9Bxxx Series
4. 32-bit mode operations 32-bit mode operations After transition to 32-bit mode, if th e reload or PWC timer is started by control of the even channel, the timer/counter in the even channel operates with the lower 16 bits. Also, the time/counter in the odd channel operates with the upper 16 bits. The operations in 32-bit mode are defined by the settings for the even channel. For this reason, the settings for the odd channel (except the Cycle Set Register for the reload timer) are ignored. For the timer start, waveform output, and interrupt signal functions, settings for the even channel are also applied (the even channel is masked and fixed to LOW). Figure 4-1 shows the configuration of ch.0 and ch.1. Figure 4-1 Configuration of 32-bit operations (for ch.0 and ch.1) T32=1 Underflow Overflow ch.0 Lower 16 bits timer/counter T32=0ch.1 Upper 16 bits timer/counterUnderflow Overflow Interrupt Waveform output Read/write signal PWC measurement waveform/external trigger Upper 16 bitsreload valueLower 16 bitsreload value FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 424 MB9Axxx/MB9Bxxx Series