Fujitsu Series 3 Manual

							 
 
 
CHAPTER 10: Clock supervisor........................................................................\
.................297 
1. Overview ........................................................................\
...............................................298 
2. Configurations  and Block Diagrams........................................................................\
......299 
3. Explanation of  Operations ........................................................................\
.....................301 
4. Setup Procedure Exampl es ........................................................................\
................... 302 
5. Operation  Examples ........................................................................\
.............................. 304 
6. Regist er list........................................................................\
....................................... .....308 
6.1. CSV control register (CSV_CTL)........................................................................\
........ 309 
6.2. CSV status regi ster (CSV_STR) ........................................................................\
......... 311 
6.3. Frequency detection  window setting register (Upper) (FCSWH_CTL) ....................... 312 
6.4. Frequency detection  window setting register (Lower) (FCSWL_CTL) ....................... 313 
6.5. Frequency detection count er register (FCSWD_CTL) ................................................ 314 
7. Usage Prec autions........................................................................\
................................315  
CHAPTER 11: Watchdog timer ........................................................................\
..................317 
1. Overview ........................................................................\
............................................ ...318 
2. Configuration and Block Di agram........................................................................\
..........319 
3. Oper ations ........................................................................\
.......................................... ...321 
4. Setting Procedur e Example ........................................................................\
...................326 
5. Operation  Example........................................................................\
................................328  
6. Registers ........................................................................\
........................................... ....331 
6.1. Software Watchdog Timer Load Register (WdogLoad) .............................................. 332 
6.2. Software Watchdog Timer  Value Register (WdogValue) ............................................ 333 
6.3. Software Watchdog Timer Control Register  (WdogControl) ....................................... 334 
6.4. Software Watchdog Timer  Clear Register (WdogIntClr) ............................................. 335 
6.5. Software Watchdog Timer Interr upt Status Register (WdogRIS) ................................ 336 
6.6. Software Watchdog Timer Lock Register  (WdogLock) ............................................... 337 
6.7. Hardware Watchdog Timer  Load Register (WDG_LDR) ............................................ 338 
6.8. Hardware Watchdog Timer  Value Register (WDG_VLR)............................................ 339 
6.9. Hardware Watchdog Timer Control Register  (WDG_CTL) ......................................... 340 
6.10. Hardware Watchdog Timer  Clear Register (WDG_ICL) ........................................... 341 
6.11. Hardware Watchdog  Timer Interrupt Status Register (WDG_RIS) ........................... 342 
6.12. Hardware Watchdog Timer  Lock Register (WDG_LCK) ........................................... 343 
7. Notes ........................................................................\
............................................... ......344 
FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
\0509\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 12: Dual Timer ........................................................................\
..........................345 
1. Overview ........................................................................\
...............................................346 
2. Archit ecture ........................................................................\
........................................ ...347 
3. Operation  Description........................................................................\
............................348  
3.1. Timer Operating Mode ........................................................................\
........................ 349 
3.2. De fault ........................................................................\
........................................... ...... 353 
3.3. Interrupt Behav ior.....................................................................\
................................... 354 
4. Setting Procedure Example ........................................................................\
...................355 
5. Register ........................................................................\
............................................ .....357 
5.1. Load Register (TimerXLoad) X=1 or 2........................................................................\
 358 
5.2. Value Register (TimerXValue) X= 1 or 2 ...................................................................... 359 
5.3. Control Register (Tim erXControl) X=1 or 2 ................................................................. 360 
5.4. Interrupt Clear Register  (TimerXIntClr) X=1 or 2 ........................................................ 362 
5.5. Interrupt Status Regist er (TimerXRIS) X=1 or 2 ......................................................... 363 
5.6. Masked Interrupt Status Regi ster (TimerXMIS) X=1 or 2 ........................................... 364 
5.7. Background Load Register (TimerXBGLoad) X=1 or 2 .............................................. 365 
CHAPTER 13-1: Watch Counter Prescaler ........................................................................\
367 
1. Overview of the Watc h Counter Prescaler.....................................................................368 
2. Configuration of the Wa tch Counter Prescaler ..............................................................369 
3. Explanation of Operations and Setti ng Procedure Examples of the Watch 
Counter Pre scaler........................................................................\
.............................. 370 
4. Registers of the Watc h Counter Prescaler ....................................................................372 
4.1. Clock Selection Register (CLK _SEL)........................................................................\
.. 373 
4.2. Division Clock Enable  Register (CLK_EN) ................................................................. 374 
CHAPTER 13-2: Watch Counter ........................................................................\
................375 
1. Overview of t he Watch Counter........................................................................\
.............376 
2. Configuration of  the Watch Counter........................................................................\
......377 
3. Interrupts of t he Watch Counter........................................................................\
.............378 
4. Explanation of Operations  and Setting Procedure Examples  of the Watch Counter .....379 
5. Registers of t he Watch Counter........................................................................\
.............381 
5.1. Watch Counter Read  Register (WCRD) ..................................................................... 382 
5.2. Watch Counter Rel oad Register (WCRL) ................................................................... 383 
5.3. Watch Counter Cont rol Register (WCCR) .................................................................. 384 
CHAPTER 14-1: Base Timer I/O Select Function ..............................................................387 
1. Overview ........................................................................\
............................................ ...388 
2. Confi guration ........................................................................\
....................................... ..389 
3. I/O  Mode........................................................................\
............................................ ....390 
3.1. Pins ........................................................................\
.............................................. ....... 391 
3.2. I/O  mode ........................................................................\
.......................................... ... 393 
4. Registers ........................................................................\
........................................... ....408 
4.1. I/O Select Register (BTSEL0123) ........................................................................\
....... 409 
4.2. I/O Select Regi ster (BTSEL4567) ........................................................................\
....... 411 
4.3. Software-based Simultaneous  Startup Register (BTSSSR) ....................................... 413 
FUJITSU SEMICO NDUCTOR LIMITED 
MN706-00002-1v0-E 
\05010\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 14-2: Base Timer ........................................................................\
......................415 
1. Overview of Base Timer ........................................................................\
........................416 
2. Block Diagram Of  Base Timer ........................................................................\
...............418 
3. Operations of  the Base Timer ........................................................................\
................421 
4. 32-bit mode  operations ........................................................................\
.......................... 423 
5. Base Time r Interrupt ........................................................................\
.............................. 425 
6. Starting the DMA  Controller (DMAC)........................................................................\
.....426 
7. Base Timer Register s ........................................................................\
............................427 
8. Notes on using the base ti mer ........................................................................\
...............428 
9. Descriptions of bas e timer functions........................................................................\
......429 
9.1. PWM timer function ........................................................................\
............................. 430  
9.1.1. 16-bit PWM timer operations........................................................................\
..............431 
9.1.2. One-shot operation ........................................................................\
............................43 2 
9.1.3. Interrupt causes and timing chart ........................................................................\
.......433 
9.1.4. Output waveforms ........................................................................\
..............................43 4 
9.1.5. PWM timer operation flowchart ........................................................................\
..........435 
9.1.6. Timer Control Registers (TMCR and TMCR2) and    Status Control Register (STC) used when the PWM timer is selected ...................436 
9.1.7. PWM Cycle Set Register (PCSR) ........................................................................\
......443 
9.1.8. PWM Duty Set Register (PDUT) ........................................................................\
........444 
9.1.9. Timer Register (TMR)........................................................................\
.........................445 
9.2. PPG time r function ........................................................................\
.............................. 44 6 
9.2.1. 16-bit PPG timer operations ........................................................................\
...............447 
9.2.2. Continuous operation ........................................................................\
.........................448  
9.2.3. One-shot operation ........................................................................\
............................44 9 
9.2.4. Interrupt causes and timing chart ........................................................................\
.......451 
9.2.5. PPG timer operation flowchart ........................................................................\
...........452 
9.2.6. Timer Control Registers (TMCR and TMCR2) and    Status Control Register (STC) used when the PPG timer is selected ....................453 
9.2.7. LOW Width Reload Register (PRLL) ........................................................................\
..460 
9.2.8. HIGH Width Reload Register (PRLH) ........................................................................\
461 
9.2.9. Timer Register (TMR)........................................................................\
.........................462  
9.3. Reload timer function ........................................................................\
.......................... 463  
9.3.1. Operations of the 16-bit reload timer........................................................................\
..464 
9.3.2. Reload timer operation flowchart ........................................................................\
.......467 
9.3.3. Timer Control Registers (TMCR and TMCR2) and   
Status Control Register (STC) used when the reload timer is selected ..................468 
9.3.4. PWM Cycle Set Register (PCSR) ........................................................................\
......476 
9.3.5. Timer Register (TMR)........................................................................\
.........................477 
9.4. PWC timer functi on ........................................................................\
............................. 478  
9.4.1. Operations of the PWC timer ........................................................................\
.............479 
9.4.2. Timer Control Registers (TMCR and TMCR2) and   
Status Control Register (STC) used when the PWC timer is selected ...................486 
9.4.3. Data Buffer Register (DTBF) ........................................................................\
..............493 
FUJITSU SEMICONDUCT OR LIMITED 
MN706-00002-1v0-E 
\05011\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 15: Multifunction Timer ........................................................................\
.............495 
1. Overview of Multifunction Timer ........................................................................\
............496 
2. Configuration of Mu ltifunction Timer........................................................................\
......497 
2.1. Block Diagram of  Multifunction Timer ........................................................................\
. 498 
2.2. Description of Each  Function Block ........................................................................\
.... 499 
2.3. I/O Pins of Mult ifunction Timer Unit........................................................................\
..... 505 
3. Operations of Mu ltifunction Timer ........................................................................\
..........508 
3.1. Example of Operation of Multifunction  Timer - 1......................................................... 509 
3.2. Example of Operation of Multifunction  Timer - 2......................................................... 516 
4. Registers of Mu ltifunction Timer ........................................................................\
............524 
4.1. Individual Notation and Common Notation of Channel Numbers in 
Descriptions of  Functions ........................................................................\
................ 525 
4.2. List of Registers  of Multifunction Timer ....................................................................... 527 
4.3. Details of Regi ster Functions ........................................................................\
.............. 529 
4.3.1. FRT Control Register A (TCSA) ........................................................................\
.........530 
4.3.2. FRT Control Register B (TCSB) ........................................................................\
.........538 
4.3.3. FRT Cycle Setting Register (TCCP)........................................................................\
...540 
4.3.4. FRT Count Value Register (TCDT) ........................................................................\
....542 
4.3.5. OCU Connecting FRT Select Register (OCFS) .........................................................543 
4.3.6. OCU Control Register A (OCSA)........................................................................\
........544 
4.3.7. OCU Control Register B (OCSB) ........................................................................\
.......548 
4.3.8. OCU Control Register C (OCSC) ........................................................................\
.......551 
4.3.9. OCU Compare Value Store Register (OCCP) ............................................................552 
4.3.10. WFG Control Register A (WFSA) ........................................................................\
.....554 
4.3.11. WFG Timer Value Register (WFTM)........................................................................\
.559 
4.3.12. NZCL Control Register (NZCL) ........................................................................\
........560 
4.3.13. WFG Interrupt Control Register (WFIR) ...................................................................564 
4.3.14. ICU Connecting FRT Select Register (ICFS) ...........................................................569 
4.3.15. ICU Control Register A (ICSA) ........................................................................\
.........570 
4.3.16. ICU Control Register B (ICSB) ........................................................................\
.........573 
4.3.17. ICU Capture value store register (ICCP)..................................................................574 
4.3.18. ADCMP  Control  Register A  (ACSA) ........................................................................\
.575 
4.3.19. ADCMP Control Register B (ACSB) ........................................................................\
.580 
4.3.20. ADCMP Compare Value Store Register  (ACCP)......................................................583 
4.3.21. ADCMP Compare Value Store Register , Down-count Direction Only (ACCPDN) ....585 
4.3.22. ADC Start Trigger Select Register (ATSA) ...............................................................587 
4.4. Details of OCU  Output Waveform ........................................................................\
....... 590 
4.5. Details of WFG  Output Waveform........................................................................\
....... 597 
5. Other Matters ........................................................................\
....................................... .605 
5.1. Connection of Model Containing Multiple MFT’s ........................................................ 606 
5.1.1. Selection of FRT Connected to OCU and ICU ...........................................................607 
5.1.2. PPG Timer Unit Connected to WFG ........................................................................\
..609 
5.2. Treatment of Event Dete ct Register and Interrupt ...................................................... 610 
FUJITSU SEMICONDUCT OR LIMITED 
MN706-00002-1v0-E 
\05012\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 16-1: PPG Configuration ........................................................................\
..........615 
1. Configuration ........................................................................\
....................................... ..616 
CHAPTER 16-2: PPG ........................................................................\
................................619 
1. Overview ........................................................................\
............................................ ...620 
2. Configuration and  Block Diagrams ........................................................................\
........621 
3. Oper ations ........................................................................\
.......................................... ...623 
3.1. PPG circuit operations ........................................................................\
........................ 624 
3.2. Timing generator  circuit operations ........................................................................\
..... 628 
4. Setup Procedure Exampl e........................................................................\
.....................630 
5. Registers ........................................................................\
........................................... ....632 
5.1. PPG Start Trigger Control Register 0 (TTCR0)........................................................... 634 
5.2. PPG Start Trigger Control Register  1 (TTCR1)........................................................... 636 
5.3. PPG Compare Register n (COMPn, where n=0 to  7) .............................................. 638 
5.4. PPG Start R egister (TRG)........................................................................\
................... 639 
5.5. Output Reverse  Register (REVC) ........................................................................\
....... 640 
5.6. PPG Operation Mode C ontrol Register (PPGC) ......................................................... 641 
5.7. PPG Reload Regist ers (PRLH, PRLL)........................................................................\
 643 
5.8. PPG Gate Function Control Registers    (GATEC0/GATEC4/GATEC4/GATEC8/GATEC12).................................................. 646 
6. Notes ........................................................................\
............................................... ......648 
CHAPTER 17: Quad Position & Revolution Counter .........................................................649 
1. Overview ........................................................................\
............................................ ...650 
2. Confi guration ........................................................................\
....................................... ..651 
3. Oper ations ........................................................................\
.......................................... ...652 
4. Registers ........................................................................\
........................................... ....665 
4.1. Quad Position & Revolution Counter Position Count Register (QPCR) ..................... 666 
4.2. QPRC Revolution Coun t Register (QRCR) ................................................................ 668 
4.3. QPRC Position Counter Co mpare Register (QPCCR) ............................................... 669 
4.4. QPRC Position and Revolution Coun ter Compare Register (QPRCR) ...................... 670 
4.5. QPRC Control Register (Q CR) ........................................................................\
........... 671 
4.6. QPRC Extension Cont rol Register (QECR) ................................................................ 676 
4.7. Low-Order Bytes of QPRC Interr upt Control Register (QICRL) ................................. 678 
4.8. High-Order Bytes of QPRC Interr upt Control Register (QICRH) ................................ 682 
4.9. QPRC Maximum Posi tion Register(QMPR) ............................................................... 686 
FUJITSU SEMICO NDUCTOR LIMITED 
MN706-00002-1v0-E 
\05013\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 18-1: A/D Converter ........................................................................\
.................687 
1. Configuration ........................................................................\
....................................... ..688 
2. Functions and  Operations ........................................................................\
.....................689 
3. Notes ........................................................................\
............................................... ......690 
CHAPTER 18-2: 10-bit A/D Converter ........................................................................\
.......691 
1. Overview ........................................................................\
............................................ ...692 
2. Confi guration ........................................................................\
....................................... ..693 
3. Explanation of  Operations ........................................................................\
.....................694 
3.1. A/D  conversi on operation ........................................................................\
.................... 695 
3.1.1. Scan conversion operation........................................................................\
.................696 
3.1.2. Priority conversion operation........................................................................\
..............698 
3.1.3. Priority levels and state transitions........................................................................\
.....699 
3.2. FIFO  operations ........................................................................\
.................................. 7 01 
3.2.1. FIFO operations in scan conversion ........................................................................\
..702 
3.2.2. Interrupts in scan conversion ........................................................................\
.............703 
3.2.3. FIFO operations in priority conversion .......................................................................705 
3.2.4. Interrupts in priority conversion ........................................................................\
..........706 
3.2.5. Restrictions on reading FIFO data registers in empty state .......................................707 
3.2.6. Bit placement selection for FIFO data registers .........................................................708 
3.3. A/D  comparison function ........................................................................\
..................... 709 
3.4. Star ting DMA ........................................................................\
...................................... . 710 
4. Setup procedure examples........................................................................\
.................... 711 
4.1. Scan conversion setup procedure example................................................................ 712 
4.2. Priority conversion se tup procedure example............................................................. 713 
4.3. Setting the co nversion time........................................................................\
................. 714 
5. Registers ........................................................................\
........................................... ....715 
5.1. A/D Control Register (ADCR)........................................................................\
.............. 716 
5.2. A/D Status Re gister (ADSR) ........................................................................\
............... 718 
5.3. Scan Conversion Control Register  (SCCR) ................................................................ 720 
5.4. Scan Conversion FIFO Stage Co unt Setup Register (SFNS) .................................... 722 
5.5. Scan Conversion FIFO  Data Register (SCFD) ........................................................... 723 
5.6. Scan Conversion Input Se lection Register (SCIS) ..................................................... 724 
5.7. Priority Conversion Co ntrol Register (PCCR) ............................................................. 725 
5.8. Priority Conversion FIFO St age Count Setup Register (PFNS) ................................. 727 
5.9. Priority Conversion FIFO  Data Register (PCFD) ........................................................ 728 
5.10. Priority Conversion Input  Selection Register (PCIS) ................................................ 729 
5.11. A/D Comparison Value Setup Register  (CMPD) ....................................................... 730 
5.12. A/D Comparison Cont rol Register (CMPCR) ............................................................ 731 
5.13. Sampling Time Select ion Register (ADSS)............................................................... 732 
5.14. Sampling Time Setu p Register (ADST).................................................................... 733 
5.15. Comparison Time Se tup Register (ADCT) ................................................................ 735 
FUJITSU SEMICO NDUCTOR LIMITED 
MN706-00002-1v0-E 
\05014\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 18-3: 12-bit A/D Converter ........................................................................\
.......737 
1. Overview ........................................................................\
...............................................738 
2. Confi guration ........................................................................\
....................................... ..739 
3. Explanation of  Operations ........................................................................\
.....................740 
3.1. Enabling operations of  the A/D converter ................................................................... 741 
3.2. A/D  conversi on operation ........................................................................\
.................... 742 
3.2.1. Scan conversion operation........................................................................\
.................743 
3.2.2. Priority conversion operation........................................................................\
..............745 
3.2.3. Priority levels and state transitions........................................................................\
.....746 
3.3. FIFO  operations ........................................................................\
.................................. 7 48 
3.3.1. FIFO operations in scan conversion ........................................................................\
..749 
3.3.2. Interrupts in scan conversion ........................................................................\
.............750 
3.3.3. FIFO operations in priority conversion .......................................................................752 
3.3.4. Interrupts in priority conversion ........................................................................\
..........753 
3.3.5. Validity of FIFO data ........................................................................\
........................... 754 
3.3.6. Bit placement selection for FIFO data registers .........................................................755 
3.4. A/D  comparis on function ........................................................................\
..................... 756 
3.5. Star ting DMA ........................................................................\
...................................... . 757 
4. Setup procedure examples........................................................................\
.................... 758 
4.1. A/D Operation Enable Setup Procedure Example ...................................................... 759 
4.2. Scan conversion set up procedure example................................................................ 760 
4.3. Priority conversion se tup procedure example............................................................. 761 
4.4. Setting the co nversion time........................................................................\
................. 762 
5. Registers ........................................................................\
........................................... ....763 
5.1. A/D Control Register (ADCR)........................................................................\
.............. 764 
5.2. A/D Status Re gister (ADSR) ........................................................................\
............... 766 
5.3. Scan Conversion Control Register  (SCCR) ................................................................ 768 
5.4. Scan Conversion FIFO Stage Co unt Setup Register (SFNS) .................................... 770 
5.5. Scan Conversion FIFO  Data Register (SCFD) ........................................................... 771 
5.6. Scan Conversion Input Se lection Register (SCIS) ..................................................... 773 
5.7. Priority Conversion Co ntrol Register (PCCR) ............................................................. 774 
5.8. Priority Conversion FIFO St age Count Setup Register (PFNS) ................................. 776 
5.9. Priority Conversion FIFO  Data Register (PCFD) ........................................................ 777 
5.10. Priority Conversion Input  Selection Register (PCIS) ................................................ 779 
5.11. A/D Comparison Value Setup Register  (CMPD) ....................................................... 780 
5.12. A/D Comparison Cont rol Register (CMPCR) ............................................................ 781 
5.13. Sampling Time Select ion Register (ADSS)............................................................... 782 
5.14. Sampling Time Setu p Register (ADST).................................................................... 783 
5.15. Comparison Time Se tup Register (ADCT) ................................................................ 785 
5.16. A/D Operation Enable Se tup Register (ADCEN) ...................................................... 786 
CHAPTER 18-4: A/D Timer Trigger Selection ....................................................................789 
1. Overview ........................................................................\
............................................ ...790 
2. Registers ........................................................................\
........................................... ....791 
2.1. Scan Conversion Timer Trigger Selection Register (SCTSL) ..................................... 792 
2.2. Priority Conversion Timer Trigger Selection Regi ster (PRTSL) .................................. 793 
FUJITSU SEMICONDUCT OR LIMITED 
MN706-00002-1v0-E 
\05015\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 19-1: Multi-function Serial Interface .................................................................795 
1. Overview of the Multi-function Serial Interface ..............................................................796 
CHAPTER 19-2: UART (Async Serial Interface) ................................................................797 
1. Overview of UART (A sync Serial Interface)................................................................... 798 
2. UART  Interrupt ........................................................................\
...................................... 799 
2.1. Receive interrupt and flag set timing........................................................................\
... 800 
2.2. Interrupt and flag set timing  when receive FIFO is used ............................................ 802 
2.3. Transmit interrupt  and flag set timing........................................................................\
.. 804 
2.4. Interrupt and flag set timing  when transmit FIFO is used ........................................... 805 
3. UART Operation ........................................................................\
....................................80 6 
4. Dedicated Baud  Rate Generator........................................................................\
...........814 
4.1. Baud rate  settings ........................................................................\
............................... 8 15 
5. Setting Procedure and Program Flow in Operation Mode 0 (Async Normal Mode).......819 
6. Setting Procedure and Program Flow in Operation Mode 1    (Async Multipro cessor Mode) ........................................................................\
............. 822 
7. UART (Async Serial In terface) Registers ......................................................................826 
7.1. Serial Control  Register (SCR) ........................................................................\
............. 827 
7.2. Serial Mode R egister (SMR) ........................................................................\
............... 830 
7.3. Serial Status  Register (SSR)........................................................................\
............... 833 
7.4. Extended Communication Co ntrol Register (ESCR) .................................................. 836 
7.5. Receive Data Register/Trans mit Data Register (RDR/TDR) ...................................... 839 
7.6. Baud Rate Generator Regist ers 1 and 0 (BGR1 and BGR0) ..................................... 841 
7.7. FIFO Control Re gister 1 (FCR1) ........................................................................\
......... 843 
7.8. FIFO Control Re gister 0 (FCR0) ........................................................................\
......... 846 
7.9. FIFO Byte R egister (FBYTE) ........................................................................\
.............. 850 
FUJITSU SEMICO NDUCTOR LIMITED 
MN706-00002-1v0-E 
\05016\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 19-3: CSIO (Clock Sync Serial Interface).........................................................853 
1. Outline of CSIO (Clock Sync Serial Interface) ............................................................... 854 
2. CSIO (Clock Sync Serial  Interface) interrupts ...............................................................855 
2.1. Receive interrupt and flag set  timing........................................................................\
... 856 
2.2. Interrupt occurrence and flag se t timing when receive FIFO is used ......................... 858 
2.3. Transmit interrupt occurrence and flag set timi ng ....................................................... 860 
2.4. Interrupt occurrence and flag se t timing when transmit FIFO is used ........................ 861 
3. CSIO (Clock Sync Serial  Interface) operations.............................................................. 862 
3.1. Normal transfer (I) ........................................................................\
............................... 862 
3.2. Normal  transfer (II) ........................................................................\
.............................. 867 
3.3. SPI tr ansfer (I) ........................................................................\
.................................. ... 872 
3.4. SPI tr ansfer (II) ........................................................................\
................................. ... 877 
4. Dedicated baud rate generator........................................................................\
..............882 
4.1. Baud rate  settings ........................................................................\
............................... 8 83 
4.2. CSIO (Clock Sync Serial Interf ace) setup procedure and program flow .................... 885 
5. CSIO (Clock Sync Serial  Interface) registers.................................................................887 
5.1. Serial Control  Register (SCR) ........................................................................\
............. 888 
5.2. Serial Mode R egister (SMR) ........................................................................\
............... 891 
5.3. Serial Status  Register (SSR)........................................................................\
............... 894 
5.4. Extended Communication Co ntrol Register (ESCR) .................................................. 896 
5.5. Receive Data Register/Trans mit Data Register (RDR/TDR) ...................................... 898 
5.6. Baud Rate Generator Regist ers 1 and 0 (BGR1 and BGR0) ..................................... 900 
5.7. FIFO Control Re gister 1 (FCR1) ........................................................................\
......... 902 
5.8. FIFO Control Re gister 0 (FCR0) ........................................................................\
......... 905 
5.9. FIFO Byte R egister (FBYTE) ........................................................................\
.............. 909 
CHAPTER 19-4: LIN Interface (Ver. 2.1)   
(LIN Communication Control Interface Ver. 2.1) ....................................... 911 
1. Overview of LIN Interface (Ver. 2.1) (LIN  Communication Control Interface Ver. 2.1) ...912 
2. LIN Interface (Ver . 2.1) Interrupts........................................................................\
..........913 
2.1. Receive interrupt and flag set  timing........................................................................\
... 914 
2.2. Interrupt and flag set timing  when receive FIFO is used ............................................ 916 
2.3. Transmit interrupt  and flag set timing........................................................................\
.. 918 
2.4. Interrupt and flag set timing  when transmit FIFO is used ........................................... 919 
3. Dedicated Baud Rate Generator........................................................................\
...........920 
3.1. Baud rate  settings ........................................................................\
............................... 9 21 
4. LIN Interface (Ver. 2.1) Operations........................................................................\
........925 
5. Operation Mode 3 (LIN Communi cation Mode) Setting Procedure and   
Program  Flow ........................................................................\
.....................................935 
6. LIN Interface (ver . 2.1) Registers........................................................................\
...........940 
6.1. Serial Control  Register (SCR) ........................................................................\
............. 941 
6.2. Serial Mode R egister (SMR) ........................................................................\
............... 945 
6.3. Serial Status  Register (SSR)........................................................................\
............... 947 
6.4. Extended Communication Co ntrol Register (ESCR) .................................................. 951 
6.5. Receive Data Register/Trans mit Data Register (RDR/TDR) ...................................... 953 
6.6. Baud Rate Generator Regist ers 1 and 0 (BGR1 and BGR0) ..................................... 955 
6.7. FIFO Control Re gister 1 (FCR1) ........................................................................\
......... 957 
6.8. FIFO Control Re gister 0 (FCR0) ........................................................................\
......... 960 
6.9. FIFO Byte R egister (FBYTE) ........................................................................\
.............. 964 
FUJITSU SEMICO NDUCTOR LIMITED 
MN706-00002-1v0-E 
\05017\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 19-5: I2C Interface (I2C Communications Control Interface).............................967 
1. Overview of I2C Interface (I2C Communications Control Interface)...............................968 
2. I
2C Interface  interrupt ........................................................................\
............................ 969 
2.1. I2C interface operation ........................................................................\
........................ 971 
2.2. Master mode ........................................................................\
....................................... 972 
2.3. Slav e mode ........................................................................\
....................................... 1 003 
2.4. Bus  error ........................................................................\
......................................... .. 1011 
3. Dedicated Baud Rate Generator........................................................................\
.........1012 
4. I
2C communication operation  flowchart examples.......................................................1014 
5. I
2C Interface R egisters ........................................................................\
........................1021 
5.1. I2C Bus Control Regi ster (IBCR)........................................................................\
....... 1022 
5.2. Serial Mode R egister (SMR) ........................................................................\
............. 1029 
5.3. I
2C Bus Status Regi ster (IBSR) ........................................................................\
......... 1031 
5.4. Serial Status  Register (SSR)........................................................................\
............. 1036 
5.5. Receive Data Register/Trans mit Data Register (RDR/TDR) .................................... 1040 
5.6. 7-bit Slave Address Mask Register (ISMK)............................................................... 1042 
5.7. 7-bit Slave Addr ess Register (ISBA) ........................................................................\
. 1043 
5.8. Baud Rate Generator Regist ers 1 and 0 (BGR1 and BGR0) ................................... 1044 
5.9. FIFO Control Re gister 1 (FCR1) ........................................................................\
....... 1045 
5.10. FIFO Control R egister 0 (FCR0)........................................................................\
..... 1048 
5.11. FIFO Byte R egister (FBYTE) ........................................................................\
.......... 1053 
CHAPTER 20-1: USB Clock Generation ........................................................................\
..1055 
1. Overview ........................................................................\
............................................ .1056 
2. Configuration and Block Di agram........................................................................\
........1057 
3. Explanation of  Operation ........................................................................\
.....................1058 
4. Setup Procedure Exampl e........................................................................\
...................1060 
5. Regist er List ........................................................................\
....................................... .1061 
5.1. USB Clock Setup Register (UCCR)........................................................................\
.. 1062 
5.2. USB-PLL Control R egister-1 (UPCR1) ..................................................................... 1063 
5.3. USB-PLL Control R egister-2 (UPCR2) ..................................................................... 1064 
5.4. USB-PLL Control R egister 3 (UPCR3) ..................................................................... 1065 
5.5. USB-PLL Control R egister 4 (UPCR4) ..................................................................... 1066 
5.6. USB-PLL Macro Status  Register (UP_STR) ............................................................. 1067 
5.7. USB-PLL Interrupt Enable  Register (UPINT_ENR) .................................................. 1068 
5.8. USB-PLL Interrupt Status  Register (UPINT_STR) .................................................... 1069 
5.9. USB-PLL Interrupt Clea r Register (UPINT_CLR) ..................................................... 1070 
5.10. USB Enable Request  Register (USBEN)................................................................ 1071 
6. Usage Prec autions........................................................................\
.............................. 1072 
FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
\05018\051 
MB9Axxx/MB9Bxxx  Series