Fujitsu Series 3 Manual
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8. Notes on using the base timer
8. Notes on using the base timer
This section provides notes on using the base timer.
Notes on setting the program common to each timer
It is prohibited to rewrite the following bits in the TMCR2 and TMCR registers during operation.
Rewriting of the bits must be performed befo re starting or after stopping the operation.
[TMCR2 bit 8], [TMCR bit 14, 13, 12] CKS3 to CKS0 : Clock selection bits
[bit 10, 9, 8] EGS2, EGS1, EGS0 : Measurement edge...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-463.png "Page 464
8. Notes on using the base timer
8. Notes on using the base timer
This section provides notes on using the base timer.
Notes on setting the program common to each timer
It is prohibited to rewrite the following bits in the TMCR2 and TMCR registers during operation.
Rewriting of the bits must be performed befo re starting or after stopping the operation.
[TMCR2 bit 8], [TMCR bit 14, 13, 12] CKS3 to CKS0 : Clock selection bits
[bit 10, 9, 8] EGS2, EGS1, EGS0 : Measurement edge...")
5. Base Timer Interrupt 5. Base Timer Interrupt This section provides a list of interrupt request flags, interrupt enable bits, and interrupt causes for each function of the base timer. Interrupt control bits and in terrupt causes for each function Ta b l e 5 - 1 shows the interrupt control bits and interrupt causes for each function. Table 5-1 Interrupt control bits and interrupt causes in each mode Status Control Register (STC) Interrupt request flag bit Interrupt request enable bit Interrupt causes Interrupt cause output signal UDIR: bit 0 UDIE: bit 4 Detection of an underflow DTIR: bit 1 DTIE: bit 5 Detection of a match in duty IRQ0 PWM timer function TGIR: bit 2 TGIE: bit 6 Detection of a timer start trigger IRQ1 UDIR: bit 0 UDIE: bit 4 Detection of an underflow IRQ0 PPG timer function TGIR: bit 2 TGIE: bit 6 Detection of a timer start trigger IRQ1 UDIR: bit 0 UDIE: bit 4 Detection of an underflow IRQ0 Reload timer function TGIR: bit 2 TGIE: bit 6 Detection of a timer start trigger IRQ1 OVIR: bit 0 OVIE: bit 4 Detection of an overflow IRQ0 PWC timer function EDIR: bit 2 EDIE: bit 6 Detection of the completion of measurement IRQ1 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 425 MB9Axxx/MB9Bxxx Series
6. Starting the DMA Controller (DMAC) 6. Starting the DMA Controller (DMAC) The DMAC can be started using the generation of an interrupt request by the base timer. DMA transfer operation using interrupt causes of the base timer The DMAC can be started using the generation of an interrupt cause by the base timer. Figure 6-1 gives an overview o f starting the DMAC using the base timer. Figure 6-1 Overview of starting the DMAC using the base timer Base timer CPU DMAC Use of the DMAC (1) Generation of an interrupt signal (2) Clears the interrupt causes by a DMA transfer request When the DMAC is used, it clears interrupt causes and eliminates the need for the CPU to clear them. Before starting the DMAC using the base timer, configure the DMAC. For settings and details on the DMAC, see Chapters DMAC and Interrupt. Figure 6-2 gives an example of a DMA transfer operation using an interrupt request by the base timer. Figure 6-2 Example DMA transfer operation Interrupt request from the base timer (2) Clears by receiving the DMA transfer request DMA transfer(1) Generation of an interrupt request (3) DMA transfer FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 426 MB9Axxx/MB9Bxxx Series
7. Base Timer Registers 7. Base Timer Registers This section provides register lists of the base timer in each mode. List of registers used when the 16-bit PWM timer is selected Table 7-1 List of registers used when the 16-bit PWM timer is selected Abbreviation Register name See TMCR Timer Control Register 9.1.6 TMCR2 Timer Control Register 2 9.1.6 STC Status Control Register 9.1.6 PCSR PWM Cycle Set Register 9.1.7 PDUT PWM Duty Set Register 9.1.8 TMR Timer Register 9.1.9 List of registers used when th e 16-bit PPG timer is selected Table 7-2 List of registers used when the 16-bit PPG timer is selected Abbreviation Register name See TMCR Timer Control Register 9.2.6 TMCR2 Timer Control Register 2 9.2.6 STC Status Control Register 9.2.6 PRLL LOW Width Reload Register 9.2.7 PRLH HIGH Width Reload Register 9.2.8 TMR Timer Register 9.2.9 List of registers used when the reload timer is selected Table 7-3 List of registers used when the reload timer is selected Abbreviation Register name See TMCR Timer Control Register 9.3.3 TMCR2 Timer Control Register 2 9.3.3 STC Status Control Register 9.3.3 PCSR PWM Cycle Set Register 9.3.4 TMR Timer Register 9.3.5 List of registers used when the PWC timer is selected Table 7-4 List of registers used when the PWC timer is selected Abbreviation Register name See TMCR Timer Control Register 9.4.2 TMCR2 Timer Control Register 2 9.4.2 STC Status Control Register 9.4.2 DTBF Data Buffer Register 9.4.3 FUJITSU SEMICONDUCT OR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 427 MB9Axxx/MB9Bxxx Series
8. Notes on using the base timer 8. Notes on using the base timer This section provides notes on using the base timer. Notes on setting the program common to each timer It is prohibited to rewrite the following bits in the TMCR2 and TMCR registers during operation. Rewriting of the bits must be performed befo re starting or after stopping the operation. [TMCR2 bit 8], [TMCR bit 14, 13, 12] CKS3 to CKS0 : Clock selection bits [bit 10, 9, 8] EGS2, EGS1, EGS0 : Measurement edge selection bits [bit 7] T32 : 32-bit timer selection bit (When the reload timer PWC function is selected) [bit 6, 5, 4] FMD2 to FMD0 : Timer function selection bits [bit 2] MDSE : Measurement mode (one-shot/continuous) selection bit When the FMD2 to FMD0 bits in the TMCR register ar e set to reset mode with 0b000, all registers of the base timer are initialized. Therefore, all registers must be set again. When the FMD2 to FMD0 bits in the TMCR register are set to reset mode with 0b000, settings for the bits other than the FMD2 to FMD0 bits in the TMCR register are ignored and initialized. Notes on using the 16-bi t PWM/PPG/reload timer If the interrupt request flag set timing coincides the clear timing, the flag set operation takes precedence and the clear operatio n is not performed. If the load timing and count timing of the down c ounter coincide, the load operation takes precedence. Set the timer function with the FMD2, FMD1, and FMD0 bits in the TMCR register, and then set the cycle, duty, HIGH width, and LOW width. In one-shot mode, if a restart is de tected at the end of counting, the c ount value is reloaded and the restart operation is started. Notes on using the PWC timer If the count start enable bit (CTEN) is set to 1, the counter is cleared. As the result, the data existed in the counter before the start is enabled becomes invalid. If the setting for PWC mode (FMD = 0b100) and the setting for starting measurement (CTEN = 1) are performed simultaneously in system reset/reset mode, the resultant operation may depend on the status of the last measurement signal. In continuous measurement mode, if a me asurement start edge is detected at the same time a restart is set, the counting is started immediately from 0x0001. If a restart is performed after the count operation has been started, the following operations may occur depending on the timing. If it coincides with a measurement end edge in pulse width one-shot measurement mode: The timer is restarted and waits for detection of a measurement start edge. However, a measurement end flag (EDIR) is set. If it coincides with a measurement end edge in pulse width continuous measurement mode: The timer is restarted and waits for detection of a measurement start edge. However, a measurement end flag (EDIR) is set and the measurement re sult at the time is transferred to the DTBF. When restarting the timer during operation, pay attention to flag operations as described above and use the interrupt control. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 428 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9. Descriptions of base timer functions This section explains each function of the base timer. Base timer functions 1. PWM timer function 2. PPG timer function 3. Reload timer function 4. PWC timer function FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 429 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.1. PWM timer function The function of the base timer can be set to either the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, or 16/32-bit PWC timer using the FMD2, 1, and 0 bits in the Timer Control Register. This section explains the timer functions available when PWM is set. 1. 16-bit PWM timer operations 2. One-shot operation 3. Interrupt causes and timing chart 4. Output waveforms 5. PWM timer operation flowchart 6. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PWM timer is selected 7. PWM Cycle Set Register (PC SR) 8. PWM Duty Set Register (PDUT) 9. Timer Register (TMR) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 430 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.1.1. 16-bit PWM timer operations In PWM timer operations, waveforms in the specified cycle from the detection of a trigger can be output in one-shot or continuously. The cycle of the output pulse can be controlled by changing the PCSR value. The duty ration can be controlled by changing the PDUT value. After writing data to the PCSR, be sure to write it to the PDUT. Continuous operation When a restart is disabled (RTGEN = 0) Figure 9-1 PWM operation timing chart (when a restart is disabled) Rising edge detection The trigger is ignored. Trigger m n o (1) (2) PWM output waveform (1) = T(n+1)ms (2) = T(m+1)msT : Count clock cycle m : PCSR value n : PCSR value When a restart is enabled (RTGEN = 1) Figure 9-2 PWM operation timing chart (when a restart is enabled) Rising edge detection Restarted by the trigger Trigger m n o (1) (2) PWM output waveform (1) = T(n+1)ms (2) = T(m+1)ms T : Count clock cycle m : PCSR value n: PDUT value FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 431 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.1.2. One-shot operation In one-shot operation, a single pulse of any width can be output using a trigger. When a restart is enabled, the counter is reloaded when an edge is detected during operation. One-shot operation When a restart is disabled (RTGEN = 0) Figure 9-3 One-shot operation timing chart (trigger restart is disabled) Rising edge detection The trigger is ignored. Trigger m n o (1) (2) PWM output waveform (1) = T(n+1)ms (2) = T(m+1)ms T : Count clock cycle m : PCSR value n : PDUT value When a restart is enabled (RTGEN = 1) Figure 9-4 One-shot operation timing chart (trigger restart is enabled) Rising edge detection Restarted by the trigger (1) (2) Trigger m n o PWM output waveform (1) = T(n+1)ms (2) = T(m+1)ms T : Count clock cycle m : PCSR value n : PDUT value FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 432 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.1.3. Interrupt causes and timing chart This section explains interrupt causes and a timing chart. Interrupt causes and timing char t (PWM output: Normal polarity) As a time from trigger input to loading of the counter va lue, T is required for software triggering or 2T to 3T (T: machine cycle) fo r external triggering. Figure 9-5 shows the interrupt causes and a timing chart wher e the cycle set value = 3 an d duty value = 1. Figure 9-5 Interrupt causes and timing chart of the PWM timer 2T to 3T (External trigger) Trigger Load Count clock Count value PWM output waveform Interrupt 0x00030x0001 0x00020x0000 0x0003 0x0002 Start edge TGIR Match in duty DTIRUnderflowUDIR 0xXXXX FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 433 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.1.4. Output waveforms This section explains the PWM output. How to make an all-LOW or all-HIGH PWM output Figure 9-6 shows how to make all-LOW PWM output and Figure 9-7 shows how to make all-HIGH output. Figure 9-6 Example of outputting all-LOW level waveforms as PWM output Duty value PWM output waveform 0x00020x00010x0000 The duty value is reduced gradually.0xXXXX Underflow interrupt An underflow interrupt sets the PMSK to 1. The output changes to all-LOW level waveforms from the cycle where the setting is made. Figure 9-7 Example of outputting all-HIGH level waveforms as PWM output PWM output waveform The duty value is increased gradually. When the duty match in terrupt causes the duty value to equal to the cycle set value, the output changes to all-HIGH level waveforms in the next cycle. Duty match interrupt FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 434 MB9Axxx/MB9Bxxx Series