Fujitsu Series 3 Manual
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3. Cortex-M3 Architecture
SysTick Timer
SysTick Timer is a system timer for OS task management integrated into NVIC.
This series generates STCLK through dividing HCLK by eight and sets the values of SysTick
Calibration Value Register (0xE000E01C) as shown below:
[Bit 31] : NOREF = 0
[Bit 30] : SKEW = 1
[Bit 23:0] : TENMS = 0x0186A0 (100000)*1
*1 : TENMS value is set to a value which becomes 10ms when 1/8 clock of HCLK is input to STCLK and that HCLK is in 80MHz (10MHz in...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-45.png "Page 46
3. Cortex-M3 Architecture
SysTick Timer
SysTick Timer is a system timer for OS task management integrated into NVIC.
This series generates STCLK through dividing HCLK by eight and sets the values of SysTick
Calibration Value Register (0xE000E01C) as shown below:
[Bit 31] : NOREF = 0
[Bit 30] : SKEW = 1
[Bit 23:0] : TENMS = 0x0186A0 (100000)*1
*1 : TENMS value is set to a value which becomes 10ms when 1/8 clock of HCLK is input to STCLK and that HCLK is in 80MHz (10MHz in...")
2. Memory Architecture 2. Memory Architecture This chapter shows this series memory architecture. For this series, 4G-byte address space is available. Maximum 1M-byte FLASH area, maximum 512K-byte on-chip SRAM area, and maximum 512K-byte code SRAM area are defined. Also, as an external bus area, 2G-byte area from 0x60000000 to 0xDFFFFFFF is defined. An external memory device can be connected to this area. Clause 2.1 illustrates the memory map, and Clause 2.2 illustrates the peripheral memory map. For the details of Cortex-M3 private peri pheral area and bit-band area shown in Figure 2-1, see Cortex-M3 T echnical Reference Manual. FUJITSU SEMICONDUCT OR LIMITED CHAPTER 1: System Overview MN706-00002-1v0-E 5 MB9Axxx/MB9Bxxx Series
2. Memory Architecture 2.1. Memory Map Figure 2-1 illustrates this series memory map. Figure 2-1 Memory Map 0x4000 _0000 0x4000 _1000 0x4001 _0000 0x4001 _1000 0x 4001 _2000 0x 4001 _3000 0x4001 _5000 0x4001 _6000 0x4002 _0000 0x4002 _1000 0x4002 _2000 0x4002 _4000 0x4002 _5000 0x4002 _6000 0x4002 _7000 0x4002 _8000 0x4002 _E000 0x4002 _F000 0x4003 _1000 0x4003 _0000 0x4003 _2000 0x4003 _3000 0x4003 _4000 0x4003 _5000 0x4003 _6000 0x4003 _7000 0x4003 _8000 0x4003 _9000 0x4003 _A000 0x4003 _B000 0x4003 _F000 0x4004 _0000 0x4005 _0000 0x 4006 _0000 0x4006 _1000 0x4006 _2000 0x4006 _3000 0x 4006 _4000 0x 41FF _FFFF FLASH I/F CRG SW WDT Reserved Dual Input Timer MFT ch0 MFT ch1 PPG Base Timer QPRC A/DC EXTI CR CALIB Reserved Int-Req. Read Reserved GPIO/MODE LVD USB CLK Can Prescaler Reserved MFS CRC Watch Counter EXT - bus I/F USB ch0 CAN ch1 Reserved DMAC Reserved CAN ch0 USB ch1 Reserved Reserved Reserved Reserved HW WDT Reserved 0x0000 _0000 0x0010 _4000 0x0010 _0000 0x2008 _0000 0x2000 _0000 0x1FF8 _0000 0x2200 _0000 0x2400 _0000 0x4000 _0000 0x4200 _0000 0x4400 _0000 0x6000 _0000 0xE000 _0000 0xE010 _0000 0xFFFF _FFFF Code SRAM Security/CR Trim Reserved On Chip SRAM 32 Mbyte Bit band alias External Device Area Reserved 32 Mbyte Bit band alias Reserved Cortex -M3 Priv te a Peripherals Peripherals Reserved Reserved FLASH Peripherals Area Do not access to reserve d area . For the details of flash memory, see Flash Programming Manual. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 1: System Overview MN706-00002-1v0-E 6 MB9Axxx/MB9Bxxx Series
2. Memory Architecture 2.2. Peripheral Address Map Table 2-1 shows this series peripheral address map. Table 2-1 Peripheral Address Map Start Address End Address Bus DMAC TransferPeripheral Register Map Details 0x4000_0000 0x4000_0FFF FLASH IF Register FLASH_IF *1 0x4000_1000 0x4000_FFFF AHB Disabled Reserved - - 0x4001_0000 0x4001_0FFF Clock and Reset Control Clock / Reset Chapter 2 Chapter 3 Chapter 5 Chapter 10 0x4001_1000 0x4001_1FFF Hardware Watchdog Timer HWWDT Chapter 11 0x4001_2000 0x4001_2FFF Software Watchdog Timer SWWDT Chapter 11 0x4001_3000 0x4001_4FFF Reserved - - 0x4001_5000 0x4001_5FFF Dual Timer Dual_ Timer Chapter 12 0x4001_6000 0x4001_FFFF APB0 Disabled Reserved - - 0x4002_0000 0x4002_0FFF Multi-function Timer unit0 MFT Chapter 15 0x4002_1000 0x4002_1FFF Multi-function Timer unit1 MFT Chapter 15 0x4002_2000 0x4002_3FFF Reserved - - 0x4002_4000 0x4002_4FFF PPG PPG Chapter 16 0x4002_5000 0x4002_5FFF Base Timer Base Timer Base Timer Selector Chapter 14-1 Chapter 14-2 0x4002_6000 0x4002_6FFF QPRC QPRC Chapter 17 0x4002_7000 0x4002_7FFF A/D Converter A/DC Chapter 18-2 Chapter 18-3 0x4002_8000 0x4002_DFFF Reserved - - 0x4002_E000 0x4002_EFFF Internal CR Trimming CR Trim Chapter 2 0x4002_F000 0x4002_FFFF APB1 Enabled Reserved - - FUJITSU SEMICONDUCTOR LIMITED CHAPTER 1: System Overview MN706-00002-1v0-E 7 MB9Axxx/MB9Bxxx Series
2. Memory Architecture Start Address End Address Bus DMACTransferPeripheral Register Map Details 0x4003_0000 0x4003_0FFF External Interrupt EXTI Chapter 7 0x4003_1000 0x4003_1FFF Interrupt Source Check Register INT-Req READ Chapter 6 0x4003_2000 0x4003_2FFF Reserved - - 0x4003_3000 0x4003_3FFF GPIO GPIO Chapter 9 0x4003_4000 0x4003_4FFF Reserved - - 0x4003_5000 0x4003_5FFF Low Voltage Detection LVD Chapter 4 0x4003_6000 0x4003_6FFF USB Clock Generation Circuit USB Clock Chapter 20-1 0x4003_7000 0x4003_7FFF CAN Pre-scaler CAN Prescaler Chapter 21-1 0x4003_8000 0x4003_8FFF Multi-function Serial MFS Chapter 19-2 Chapter 19-3 Chapter 19-4 Chapter 19-5 0x4003_9000 0x4003_9FFF CRC CRC Chapter 22 0x4003_A000 0x4003_AFFF Watch Counter Wa t c h Counter Chapter 13-1 Chapter 13-2 0x4003_B000 0x4003_EFFF Reserved - - 0x4003_F000 0x4003_FFFF APB2 Enabled External Bus I/F EXT-Bus I/F Chapter 23 0x4004_0000 0x4004_FFFF USB ch0 USB Chapter 20-2 Chapter 20-3 0x4005_0000 0x4005_FFFF USB ch1 USB Chapter 20-2 Chapter 20-3 0x4006_0000 0x4006_0FFF DMAC Register DMAC Chapter 8 0x4006_1000 0x4006_1FFF Reserved - - 0x4006_2000 0x4006_2FFF CAN ch0 CAN Chapter 21-2 0x4006_3000 0x4006_3FFF CAN ch1 CAN Chapter 21-2 0x4006_4000 0x41FF_FFFF AHB Enabled Reserved - - *1 : For the details of FLASH IF Register, see Flash Programming Manual. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 1: System Overview MN706-00002-1v0-E 8 MB9Axxx/MB9Bxxx Series
3. Cortex-M3 Architecture 3. Cortex-M3 Architecture This chapter explains the core architecture used in this series. Cortex-M3 core block architecture used in this series is as follows: Cortex-M3 Core NVIC MPU DWT ITM FPB ETM SWJ-DP TPIU ROM Table Cortex-M3 Core High-performance 32-bit processor core (ARM Cortex-M3 core) is equipped with this series. This peripheral manual does not describe the details of Cortex-M3 core. For the details, see Cortex-M3 Technical Reference Manual. Cortex-M3 Core Version For the version of Cortex-M 3 core, See Data sheet. NVIC(Nested Vectored Interrupt Controller) For this series, 1 NMI(non-maskable interrupt) and 48 peripheral interrupts (IRQ0 to IRQ47)*1 can be used. Also, interrupt priority register (from 0xE000E400) is co mprised of 4 bits, and 16 interrupt priority levels can be configured. For the details of peripheral interrupts, see another chapter Interrupt, and for NMI operations, see also another chapter External Interrupt and NMI Control Block. NMI terminal is assigned for a combined use with a general-purpose port. Its default value after a reset release is set to the general-purpose port, and NMI input is masked. When NMI is used, enable NMI in the port setting. For the details, see another chapter I/O Port. *1 : Cortex-M3 Technical Reference Manual defines an exception type: IRQ as an external interrupt. In this peripheral manual, to distinguish from an interrupt by an external terminal External Interrupt and NMI Control Block, the exception type: IRQ is indicated as a peripheral interrupt. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 1: System Overview MN706-00002-1v0-E 9 MB9Axxx/MB9Bxxx Series
3. Cortex-M3 Architecture SysTick Timer SysTick Timer is a system timer for OS task management integrated into NVIC. This series generates STCLK through dividing HCLK by eight and sets the values of SysTick Calibration Value Register (0xE000E01C) as shown below: [Bit 31] : NOREF = 0 [Bit 30] : SKEW = 1 [Bit 23:0] : TENMS = 0x0186A0 (100000)*1 *1 : TENMS value is set to a value which becomes 10ms when 1/8 clock of HCLK is input to STCLK and that HCLK is in 80MHz (10MHz in 1/8 case). The value of TENMS is not always 10ms because HCLK can be changed to another frequency in the clock control block. Therefore, it is required to calculate an appropriate interrupt timing according to HCLK frequency. DWT(Data Watchpoint & Trace Unit) This series is equipped with DWT to use as the debug function. DWT contains four comparators, and each comparator can be set as a hardware watchpoint. ITM(Instrumentation Trace Macrocell) This series is equipped with ITM as a debug function. ITM is an optional application driven trace source th at supports printf style debugging. The operation system (OS) and application event are traced, an d the system diagnostic information is sent. FPB(Flash Patch & Breakpoint) FPB has the following functions: Hardware Breakpoint function The function of remapping from Code memory space (FLASH) to Sy stem space (On-chip SRAM). FPB is equipped with six instruction comparators and two literal comparators. MPU(Memory Protection Unit) This series is equipped with a Cortex-M3 optional component MPU, and maximum eight areas can be defined. ETM(Embedded Trace Macrocell) This series is equipped with a Cortex-M3 optional component ETM to support instruction trace. SWJ-DP This series is equipped with SWJ-DP to support both serial wire protocol and JTAG protocol. TPIU(Trace Port Interface Unit) ETM/ITM trace information is output via TPIU. ROM Table ROM table provides the address information of a debug component to an external debug tool. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 1: System Overview MN706-00002-1v0-E 10 MB9Axxx/MB9Bxxx Series
4. Mode FUJITSU SEMICONDUCTOR LIMITED CHAPTER: System Overview FUJITSU SEMICONDUCTOR CONFIDENTIAL 12 4. Mode This chapter explains operating modes. In this product line, the following operating modes can be used: User Mode Internal ROM(Flash) Startup : CPU obtains a re set vector from Flash and starts operations. Serial Writer Mode Flash serial write is enabled. * : For the details of this mode, see Flash Programming Manual. Operating modes are determined after a release of resp ective power-on reset, low voltage detection reset, and INITX pin input reset. * : For the details of power consumption control and clock selection modes, see other chapters Low-power Mode and Clock. 4.1. How to Set Operating Mode Operating modes are configured by MD pins’ (MD1 and MD0) inputs. MD Pin MD1 MD0 Mode 0 0 User Mode Internal ROM(Flash) Startup 0 1 Serial Writer Mode 1 0 Configuration Prohibited 1 1 Configuration Prohibited 4.2. Startup Sequence Processes to determine operating modes in the startup sequence are shown below: 1. MD Terminal Sampling 2. Determining Operating Mode and Retaining Mode Data The descriptions of these processes are as follows: 1. MD Terminal Sampling Operating mode is configured by MD terminal inputs (MD1, MD0). These inputs are sampled by power-on reset, low-voltage detecti on reset, and INITX pin input reset. Until each reset, which is the sampling factor, is re leased, MD1 and MD0 terminal inputs need to be determined. 2. Determining Operating Mode and Retaining Mode Data MD1 and MD0 which are sampled by respective resets are retained until respective resets are input again. Operating modes are determined by the retained MD1 and MD0. Therefore, even MD1 and MD0 are changed after a reset is released, it does not affect an operating mode. CHAPTER 1: System Overview MN706-00002-1v0-E 11 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 12 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Chapter: Clock This chapter explains the operating clock. 1. Clock Generation Unit Overview 2. Clock Generation Unit Configuration/Block Diagram 3. Clock Generation Unit Operations 4. Clock Setup Procedure Examples 5. Clock Generation Unit Register List 6. Clock Generation Unit Usage Precautions CODE: 9BFCLOCK-E02.1 CHAPTER 2-1: Clock MN706-00002-1v0-E 13 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 1. Clock Generation Unit Overview This section provides an overview of the clock generation unit. The clock generation unit generates various types of clocks used to operate the MCU. Source clock is the generic name for external and internal oscillation clocks of this MCU. The following five types of clocks are source clocks: Main clock (CLKMO) Sub clock (CLKSO) High-speed CR clock (CLKHC) Low-speed CR clock (CLKLC) PLL clock (CLKPLL) Select one from the source clock. In this chapter, th e selected clock is referred to as the master clock.The master clock is a source of internal bus clocks used to operate this MCU. Dividing the master clock frequency can generate a base clock. In addition, dividing the base clock can generate each bus clock. In this chapter, the base clock and bus clocks are referred to as internal bus clocks.The following five types of clocks are internal bus clocks: Base clock (FCLK/HCLK) APB0 bus clock (PCLK0) APB1 bus clock (PCLK1) APB2 bus clock (PCLK2) TRACE clock (TPIUCLK) In addition to source clocks, the master clock, and internal bus clocks, the following clocks are provided: USB-PLL clock CAN prescaler clock Software watchdog timer count clock The following shows th e features of the clock generation unit. It can be set the oscillation stabilization wait time of the main clock (CLKMO). It can be set the interrupt which generates at completing the oscillation stabilization wait time of the main clock (CLKMO). It can be set the oscillation stabilization wait time of the sub clock (CLKSO). It can be set the interrupt which generates at completing the oscillation stabilization wait time of the sub clock (CLKSO). It can be set the oscillation stabilization wait time of the PLL clock (CLKPLL). It can be set the interrupt which generates at completing the oscillation stabilization wait time of the PLL clock (CLKPLL). It can be set the PLL multiplication ratio. It can be selected the master clock. It can be set the frequency division ratio of each internal bus clock frequency. It can be selected run or stop of the APB1 and APB2 bus clocks. It can be set the frequency division ratio of th e software watchdog timer count clock frequency. It can be set run/stop of the software watchdog timer count clock. It can be set the software watchdog timer count operation in debug mode. It in cludes registers for enabling clock-related inte rrupts, checking in terrupt status, and clearing interrupt causes. CHAPTER 2-1: Clock MN706-00002-1v0-E 14 MB9Axxx/MB9Bxxx Series