Fujitsu Series 3 Manual
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3. Explanation of Operations
3.3.2. Interrupts in scan conversion
This section explains interrupts in scan conversion.
Figure 3-6 FIFO interrupt settings and FIFO operations
FIFO interrupt
request FIFO stage
count settingValid FIFO
stage count
N=5(6stages)
N=3(4stages)
FIFO readout
A/D conversion
Stop123456Stop123456Stop1 Stop
Flag clear
Flag clear
When conversion data for the number of FIFO stages (N + 1) set in SFS [3:0] in the Scan Conversion FIFO
Stage Count Setup Register (SFNS)...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-785.png "Page 786
3. Explanation of Operations
3.3.2. Interrupts in scan conversion
This section explains interrupts in scan conversion.
Figure 3-6 FIFO interrupt settings and FIFO operations
FIFO interrupt
request FIFO stage
count settingValid FIFO
stage count
N=5(6stages)
N=3(4stages)
FIFO readout
A/D conversion
Stop123456Stop123456Stop1 Stop
Flag clear
Flag clear
When conversion data for the number of FIFO stages (N + 1) set in SFS [3:0] in the Scan Conversion FIFO
Stage Count Setup Register (SFNS)...")
![Page 787
3. Explanation of Operations
3. One-shot mode for multiple channels
To generate an interrupt after the completion of conversion of the multiple specified channels, set the
FIFO stage count according to the number of channe ls. If eight channels are selected, set the FIFO
stage count by setting SFS [3:0] = 0x7. When the conv ersion of the last one of the selected channels
is completed, SCIF is set to 1.
An interrupt can be generated at any timing before scan completion by setting SFS [3:0] to a...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-786.png "Page 787
3. Explanation of Operations
3. One-shot mode for multiple channels
To generate an interrupt after the completion of conversion of the multiple specified channels, set the
FIFO stage count according to the number of channe ls. If eight channels are selected, set the FIFO
stage count by setting SFS [3:0] = 0x7. When the conv ersion of the last one of the selected channels
is completed, SCIF is set to 1.
An interrupt can be generated at any timing before scan completion by setting SFS [3:0] to a...")
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3. Explanation of Operations
3.3.4. Interrupts in priority conversion
This section explains interrupts in priority conversion.
When conversion data for the number of FIFO stages (N + 1) set in PFS [1:0] in the Priority Conversion
FIFO Stage Count Setup Register (PFNS) is written in FIFO, the interrupt request bit (PCIF) in the A/D
Control Register (ADCR) is set to 1. If the interrupt en able bit (PCIE) is set to 1, an interrupt request is
generated to the CPU.
The following explains FIFO...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-788.png "Page 789
3. Explanation of Operations
3.3.4. Interrupts in priority conversion
This section explains interrupts in priority conversion.
When conversion data for the number of FIFO stages (N + 1) set in PFS [1:0] in the Priority Conversion
FIFO Stage Count Setup Register (PFNS) is written in FIFO, the interrupt request bit (PCIF) in the A/D
Control Register (ADCR) is set to 1. If the interrupt en able bit (PCIE) is set to 1, an interrupt request is
generated to the CPU.
The following explains FIFO...")
3. Explanation of Operations 3.3.6. Bit placement selection for FIFO data registers This section explains bit placement selection for FIFO data registers. The A/D converter can change the bit placement for the conversion results in the Scan Conversion FIFO Data Register (SCFD) and Priority Conversion FIFO Da ta Register (PCFD) with the FDAS bit in the A/D Status Register (ADSR) ( Figure 3-7). Setting the FDAS bit to 1 places 12-bit A/D conversion results (SD11 to SD0, PD11 to PD0) on the LSB side (bit 27:16) when a FIFO data re gister is read. Placement of the least significant 16 bits of a FIFO data register does not change. FIFO is shifted, regardless of the set value of the FDAS bit, by read ing bit 31:24 (for a byte access), bit 31:16 (for a half word access), or bit 31:0 (for a word access) of a FIFO data register. Figure 3-7 FIFO data register bit placement FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 755 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.4. A/D comparison function The A/D comparison function compares A/D conversion results and generates interrupts. To use the comparison function, set the CMPEN bit in the A/D Comparison Control Register (bit 7 in the CMPCR register) to 1. The values set in the A/D Comparison Value Setup Register (CMPD) are compared with the most significant 10 bits (AD11:2) of the A/D conversion result. If the comparison result satisfies the conditions set in the A/D Comparison Control Register (CMPCR) , the A/D comparison interrupt bit (CMPIF) in the ADCR register is set to 1. If the interrupt enable bit (CMPIE) is 1, an interrupt is generated to the CPU. Two bits (bit 1, bit 0) on the LSB side are not compared. Because the result of A/D conversion, regardless of scan or priority, is compared before it is written to FIFO, com parison is possible when FIFO is full. If CMD1 is set to 1 (to generate an interrupt when the result is equal to or more than the CMPD set value), CMPIF is set to 1 when the conversion result is equal to the value in the A/D Comparison Value Setup Register. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 756 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.5. Starting DMA The A/D converter can start DMA transfer with a scan conversion FIFO stage count interrupt request. The A/D converter can transfer scan FIFO data by connecting the interrupt signal of scan conversion from the A/D converter to DMA and starting DMA. By setting the scan FIFO stage count for interrupt generation to 0 (an interrupt is generated when a conversion re sult is stored in the first FIFO stage), DMA transfer can be performed in conjunction with A/D conversion. The setting in the DMA Transfer Request Selection Regi ster of the interrupt controller as to whether the A/D converter scan conversion interrupt signal is connected to the CPU or DMAC should be made for DMA transfer. Figure 3-8 DMA transfer operation F IF O int errupt request (DM A s tart reques t) F IFO stage se t Valid FI FO st age c ount N=0(1s tage) FIFO reado ut(D MA t rans fer) A/ D conv ers io nStop 1 2 3 4 5 6 St op 123456St op Clear by DMAC A/D staret 78 C l ear b y D MAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 757 MB9Axxx/MB9Bxxx Series
4. Setup procedure examples 4. Setup procedure examples This section provides examples of setup procedures for the 12-bit A/D converter. 4.1 A/D Operation Enable Setup Procedure Example 4.2 Scan conversion setup procedure example 4.3 Priority conversion setup procedure example 4.4 Setting the conversion time FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 758 MB9Axxx/MB9Bxxx Series
4. Setup procedure examples 4.1. A/D Operation Enable Setup Procedure Example This section provides an A/D operation enable setup procedure example. Set the period of operation enable state transitions Poll the operation enable state Figure 4-1 A/D Operation Enable Setup Procedure Example FUJITSU SEMICONDUCT OR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 759 MB9Axxx/MB9Bxxx Series
4. Setup procedure examples 4.2. Scan conversion setup procedure example This section provides a scan conversion setup procedure example. Scan conversion by software startup Set A/D conversion channels to ch.1 and ch.3 Set different sampling times for ch.1 and ch.3 Set the comparison time Read the least significant 16 bits of FIFO data and check data validity by the INVL bit After checking that data is valid, read the most significant 16 bits of FIFO data Figure 4-2 Scan conversion setup procedure example Start Initial settings - Set A/D conversion channels (set SCIS0 to ch.1, ch.3) - Set sampling times(set ADST0, ADST1, ADSS) - Set the comparison time (set ADCT:CT) - Set FIFO data placement (write ADSR:FDAS=1) - No comparison function used (write CMPCR:CMPEN=0) - No interrupt used (write ADCR:SCIE=0) - Clear FIFO (write SCCR:SFCLR=1) - Set a conversion mode (write SCCR:RPT=0) - Start the A/D software (write SCCR:SSTR=1) End Check data validity SCFD:INVL=0? Yes No Read the least significant 16 bits of FIFO data (the SCFD register) Check data validity SCFD:INVL=0? Yes No Read the most significant 16 bits of FIFO data (the SCFD register) (read the A/D conversion results of ch.1) Read the most significant 16 bits of FIFO data (the SCFD register) (read the A/D conversion results of ch.3) Read the least significant 16 bits of FIFO data (the SCFD register) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 760 MB9Axxx/MB9Bxxx Series
4. Setup procedure examples 4.3. Priority conversion setup procedure example This section provides a priority conversion setup procedure example. Priority conversion at priority level 2 by timer start Conversion channels are ch.1 and ch.3 Set different sampling times for ch.1 and ch.3 Set the comparison time Read 32 bits of FIFO data by using an interrupt Read FIFO by the specified stage count Figure 4-3 Priority conversion setup procedure example FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 761 MB9Axxx/MB9Bxxx Series
4. Setup procedure examples
4.4. Setting the conversion time
The conversion time of the A/D converter is sampling time + comparison time. Two
sampling time settings can be applied to each channel. This section explains how to set and
calculate the conversion time.
Example of setting the sampling time
A sampling time is set in each of Sampling Time Setup Registers 0 and 1 (ADST0 and ADST1). Using
Sampling Time Selection Registers (ADSS3 to 0), whether Sampling Time Setup Registers 0 or 1 is used to
provide the value can be selected for each channel. This allows you to set different sampling times for
channels with different external impedances.
Sampling time = Base clock (HCLK) cycle × {(ST set value + 1) × STX setting multiplier + 1}
When
STXx2, STXx1, and STXx0 = 000 (STx4 to STx0 set values mu
ltiplied by 1) are set, set STx4 to
STx0 to 3 or more (2 or less must not be set).
For setting the sampling time, refer to the Electrical Char acteristics in the data sheet to make sure that
an appropriate time should be selected in accordance with an external impedance of an input channel, an
analog power supply voltage (AVCC) , and a base clock (HCLK) cycle.
Example of setting the comparison time
The comparison time is set in the Comparison Time Setup Register (ADCT).
Comparison time = Compare clock cycle × 14
Compare clock cycle = Base clock (HCLK) cycle × (CT set value + 2)
Fo r settin g th
e
compare clock cycle, refer to the Electrical Characteristics in the data sheet to make
su re
th at an
appropriate time should be selected in accordance with an analog power supply voltage
(AVCC) and a base clock (HCLK) cycle.
If the sampling time or compare clock cycle fails to meet the electrical characteristics of the A/D
converter, the A/D conversion accuracy may be degraded.
Example of conversion time calculation (when HCLK = 80 MHz (12.5 ns cycle))
(1) Sampling time
When ST04 to 00 = 17 and STX02, STX01, and STX00 = 000 (multiplied by 1)
Sampling time = 12.5 ns × {(17 + 1) × 1 + 1} = 237.5 ns
When ST14 to 10 = 19 and STX12, STX11, and STX10 = 001 (multiplied by 4)
Sampling time = 12.5 ns × {(19 + 1) × 4 + 1} = 1012.5 ns
(2) Comparison time
When CT02 to 00 = 3
Compare clock cycle = 12 .5 ns × (3 + 2) = 62.5 ns
Comparison time = 62.5 ns × 14 = 875 ns
(3) Conversion time By adding (1) and (2) together:
Conversion time for chan nels specified with the ADST0 register = 1112.5 ns
Conversion time for chan nels specified with the ADST1 register = 1887.5 ns
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 18-3: 12-bit A/D Converter
MN706-00002-1v0-E
762
MB9Axxx/MB9Bxxx Series
5. Registers 5. Registers This section explains the configuration and functions of the registers used for the \ 12-bit A/D converter. List of registers for the 12-bit A/D converter Abbreviation Register name See ADCR A/D Control Register 5.1 ADSR A/D Status Register 5.2 SCCR Scan Conversion Control Register 5.3 SFNS Scan Conversion FIFO Stage Count Setup Register 5.4 SCFD Scan Conversion FIFO Data Register 5.5 SCIS Scan Conversion Input Selection Register 5.6 PCCR Priority Conversion Control Register 5.7 PFNS Priority Conversion FIFO Stage Count Setup Register 5.8 PCFD Priority Conversion FIFO Data Register 5.9 PCIS Priority Conversion Input Selection Register 5.10 CMPD A/D Comparison Value Setup Register 5.11 CMPCR A/D Comparison Control Register 5.12 ADSS Sampling Time Selection Register 5.13 ADST Sampling Time Setup Register 5.14 ADCT Comparison Time Setup Register 5.15 ADCEN A/D Operation Enable Setup Register 5.16 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 763 MB9Axxx/MB9Bxxx Series
5. Registers 5.1. A/D Control Register (ADCR) The A/D Control Register (ADCR) performs interrupt flag display and interrupt enable control. bit 15 14 13 12 11 10 9 8 Field SCIF PCIF CMPIFRes ervedSCIE PCIE CMPIE OVRIE Attribute R/W R/W R/W - R/W R/W R/W R/W Initial value 0 0 0 X 0 0 0 0 [bit 15] SCIF: Scan conversion interrupt request bit When conversion values are written up to the stage count specified in the Scan Conversion FIFO Stage Count Setup Register (SFNS) , this bit is set to 1. The read value of Read-Modify-Write access is 1 regardless of the bit value. Description Bit Read Write 0 Conversion result is not stored. Clears this bit. 1 Conversion result is stored. No effect. [bit 14] PCIF: Priority conversion interrupt request bit When conversion values are written up to the stage speci fied in the Priority Conversion FIFO Stage Count Setup Register (PFNS), this bit is set to 1. The read value of Read-Modify-Write access is 1 regardless of the bit value. Description Bit Read Write 0 Conversion result is not stored. Clears this bit. 1 Conversion result is stored. No effect. [bit 13] CMPIF: Conversion result comparison interrupt request bit When the condition set in the A/D Comparison Value Setup Register (CMPD) or A/D Comparison Control Register (CMPCR) is satisfied during the operation of the A/D conversion result comparison function, this bit is set to 1. The read value of Read-Modify -Write access is 1 regardless of the bit value. Description Bit Read Write 0 Specified condition is not satisfied. Clears this bit. 1 Specified condition is satisfied. No effect. [bit 12] Reserved: Reserved bit Write Has no effect on operation. Read The value is undefined. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 764 MB9Axxx/MB9Bxxx Series