Fujitsu Series 3 Manual
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2. Configuration of Multifunction Timer 2.3. I/O Pins of Multifunction Timer Unit Correspondence with LSI External I/O Pins Of all the I/O signals illustrated in the block diagrams, Ta b l e 2 - 1 shows a list of correspondence between I/O pins of M FT unit and LSI external I/O pins. In this series, some models have more than one MFT unit. Therefore, LSI pin names are composed of I/O pin names shown in the block diagrams plus MFT’s unit number (0, 1, 2). It should be noted that descriptions in this chapter are based on the pin names shown in the block diagrams. Table 2-1 Correspondence Table for I/O Pins of MFT Unit and LSI External I/O Pins Name of LSI Pin Name of MFT Unit Pin (Pin Name in Block Diagram) Function MFT-unit0 MFT-unit1 FRCK FRT external input clock FRCK0 FRCK1 DTTIX Motor emergency shutdown interrupt input DTTI0X DTTI1X RTO0 WFG-PWM output ch.0 RTO00 RTO10 RTO1 WFG-PWM output ch.1 RTO01 RTO11 RTO2 WFG-PWM output ch.2 RTO02 RTO12 RTO3 WFG-PWM output ch.3 RTO03 RTO13 RTO4 WFG-PWM output ch.4 RTO04 RTO14 RTO5 WFG-PWM output ch.5 RTO05 RTO15 IC0 ICU input ch.0 IC00 IC10 IC1 ICU input ch.1 IC01 IC11 IC2 ICU input ch.2 IC02 IC12 IC3 ICU input ch.3 IC03 IC13 ICU’s input pins can be switched with the following LS I internal signals, in addition to the external pin inputs, using the selector function of the I/O port block. SYNC signal when the LYN function of the multifunction serial block is used Internal CR oscillator/oscillation frequency trimming input signal For details, see the section regarding the I/O port block. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 505 MB9Axxx/MB9Bxxx Series
2. Configuration of Multifunction Timer Interrupt Signal Outputs Of all the I/O signals illustrated in the block diagrams, Ta b l e 2 - 2 shows a list of interrupt signals generated from the MFT u nit. Any model that contains more than one MFT unit has interrupt outputs equivalent to the number of mounted MFT units. Table 2-2 List of Interrupt Signals Generated from MFT Unit Generation Block Interrupt Type FRT ch.0 Zero value detection interrupt FRT ch.1 Zero value detection interrupt FRT ch.2 Zero value detection interrupt FRT ch.0 Peak value detection interrupt FRT ch.1 Peak value detection interrupt FRT ch.2 Peak value detection interrupt OCU ch.0 Match detection interrupt OCU ch.1 Match detection interrupt OCU ch.2 Match detection interrupt OCU ch.3 Match detection interrupt OCU ch.4 Match detection interrupt OCU ch.5 Match detection interrupt ICU ch.0 Input signal edge detection interrupt ICU ch.1 Input signal edge detection interrupt ICU ch.2 Input signal edge detection interrupt ICU ch.3 Input signal edge detection interrupt NZCL DTIF interrupt (emergency motor shutdown interrupt) WFG ch.10 WFG timer 10 interrupt WFG ch.32 WFG timer 32 interrupt WFG ch.54 WFG timer 54 interrupt FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 506 MB9Axxx/MB9Bxxx Series
2. Configuration of Multifunction Timer Other I/O Signals Of all the I/O signals illustrated in the block diagrams, the following section describes the other signals. PCLK This is an LSI internal peripheral clock signal used in the MFT unit. It uses the clock signal of the APB bus to be connected. FRT (when the LSI internal peripheral clock is selected) and the WFG timer operate based on the count clock divided from PCLK. FRT input and FRT output of external MFT A model containing more than one MFT unit can use FRT count output for the other MFT. This connection configuration allows OCU and ICU mounted separately on multiple MFT units to be interlocked by a single FRT. (A model containing 2 MFT units can output12 channels of PWM simultaneously. A model containing 3 MFT units can output 18 channels of PWM simultaneously. For details, see 5.1 Connection of Model Containing Multiple MFT’s . GATE signal / PPG signal GATE signal is PPG’s start signal that is output fr om MFT and input to PPG. PPG signal is output from PPG and input to MFT. PPG units to be connected for these signals vary depending on the mounted MFT unit. For details of their connection, see 5.1 Connection of Model Containing Multiple MFT’s . AD conversion start signal A total of 6 AD conversion start signals are output: scan start signals and priority start signals for each of the three units of ADC. In models containing more than one MFT unit, start signals undergo logic OR for each ADC unit and are used in each ADC unit. For details, see the chapter A/D Converter. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 507 MB9Axxx/MB9Bxxx Series
3. Operations of Multifunction Timer 3. Operations of Multifunction Timer This chapter provides examples of operations of the multifunction timer and explains its setting procedures. 3.1 Example of Operation of Multifunction Timer - 1 3.2 Example of Operation of Multifunction Timer - 2 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 508 MB9Axxx/MB9Bxxx Series
3. Operations of Multifunction Timer 3.1. Example of Operation of Multifunction Timer - 1 Example of Operation of Multifunction Timer - 1 explains the cases where each function block is operated in the following modes: FRT : Up-count mode, without interrupt OCU : Up-count mode (1-change), with interrupt WFG : RT-PPG mode, generation of GATE signal, superimposition of PPG signal ICU : Rising edge detection mode, with interrupt Time Chart Figure 3-1 Time Chart of Main Registers and I/O Signals of Each Block ch.0 count OCCP0 reg.RT0 output RT1 output 0x5FFF 0x5FFF 0x0000 0x1800 0x2800 0x3800 0x4800 0x5800 0x0800 TCCP0 reg. RTO0 output RTO1 output Ch.0 Interrupt CPU Operation timing12345 FRT WFG IC0 input ICCP0 reg.Ch.0 Interrupt ICU0x57FE0x58020x57FF 6 0x18000x38000x38000x38000x18000x18000x1800 7 GATE0 output OCU PPG0 input OCCP1 reg.0x48000x08000x08000x4800 Ch.1 Interrupt 0x08000x4800 456456 Figure 3-1 shows the time chart of main registers and I/O signals fo r each block. From top to bottom, the figure indicates CPU operation, FRT operation, OCU operation, WFG operation and ICU operation. The following section describes the operation of each functi on block and what is controlled from CPU at the timing 1 to 7. It also shows specific examples of CPU register settings at each of the timings. For details of register settings, see 4 Registers of Multifunction Timer. It should be noted that in addition to the abo ve, LSI I/ O port block, interrupt control block and PPG must be set separately. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 509 MB9Axxx/MB9Bxxx Series
3. Operations of Multifunction Timer Operation of FRT, OCU Timing 1 Set Up-count operation to FRT-ch.0 (TCSA0 register write). Set an operating cycle to FRT-ch.0 (TCCP0 register write). In this example, 0x5FFF is set. When the pre-scaler is set to 1/128 and PCLK to 40MHz, the count cycle of FRT is 78.6432ms. Connect and set FRT-ch.0 to OCU-ch.0/ch.1 (OCFS10 register write). Set OCU-ch.0/ch.1 to Up-count mode (1-change) operation. Also specify the initial output level of output signals (RT0, RT1) (OCSA10, OCSB10 and OCSC register write). Set the timing of changing the output signal (RT0 ) for OCU-ch.0 (OCCP0 register write). In this example, 0x1800 is set. The value is written to the buffer register, and then transferred to the OCCP0 register. Set the timing of changing the output signal (RT1 ) for OCU-ch.1 (OCCP1 register write). In this example, 0x4800 is set. The value is written to the buffer register, and then transferred to the OCCP1 register. Timing 2 Instruct FRT-ch.0 to start count operation (TCSA0 register write). In Up-count mode, FRT-ch.0 starts counting from 0x0000 and continues the Up-count operation until the TCCP value is reached (=0x5FFF), as shown in the figure. Then, it returns to 0x0000 and continues counting. Timing 3 Instruct OCU-ch.0/ch.1 to enable the operation (OCSA10 register write). Timing 4 When OCU-ch.0 detects that the value of the FRT counter has reached 0x1800 and matched the setting value of OCCP0, it changes the output signal (RT0) from the Low to High level. It also generates an interrupt to CPU. CPU determines that an interrupt has been generated from OCU-ch.0, because 1 is set to the match detection flag of OCU-ch.0 (OCSA10 register read). Update the timing of changing the output signal (RT0) for OCU-ch.0 to 0x3800 (OCCP0 register write). CPU clears the match detection flag and returns from the interrupt (OCSA10 register write). Timing 5 When OCU-ch.0 detects that the value of the FRT counter matches the value of OCCP0, it changes the output signal (RT0) from the High to Low level. It also generates an interrupt to CPU. CPU identifies the interrupt from OC U-ch.0 (OCSA10 register read). Update the OCCP0 register of OCU-ch.0 to 0x1800 (OCCP0 register write). CPU clears the match detection flag and returns from the interrupt (OCSA10 register write). After that, repeat Operations 4 and 5 so that PWM wa veform in the FRT cycle can be achieved for the RT0 output signal, as shown in the figure. Similarly, PWM output waveform can also be achieved for the RT1 by updating the value of the OCCP1 regist er every time an interrupt occurs. Operation of WFG Timing 1 Set RT-PPG mode operation to WF G-ch.10 (WFSA10 register write). Timing 4 When the RT0 signal from OCU-ch.0 is changed to the High level, WFG asserts the GATE signal (GATE0) and instructs PPG-ch.0 to start. When the GATE signal is asserted, PPG-ch.0 starts the output of the PPG signal (PPG0). WFG superimposes and outputs the PPG signal to RTO0 while the RT0 signal remains at the High level. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 510 MB9Axxx/MB9Bxxx Series
3. Operations of Multifunction Timer Timing 5 When the RT0 signal is changed to the Low level, WFG deasserts the GATE signal and gives a stop instruction. PPG-ch.0 changes the PPG signal to the Low level and stops the output. WFG changes the RTO0 signal to the Low level and stops the output. WFG performs the same operation to the RT1 signal from OCU-ch.1, and superimposes and outputs the PPG signal to RTO1. DC chopper control waveform, as shown in the figure, can be output to RTO0/RTO1 by using the WFG function. Operation of ICU Timing 1 Connect and set FRT-ch.0 to ICU-ch .0/ch.1 (ICFS10 register write). Set rising edge detection operation to ICU-ch.0 (ICSA10 register write). Timing 6 When a rising edge is detected at the input signal (IC0), ICU-ch.0 stores FRT’s count value to the ICCP0 register. It also generates an interrupt to CPU. CPU determines that an interrupt has been genera ted from ICU-ch.0, because 1 is set to the valid edge detection flag of ICU-ch .0 (ICSA10 register read). CPU captures the position of the rising edge of the signal (ICCP0 register read). CPU clears the valid edge detection flag and returns from the interrupt (ICSA10 register write). Completion of Processing Timing 7 The processing at Timing 7 indicates the procedure for completing the output of the PWM signal. Disable the operation of OCU-ch.0 and ch.1 (OCSA10 register write). Set the level of the output signals (RT0, RT1) fo r OCU-ch.0 and ch.1 (OCSB10 register write). Disable the operation of ICU-ch .0 (ICSA10 register write). When the output of OCU stops, WFG does not perform its operation. Instruct FRT-ch.0 to stop the count operation (TCSA0 register write). Set 0x0000 to FRT’s count value (TCDT0 register write). Processing of Other Channels The above example explained the operation with 2 channels of OCU, one channel of WFG and one channel of ICU. If OCU-6ch, WFG-3ch, and ICU-3ch are connected to the same FRT to perform interlocking control, three-phase motor control can be achieved. Details of Register Settings Register settings in Example of Operation of Multifunction Timer - 1 are detailed below. The meanings of the symbols in the table are as follows: Operation HW Half-word write access BW Byte write access HR Half-word read access BR Byte read access Value NM Indicates either writing the same va lue as the register value that has already been set or reading from the register to write the original value (No Modify). 1(RMW) Indicates writing 1, if register cl ear is not intended. In the case of update by RMW access (see 5.2 Treatment of Event Detect Register and Int errupt ), it in d icates that the read value can be written back. Other Ind i cates setting bits of other channels and no relation to this explanatory example. DC Indicates no relation to the read value (Dont Care). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 511 MB9Axxx/MB9Bxxx Series
3. Operations of Multifunction Timer Table 3-1 Example of Operation 1 – Register Settings 1 Setting Timing Name of Target Block Name of Register Operation Bit Field Value Description of Setting CLK[3:0]0111 Clock division pre-scaler setting: 1/128 SCLR 0 Soft clear: Do nothing MODE 0 Count mode setting: Up-count mode STOP 1 FRT count operation: Stop counting BFE 1 TCCP buffer function: Enable ICRE 0 Peak value detection interrupt: Disable ICLR 0 Peak value detection: Clear Reserved 000 - IRQZE 0 Zero value detection interrupt: Disable IRQZF 0 Zero value detection: Clear TCSA0 HW ECKE 0 Selection of clock used: Internal clock FRT TCCP0 HW TCCP 0x5FFFSet FRT cycle FSO0[3:0] 0000 FRT connected to ch.0: FRT ch.0 OCFS10 BW FSO1[3:0]0000 FRT connected to ch.1: FRT ch.0 CST0 0 ch.0 operation state: Operation disable CST1 0 ch.1 operation state: Operation disable BDIS0 1 ch.0 OCCP buffer function: Disable BDIS1 1 ch.1 OCCP buffer function: Disable IOE0 1 ch.0 interrupt: Enable IOE1 1 ch.1 interrupt: Enable IOP0 0 ch.0 match detection: Clear OCSA10 BW IOP1 0 ch.1 match detection: Clear OTD0 0 RT0 output level initial setting: Low OTD1 0 RT1 output level initial setting: Low Reserved 00 - CMOD 0 ch.0/ch.1 operation mode: Up-count (1-change) BTS0 0 ch.0 buffer transfer: don’t care BTS1 0 ch.1 buffer transfer: don’t care OCSB10 BW Reserved 0 - MOD0 0 ch.0 operation mode: Up-count (1-change) MOD1 0 ch.1 operation mode: Up-count (1-change) MOD2 Other ch.2 operation mode: MOD3 Other ch.3 operation mode: MOD4 Other ch.4 operation mode: MOD5 Other ch.5 operation mode: OCSC BW Reserved 00 - OCCP0 HW OCCP 0x1800Specify ch.0 change timing 1 OCU OCCP1 HW OCCP 0x4800Specify ch.1 change timing FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 512 MB9Axxx/MB9Bxxx Series
3. Operations of Multifunction Timer Table 3-2 Example of Operation 1 – Register Settings 2 Setting Timing Name of Target Block Name of Register Operation Bit Field Value Description of Setting DCK[2:0] 000 Clock division pre-scaler setting: 1/1 (don’t care) TMD[2:0] 001 Operation mode : Select RT-PPG mode GTEN[1:0] 11 Gate signal genera tion: RT0, RT1 signal logic OR PSEL[1:0]00 Connecting PPG : PPG0 PGEN[1:0] 11 PPG reflection: Logic AND of PPG signal to RTO0/RTO1 signals DMOD 0 Output polarity: don’t care WFG WFSA10 HW Reserved 000 - FSI0[3:0] 0000 FRT connected to ch.0: FRT ch.0 ICFS10 BW FSI1[3:0] Other FRT connected to ch.1: EG0[1:0] 01 ch.0 operation state: Operation enabled, rising edge EG1[1:0] Other ch.1 operation state: ICE0 1 ch.0 interrupt: Enable ICE1 Other ch.1 interrupt: ICP0 0 ch.0 edge detection: Clear 1 ICU ICSA10 BW ICP1 Other ch.1 edge detection: CLK[3:0]NM Clock division pre-scaler setting: SCLR NM Soft clear: MODE NM Count mode setting: STOP 0 FRT count operation: Start counting BFE NM TCCP buffer function: ICRE NM Peak value detection interrupt: ICLR 1(RMW)Peak value detection: Do nothing Reserved NM - IRQZE NM Zero value detection interrupt: IRQZF 1(RMW)Zero value detection: Do nothing 2 FRT TCSA0 HW ECKE NM Selection of clock used: Internal clock CST0 1 ch.0 operation state: Operation enabled CST1 1 ch.1 operation state: Operation enabled BDIS0 NM ch.0 OCCP buffer function: BDIS1 NM ch.1 OCCP buffer function: IOE0 NM ch.0 interrupt: IOE1 NM ch.1 interrupt: IOP0 1 ch.0 match detection: Do nothing 3 OCU OCSA10BW IOP1 1 ch.1 match detection: Do nothing FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 513 MB9Axxx/MB9Bxxx Series
3. Operations of Multifunction Timer Table 3-3 Example of Operation 1 – Register Settings 3 Setting Timing Name of Target Block Name of Register Operation Bit Field Value Description of Setting CST0 DC ch.0 operation state: CST1 DC ch.1 operation state: BDIS0 DC ch.0 OCCP buffer function: BDIS1 DC ch.1 OCCP buffer function: IOE0 DC ch.0 interrupt: IOE1 DC ch.1 interrupt: IOP0 1 ch.0 match dete ction: Match detected OCSA10BR IOP1 0 ch.1 match detec tion: Match not detected OCCP0 HW OCCP0 0x3800Specify ch.0 change timing CST0 NM ch.0 operation state: CST1 NM ch.1 operation state: BDIS0 NM ch.0 OCCP buffer function: BDIS1 NM ch.1 OCCP buffer function: IOE0 NM ch.0 interrupt: IOE1 NM ch.1 interrupt: IOP0 0 ch.0 match detection: Flag cleared 4 OCU OCSA10BW IOP1 1(RMW)ch.1 match detection: Do nothing CST0 DC ch.0 operation state: CST1 DC ch.1 operation state: BDIS0 DC ch.0 OCCP buffer function: BDIS1 DC ch.1 OCCP buffer function: IOE0 DC ch.0 interrupt: IOE1 DC ch.1 interrupt: IOP0 1 ch.0 match dete ction: Match detected OCSA10BR IOP1 0 ch.1 match detec tion: Match not detected OCCP0 HW OCCP0 0x1800Specify ch.0 change timing CST0 NM ch.0 operation state: CST1 NM ch.1 operation state: BDIS0 NM ch.0 OCCP buffer function: BDIS1 NM ch.1 OCCP buffer function: IOE0 NM ch.0 interrupt: IOE1 NM ch.1 interrupt: IOP0 0 ch.0 match detection: Flag cleared 5 OCU OCSA10BW IOP1 1(RMW)ch.1 match detection: Do nothing FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 514 MB9Axxx/MB9Bxxx Series