Samsung Exynos 5 User Manual
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![Page 871
Samsung Confidential
Exynos 5250_UM 15 Display Controller
15-129
15.5.5.13 SIFCCON1
Base Address: 0x1442_0000
Address = Base Address + 0x01E4, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
RSVD [31:24] –=Reserved (should be 0)=0=
SYS_WDATA=[23:0]=RW=Controls the LCD i80 System Interface Write Data.=0=
=
15.5.5.14 SIFCCON2
Base Address: 0x1442_0000
Address = Base Address + 0x01E8, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
RSVD [31:24]...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-870.png "Page 871
Samsung Confidential
Exynos 5250_UM 15 Display Controller
15-129
15.5.5.13 SIFCCON1
Base Address: 0x1442_0000
Address = Base Address + 0x01E4, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
RSVD [31:24] –=Reserved (should be 0)=0=
SYS_WDATA=[23:0]=RW=Controls the LCD i80 System Interface Write Data.=0=
=
15.5.5.14 SIFCCON2
Base Address: 0x1442_0000
Address = Base Address + 0x01E8, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
RSVD [31:24]...")
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0 = Non-invert
1 = Invert
RSVD [15:9] –=Reserved=0=
CRCMXSEL=[8:4]=RW=Specifies the CRC Data Mux. Selection.=
Select n th=(0 to 23) Video data (VD) for CRC.=0=
RSVD=[3]=–=Reserved=0=
CRCCLKEN=[2]=RW=
CRCCLK Enable control=
0 = Disable=
1 = Enable=
0=
CRCSTART_F [1] RW
CRC start control
0 = Disable CRC logic at next frame
1 = Enable CRC logic at next frame
0
CRCEN [0] RW
Enables the CRC check
0 = Disables CRC check
1 = Enables CRC check
0
15.5.5.17 I80IFCONn (n = 0 to 11)
Base...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-871.png "Page 872
0 = Non-invert
1 = Invert
RSVD [15:9] –=Reserved=0=
CRCMXSEL=[8:4]=RW=Specifies the CRC Data Mux. Selection.=
Select n th=(0 to 23) Video data (VD) for CRC.=0=
RSVD=[3]=–=Reserved=0=
CRCCLKEN=[2]=RW=
CRCCLK Enable control=
0 = Disable=
1 = Enable=
0=
CRCSTART_F [1] RW
CRC start control
0 = Disable CRC logic at next frame
1 = Enable CRC logic at next frame
0
CRCEN [0] RW
Enables the CRC check
0 = Disables CRC check
1 = Enables CRC check
0
15.5.5.17 I80IFCONn (n = 0 to 11)
Base...")
![Page 876
Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-4
16.5 ADC Input Clock Diagram
Figure 16-2 Input Clock Diagram for ADC PCLK1/NADCCLK
ADCCON[13:6]](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-875.png "Page 876
Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-4
16.5 ADC Input Clock Diagram
Figure 16-2 Input Clock Diagram for ADC PCLK1/NADCCLK
ADCCON[13:6]")
![Page 877
Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-5
16.6 I/O Descriptions
Signal I/O Description Pad Type
AIN[7] Input ADC Channel[7] Analog input Xadc0AIN_7 Analog
AIN[6] Input ADC Channel[6] Analog input Xadc0AIN_6 Analog
AIN[5] Input ADC Channel[5] Analog input Xadc0AIN_5 Analog
AIN[4] Input ADC Channel[4] Analog input Xadc0AIN_4 Analog
AIN[3] Input ADC Channel[3] Analog input Xadc0AIN_3 Analog
AIN[2] Input ADC Channel[2] Analog input Xadc0AIN_2 Analog
AIN[1]...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-876.png "Page 877
Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-5
16.6 I/O Descriptions
Signal I/O Description Pad Type
AIN[7] Input ADC Channel[7] Analog input Xadc0AIN_7 Analog
AIN[6] Input ADC Channel[6] Analog input Xadc0AIN_6 Analog
AIN[5] Input ADC Channel[5] Analog input Xadc0AIN_5 Analog
AIN[4] Input ADC Channel[4] Analog input Xadc0AIN_4 Analog
AIN[3] Input ADC Channel[3] Analog input Xadc0AIN_3 Analog
AIN[2] Input ADC Channel[2] Analog input Xadc0AIN_2 Analog
AIN[1]...")
![Page 879
Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-7
16.7.1.1 ADCCON
Base Address: 0x12D1_0000
Address = Base Address + 0x0000, Reset Value = 0x0000_3FC4
Name Bit Type Description Reset Value
RES [16] RW
ADC output resolution selection
0 = 10-bit A/D conversion
1 = 12-bit A/D conversion
0
ECFLG [15] RW
End of conversion flag(Read only)
0 = A/D conversion in process
1 = End of A/D conversion
0
PRSCEN [14] RW
A/D converter prescaler enable
0 = Disable
1 =...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-878.png "Page 879
Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-7
16.7.1.1 ADCCON
Base Address: 0x12D1_0000
Address = Base Address + 0x0000, Reset Value = 0x0000_3FC4
Name Bit Type Description Reset Value
RES [16] RW
ADC output resolution selection
0 = 10-bit A/D conversion
1 = 12-bit A/D conversion
0
ECFLG [15] RW
End of conversion flag(Read only)
0 = A/D conversion in process
1 = End of A/D conversion
0
PRSCEN [14] RW
A/D converter prescaler enable
0 = Disable
1 =...")
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Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-8
16.7.1.2 ADCDLY
Base Address: 0x12D1_0000
Address = Base Address + 0x0008, Reset Value = 0x0000_00FF
Name Bit Type Description Reset Value
DELAY [15:0] RW
ADC conversion is delayed by counting this value.
Counting clock is PCLK.
ADC conversion delay value.
NOTE: Do not use zero value(0x0000)
00ff
16.7.1.3 ADCDATX
Base Address: 0x12D1_0000
Address = Base Address + 0x000C, Reset Value = Undefined...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-879.png "Page 880
Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-8
16.7.1.2 ADCDLY
Base Address: 0x12D1_0000
Address = Base Address + 0x0008, Reset Value = 0x0000_00FF
Name Bit Type Description Reset Value
DELAY [15:0] RW
ADC conversion is delayed by counting this value.
Counting clock is PCLK.
ADC conversion delay value.
NOTE: Do not use zero value(0x0000)
00ff
16.7.1.3 ADCDATX
Base Address: 0x12D1_0000
Address = Base Address + 0x000C, Reset Value = Undefined...")
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Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-9
16.7.1.5 ADCMUX
Base Address: 0x12D1_0000
Address = Base Address + 0x001C, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
SEL_MUX [3:0] RW
Analog input channel select
0000 = AIN 0
0001 = AIN 1
0010 = AIN 2
0011 = AIN 3
0100 = AIN 4
0101 = AIN 5
0110 = AIN 6
0111 = AIN 7
0](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-880.png "Page 881
Samsung Confidential
Exynos 5250_UM 16 Analog to Digital Converter (ADC)
16-9
16.7.1.5 ADCMUX
Base Address: 0x12D1_0000
Address = Base Address + 0x001C, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
SEL_MUX [3:0] RW
Analog input channel select
0000 = AIN 0
0001 = AIN 1
0010 = AIN 2
0011 = AIN 3
0100 = AIN 4
0101 = AIN 5
0110 = AIN 6
0111 = AIN 7
0")
Samsung Confidential Exynos 5250_UM 16 Analog to Digital Converter (ADC) 16-9 16.7.1.5 ADCMUX Base Address: 0x12D1_0000 Address = Base Address + 0x001C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value SEL_MUX [3:0] RW Analog input channel select 0000 = AIN 0 0001 = AIN 1 0010 = AIN 2 0011 = AIN 3 0100 = AIN 4 0101 = AIN 5 0110 = AIN 6 0111 = AIN 7 0