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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-99  
15.5.2.50 WPALCON_L 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x01A0, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:10] –=oeserved=0=
PALUPDATEEN=[9]=RW=0 = Normal Mode=
1 = Enables=palette=update=0=
W4PAL_i=x8]=RW=W4PAL[0]=0=
W3PAL_i=x7]=RW=W3PAL[0]=0=
W2PAL_i=xS]=RW=W2PAL[0]=0=
W1PAL_i=x=5: 3]=RW=W1PAL[2:0]=0=
W0PAL_i=x=2: 0]=RW=W0PAL[2:0]=0=
NOTE: WPALCON = {WPALCON_H, WPALCON_L} 
 
WPALCON Description Reset Value 
PALUPDATEEN 0 = Normal Mode 
1 = Enable (Palette Update) 0 
W4PAL[3:0] 
Specifies the Window 4 Palette data format size. 
000 = 16-bit (5:6:5)  
001 = 16-bit (A:5:5:5) 
010 = 18-bit (6:6:6) 
011 = 18-bit (A:6:6:5) 
100 = 19-bit (A:6:6:6) 
101 = 24-bit (8:8:8) 
110 = 25-bit (A:8:8:8)  
111 = 32-bit (8:8:8:8) (A: 8-bit) 
0 
W3PAL[2:0] 
Specifies the Window 3 Pallet data format size. 
000 = 16-bit (5:6:5) 
001 = 16-bit (A:5:5:5) 
010 = 18-bit (6:6:6) 
011 = 18-bit (A:6:6:5) 
100 = 19-bit (A:6:6:6) 
101 = 24-bit (8:8:8) 
110 = 25-bit (A:8:8:8)  
111 = 32-bit (8:8:8:8) (A: 8-bit) 
0 
W2PAL[2:0] 
Specifies the Window 2 Pallet data format size. 
000 = 16-bit (5:6:5)  
001 = 16-bit (A:5:5:5) 
010 = 18-bit (6:6:6) 
011 = 18-bit (A:6:6:5) 
100 = 19-bit (A:6:6:6) 
101 = 24-bit (8:8:8) 
110 = 25-bit (A:8:8:8)  
111 = 32-bit (8:8:8:8) (A: 8-bit) 
0
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Exynos 5250_UM 15 Display Controller 
 15-100  
WPALCON Description Reset Value 
W1PAL[2:0] 
Specifies the Window 1 Pallet data format size. 
000 = 25-bit (A:8:8:8) 
001 = 24-bit (8:8:8) 
010 = 19-bit (A:6:6:6) 
011 = 18-bit (A:6:6:5) 
100 = 18-bit (6:6:6) 
101 = 16-bit (A:5:5:5) 
110 = 16-bit (5:6:5) 
111 = 32-bit (8:8:8:8) (A: 8-bit) 
0 
W0PAL[2:0] 
Specifies the Window 0 pallet data format size. 
000 = 25-bit (A:8:8:8) 
001 = 24-bit (8:8:8) 
010 = 19-bit (A:6:6:6) 
011 = 18-bit (A:6:6:5) 
100 = 18-bit (6:6:6) 
101 = 16-bit (A:5:5:5) 
110 = 16-bit (5:6:5)  
111 = 32-bit (8:8:8:8) (A: 8-bit) 
0 
NOTE: The bit map for W0/W1 and W2/W3/W4 is different.
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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-101  
15.5.2.51 LAYERSYNC_CON 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x01C0, Reset Value = 0xFFFF_FF00 
Name Bit Type Description Reset Value 
FIRE_PULSE_W ID
TH [31:8] RW Reserved 0xFF_FFFF 
RSVD [7] –=Reserved=0=
SYNC_UPDATb=[6]=RS=
All enabled layersync channel updated=
0 = Do NOT update shadow register next frame=
1 = Update shadow register next frame=
0=
ALL_SYNC_ON=[5]=RW=
Enable all channel layersync=
0 = Disable all channel layersync=
1 = Enable all channel layersync=
0=
W4_SYNC_ON=[4]=RW=
Enable channel 4’s layersync to display 3D image.=
0 = Disable channel 4 layersync=
1 = Enable channel 4 layersync=
0=
W3_SYNC_ON=[3]=RW=
Enable channel 3’s layersync to display 3D image.=
0 = Disable channel 3 layersync=
1 = Enable channel 3 layersync=
0=
W2_SYNC_ON=[2]=RW=
Enable channel 2’s layersync to display 3D image.=
0 = Disable channel 2 layersync=
1 = Enable channel 2=layersync=
0=
W1_SYNC_ON=[1]=RW=
Enable channel 1’s layersync to display 3D image.=
0 = Disable channel 1 layersync=
1 = Enable channel 1 layersync=
0=
W0_SYNC_ON=[0]=RW=
Enable channel 0’s layersync to display 3D image.=
0 = Disable channel 0 layersync=
1 = Enable channel 0 layersync=
0=
=
=
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Exynos 5250_UM 15 Display Controller 
 15-102  
15.5.2.52 VIDW0ALPHA0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x021C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
ALPHA0_R_F=[23:16]=RW=Specifies the Red Alpha value=(when=AEN == 0).=0=
ALPHA0_G_F=[15:8]=RW=Specifies the Green Alpha value=(when=AEN == 0).=0=
ALPHA0_B_F=[7:0]=RW=Specifies the Blue Alpha value=(when=AEN == 0).=0=
=
=
15.5.2.53 VIDW0ALPHA1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0220, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
ALPHA1_R_F=[23:16]=RW=Specifies the Red Alpha value=(when=AEN == 1).=0=
ALPHA1_G_F=[15:8]=RW=Specifies the Green Alpha value=(when=AEN == 1).=0=
ALPHA1_B_F=[7:0]=RW=Specifies the Blue Alpha value=(when=AEN == 1).=0=
=
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Exynos 5250_UM 15 Display Controller 
 15-103  
15.5.2.54 VIDW1ALPHA0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0224, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
RSVD=[23:20]=–=oeserved=0=
ALPHA0_R_L_F=[19:16]=RW=Specifies the Red Alpha iower value=(when=AEN ===
0).=0=
oSVa=[15:12]=–=Reserved=0=
ALPHA0_G_L_F=[11: 8]=RW=Specifies the Green Alpha iower value=(when=AEN ===
0).=0=
oSVa=[7: 4]=–=Reserved=0=
ALPHA0_B_L_F=[3: 0]=RW=Specifies the Blue Alpha=iower value=(when=AEN ===
0).=0=
NOTE: ALPHA0_R (G, B) [7:4] = ALPHA0_R (G, B)_H[3:0] at VIDOSD1C 
ALPHA0_R (G, B) [3:0] = ALPHA0_R (G, B)_L[3:0] at VIDW1ALPHA0  
 
15.5.2.55 VIDW1ALPHA1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0228, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
RSVD=[23:20]=–=oeserved=0=
ALPHA1_R_L_F=[19:16]=RW=Specifies the Red Alpha iower value=(when=AEN == 1).=0=
RSVD=[15:12]=RW=oeserved=0=
ALPHA1_G_L_F=[11: 8]=RW=Specifies the Green Alpha iower value=(when=AEN ===
1).=0=
RSVD=[7: 4]=–=oeserved=0=
ALPHA1_B_L_F=[3: 0]=RW=Specifies the Blue Alpha=iower value=(when=AEN == 1).=0=
NOTE: ALPHA1_R (G, B) [7:4] = ALPHA1_R (G, B)_H[3:0] at VIDOSD1C 
ALPHA1_R (G, B) [3:0] = ALPHA1_R (G, B)_L[3:0] at VIDW1ALPHA1
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Exynos 5250_UM 15 Display Controller 
 15-104  
15.5.2.56 VIDW2ALPHA0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x022C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
oSVa=[23:20]=–=oeserved=0=
ALPHA0_R_L_F=[19:16]=RW=Specifies the Red Alpha iower value=(when=AEN == 0).=0=
oSVa=[15:12]=–=oeserved=0=
ALPHA0_G_L_F=[11: 8]=RW=Specifies the Green Alpha iower value=(when=AEN ===
0).=0=
oSVa=[7: 4]=–=oeserved=0=
ALPHA0_B_L_F=[3: 0]=RW=Specifies the Blue Alpha=iower value=(when=AEN == 0).=0=
NOTE: ALPHA0_R (G, B) [7:4] = ALPHA0_R (G, B)_H[3:0] at VIDOSD2C 
ALPHA0_R (G, B) [3:0] = ALPHA0_R (G, B)_L[3:0] at VIDW2ALPHA0  
 
15.5.2.57 VIDW2ALPHA1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0230, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
RSVD=[23:20]=–=oeserved=0=
ALPHA1_R_L_F=[19:16]=RW=Specifies the Red Alpha iower value=(when=AEN == 1).=0=
RSVD=[15:12]=–=oeserved=0=
ALPHA1_G_L_F=[11: 8]=RW=Specifies the Green Alpha iower value=(when=AEN ===
1).=0=
RSVD=[7: 4]=–=oeserved=0=
ALPHA1_B_L_F=[3: 0]=RW=Specifies the Blue Alpha=iower value=(when=AEN == 1).=0=
NOTE: ALPHA1_R (G, B) [7:4] = ALPHA1_R (G, B)_H[3:0] at VIDOSD2C 
ALPHA1_R (G, B) [3:0] = ALPHA1_R (G, B)_L[3:0] at VIDW2ALPHA1
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Exynos 5250_UM 15 Display Controller 
 15-105  
15.5.2.58 VIDW3ALPHA0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0234, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
RSVD=[23:20]=–=oeserved=0=
ALPHA0_R_L_F=[19:16]=RW=Specifies the Red Alpha iower value=(when=AEN ===
0).=0=
RSVD=[15:12]=–=oeserved=0=
ALPHA0_G_L_F=[11: 8]=RW=Specifies the Green Alpha iower value=(when=AEN ===
0).=0=
RSVD=[7: 4]=–=oeserved=0=
ALPHA0_B_L_F=[3: 0]=RW=Specifies the Blue Alpha=iower value=(when=AEN ===
0).=0=
NOTE: ALPHA0_R (G, B) [7:4] = ALPHA0_R (G, B)_H[3:0] at VIDOSD3C 
ALPHA0_R (G, B) [3:0] = ALPHA0_R (G, B)_L[3:0 ] at VIDW3ALPHA0  
 
15.5.2.59 VIDW3ALPHA1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0238, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
RSVD=[23:16]=–=Reserved=0=
ALPHA1_R_L_F=[19:16]=RW=Specifies the Red Alpha Lower value (when AEN == 1).=0=
RSVD=[15:12]=–=Reserved=0=
ALPHA1_G_L_F=[11: 8]=RW=Specifies the Green Alpha Lower value (when AEN ===
1).=0=
RSVD=[7: 4]=–=Reserved=0=
ALPHA1_B_L_F=[3: 0]=RS=Specifies the Blue Alpha=Lower value (when AEN == 1).=0=
NOTE: ALPHA1_R (G, B) [7:4] = ALPHA1_R (G, B)_H[3:0] at VIDOSD3C 
ALPHA1_R (G, B) [3:0] = ALPHA1_R (G, B)_L[3:0] at VIDW3ALPHA1
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Exynos 5250_UM 15 Display Controller 
 15-106  
15.5.2.60 VIDW4ALPHA0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x023C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
RSVD=[23:20]=–=Reserved=0=
ALPHA0_R_L_F=[19:16]=RW=Specifies the Red Alpha iower value=(when=AEN == 0).=0=
RSVD=[15:12]=–=Reserved=0=
ALPHA0_G_L_F=[11: 8]=RW=Specifies the Green Alpha iower value=(when=AEN ===
0).=0=
RSVD=[7: 4]=–=Reserved=0=
ALPHA0_B_L_F=[3: 0]=RW=Specifies the Blue Alpha=iower value=(when=AEN == 0).=0=
NOTE: ALPHA0_R (G, B) [7:4] = ALPHA0_R (G, B)_H[3:0] at VIDOSD4C 
ALPHA0_R (G, B) [3:0] = ALPHA0_R (G, B)_L[3:0] at VIDW4ALPHA0  
 
15.5.2.61 VIDW4ALPHA1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0240, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
RSVD=[23:20]=–=Reserved=0=
ALPHA1_R_L_F=[19:16]=RW=Specifies the Red Alpha iower value=(when=AEN == 1).=0=
RSVD=[15:12]=–=Reserved=0=
ALPHA1_G_L_F=[11: 8]=RW=Specifies the Green Alpha iower value=(when=AEN ===
1).=0=
RSVD=[7: 4]=–=Reserved=0=
ALPHA1_B_L_F=[3: 0]=RW=Specifies the Blue Alpha=iower value=(when=AEN == 1).=0=
NOTE: ALPHA1_R (G, B) [7:4] = ALPHA1_R (G, B)_H[3:0] at VIDOSD4C 
ALPHA1_R (G, B) [3:0] = ALPHA1_R (G, B)_L[3:0] at VIDW4ALPHA1
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Exynos 5250_UM 15 Display Controller 
 15-107  
15.5.2.62 BLENDEQ1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0244, Reset Value = 0x0000_00C2 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x000=
Q_FUNC_F=[21:18]=RW=
Specifies the constant that is used in alphaB=(alpha=
value of background(1)) 
0000 = 0 (zero) 
0001 = 1 (maximum) 
0010 = alphaA(2) (alpha value of foreground(1)) 
0011 = 1 –=alphaA=
0100 = alphaB =
0101 = 1=–=alphaB=
0110 = ALPHA0=
0111 = Reserved=
100x = Reserved=
1010 = A (foreground color data)=
1011 = 1=–=A=
1100 = B (background color data)=
1101 = 1=–=B=
111x = Reserved=
0x0=
RSVD=[17:16]=–=oeserved=00=
P_FUNC_F=[15:12]=RW=
Specifies the constant that is used in alpha.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information).=
0x0=
RSVD=[11:10]=–=oeserved=00=
B_FUNC_F=[9:6]=RW=
Specifies the constant that is used in B.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information).=
0x3=
RSVD=[5:4]=–=oeserved=00=
A_FUNC_F=[3:0]=RW=
Specifies the constant that is used in A.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information).=
0x2=
NOTE: Refer to Figure 15-5, Blending equation, for more information. 
1. Background = Window 0, foreground = Window 1 (in blend equation 1) 
2. BPPMODE_F, BLD_PIX, ALPHA_SEL at WINCONx, and WxPAL at WPALCON decides the alphaA and alphaB.
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Exynos 5250_UM 15 Display Controller 
 15-108  
15.5.2.63 BLENDEQ2 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0248, Reset Value = 0x0000_00C2 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x000=
Q_FUNC_F=[21:18]=RW=
Specifies the constant that is used in alphaB=(alpha=
value of background (1)). 
0000 = 0 (zero) 
0001 = 1 (maximum) 
0010 = alphaA (2) (alpha value of foreground (1)) 
0011 = 1 –=alphaA=
0100 = alphaB =
0101 = 1=–=alphaB=
0110 = ALPHA0=
0111 = Reserved=
100x = Reserved=
1010 = A (foreground color data)=
1011 = 1=–=A=
1100 = B (background color data)=
1101 = 1=–=B=
111x = Reserved=
0x0=
oSVa=[17:16]=–=oeserved=00=
P_FUNC_F=[15:12]=RW=
Specifies the constant that is used in alpha.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information)=
0x0=
oSVa=[11:10]=–=oeserved=00=
B_FUNC_F=[9:6]=RW=
Specifies the constant that is used in B.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information)=
0x3=
oSVa=[5:4]=–=oeserved=00=
A_FUNC_F=[3:0]=RW=
Specifies the constant used in A.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information)=
0x2=
NOTE: Refer to Figure 15-5, Blending equation for more information. 
1. Background = Window 01, foreground = Window 2 (in blend equation 2) 
2. BPPMODE_F, BLD_PIX, ALPHA_SEL at WINCONx, and WxPAL at WPALCON decides alphaA and alphaB.
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