Samsung Exynos 5 User Manual
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Samsung Confidential Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 8-9 Base Address: 0x121A_0000 (PDMA0) Base Address: 0x121B_0000 (PDMA1) Register Offset Description Reset Value PDMA0/PDMA1 DSR 0x0000 Specifies the DMA status register. 0x0000_0200 DPC 0x0004 Specifies the DMA program counter register. 0x0 RSVD 0x0008 to 0x001C Reserved Undefined INTEN 0x0020 Specifies the interrupt enable register. 0x0 INT_EVENT _RIS 0x0024 Specifies the event status register. 0x0 INTMIS 0x0028 Specifies the interrupt status register 0x0 INTCLR 0x002C Specifies the interrupt clear register. 0x0 FSRD 0x0030 Specifies the fault status DMA manager register. 0x0 FSRC 0x0034 Specifies the fault status DMA channel register. 0x0 FTRD 0x0038 Specifies the fault type DMA manager register. 0x0 RSVD 0x003C Reserved Undefined FTR0 0x0040 Specifies the fault type for DMA channel 0. 0x0 FTR1 0x0044 Specifies the fault type for DMA channel 1. 0x0 FTR2 0x0048 Specifies the fault type for DMA channel 2. 0x0 FTR3 0x004C Specifies the fault type for DMA channel 3. 0x0 FTR4 0x0050 Specifies the fault type for DMA channel 4. 0x0 FTR5 0x0054 Specifies the fault type for DMA channel 5. 0x0 FTR6 0x0058 Specifies the fault type for DMA channel 6. 0x0 FTR7 0x005C Specifies the fault type for DMA channel 7. 0x0 RSVD 0x0060 to 0x00FC Reserved Undefined CSR0 0x0100 Specifies the channel status for DMA channel 0. 0x0 CSR1 0x0108 Specifies the channel status for DMA channel 1. 0x0 CSR2 0x0110 Specifies the channel status for DMA channel 2. 0x0 CSR3 0x0118 Specifies the channel status for DMA channel 3. 0x0 CSR4 0x0120 Specifies the channel status for DMA channel 4. 0x0 CSR5 0x0128 Specifies the channel status for DMA channel 5. 0x0 CSR6 0x0130 Specifies the channel status for DMA channel 6. 0x0 CSR7 0x0138 Specifies the channel status for DMA channel 7. 0x0 CPC0 0x0104 Specifies the channel PC for DMA channel 0. 0x0 CPC1 0x010C Specifies the channel PC for DMA channel 1. 0x0 CPC2 0x0114 Specifies the channel PC for DMA channel 2. 0x0
Samsung Confidential Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 8-10 Register Offset Description Reset Value CPC3 0x011C Specifies the channel PC for DMA channel 3. 0x0 CPC4 0x0124 Specifies the channel PC for DMA channel 4. 0x0 CPC5 0x012C Specifies the channel PC for DMA channel 5. 0x0 CPC6 0x0134 Specifies the channel PC for DMA channel 6. 0x0 CPC7 0x013C Specifies the channel PC for DMA channel 7. 0x0 RSVD 0x0140 to 0x03FC Reserved Undefined SAR_0 0x0400 Specifies the source address for DMA channel 0. 0x0 SAR_1 0x0420 Specifies the source address for DMA channel 1. 0x0 SAR_2 0x0440 Specifies the source address for DMA channel 2. 0x0 SAR_3 0x0460 Specifies the source address for DMA channel 3. 0x0 SAR_4 0x0480 Specifies the source address For DMA channel 4. 0x0 SAR_5 0x04A0 Specifies the source address for DMA channel 5. 0x0 SAR_6 0x04C0 Specifies the Source address for DMA channel 6. 0x0 SAR_7 0x04E0 Specifies the source address for DMA channel 7. 0x0 DAR_0 0x0404 Specifies the destination address for DMA channel 0. 0x0 DAR_1 0x0424 Specifies the destination address for DMA channel 1. 0x0 DAR_2 0x0444 Specifies the destination address for DMA channel 2. 0x0 DAR_3 0x0464 Specifies the destination address for DMA channel 3. 0x0 DAR_4 0x0484 Specifies the destination address for DMA channel 4. 0x0 DAR_5 0x04A4 Specifies the destination address for DMA channel 5. 0x0 DAR_6 0x04C4 Specifies the destination address for DMA channel 6. 0x0 DAR_7 0x04E4 Specifies the destination address for DMA channel 7. 0x0 CCR_0 0x0408 Specifies the channel control for DMA channel 0. 0x0 CCR_1 0x0428 Specifies the channel control for DMA channel 1. 0x0 CCR_2 0x0448 Specifies the channel control for DMA channel 2. 0x0 CCR_3 0x0468 Specifies the channel control for DMA channel 3. 0x0 CCR_4 0x0488 Specifies the channel control for DMA channel 4. 0x0 CCR_5 0x04A8 Specifies the channel control for DMA channel 5. 0x0 CCR_6 0x04C8 Specifies the channel control for DMA channel 6. 0x0 CCR_7 0x04E8 Specifies the channel control for DMA channel 7. 0x0 LC0_0 0x040C Specifies the loop counter 0 for DMA channel 0. 0x0 LC0_1 0x042C Specifies the loop counter 0 for DMA channel 1. 0x0 LC0_2 0x044C Specifies the loop counter 0 for DMA channel 2. 0x0 LC0_3 0x046C Specifies the loop counter 0 for DMA channel 3. 0x0 LC0_4 0x048C Specifies the loop counter 0 for DMA channel 4. 0x0 LC0_5 0x04AC Specifies the loop counter 0 for DMA channel 5. 0x0
Samsung Confidential Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 8-11 Register Offset Description Reset Value LC0_6 0x04CC Specifies the loop counter 0 for DMA channel 6. 0x0 LC0_7 0x04EC Specifies the loop counter 0 for DMA channel 7. 0x0 LC1_0 0x0410 Specifies the loop counter 1 for DMA channel 0. 0x0 LC1_1 0x0430 Specifies the loop counter 1 for DMA channel 1. 0x0 LC1_2 0x0450 Specifies the loop counter 1 for DMA channel 2. 0x0 LC1_3 0x0470 Specifies the loop counter 1 for DMA channel 3. 0x0 LC1_4 0x0490 Specifies the loop counter 1 for DMA channel 4. 0x0 LC1_5 0x04B0 Specifies the loop counter 1 for DMA channel 5. 0x0 LC1_6 0x04D0 Specifies the loop counter 1 for DMA channel 6. 0x0 LC1_7 0x04F0 Specifies the loop counter 1 for DMA channel 7. 0x0 RSVD 0x0414 to 0x041C Reserved Undefined RSVD 0x0434 to 0x043C Reserved Undefined RSVD 0x0454 to 0x045C Reserved Undefined RSVD 0x0474 to 0x047C Reserved Undefined RSVD 0x0494 to 0x049C Reserved Undefined RSVD 0x04B4 to 0x04BC Reserved Undefined RSVD 0x04D4 to 0x04DC Reserved Undefined RSVD 0x04F4 to 0x0CFC Reserved Undefined DBGSTATUS 0x0D00 Specifies the debug status register 0x0 DBGCMD 0x0D04 Specifies the debug command register. Undefined DBGINST0 0x0D08 Specifies the debug instruction-0 register. Undefined DBGINST1 0x0D0C Specifies the debug instruction-1 register. Undefined CR0 0x0E00 Specifies the configuration register 0. 0x003F_F075 CR1 0x0E04 Specifies the configuration register 1. 0x0000_0074 CR2 0x0E08 Specifies the configuration register 2 0x0000_0000 CR3 0x0E0C Specifies the configuration register 3. 0xFFFF_FFFF CR4 0x0E10 Specifies the configuration register 4. 0xFFFF_FFFF CRD 0x0E14 Specifies the configuration register dn. 0x01F7_3732 RSVD 0x0E18 to 0x0E7C Reserved Undefined WD 0x0E80 Watchdog register 0x0
Samsung Confidential Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 8-12 Register Offset Description Reset Value periph_id_n 0x0FE0 to 0x0FEC Specifies the peripheral identification registers 0-3. Configuration- dependent pcell_id_n 0x0FF0 to 0x0FFC Specifies the prime cell identification registers 0-3. Configuration- dependent NOTE: The SFR provides description for only the restricted and fixed part of some SFR. DMA330 TRM provides detailed information of other parts and other SFRs.
Samsung Confidential
Exynos 5250_UM 9 SROM Controller
9-1
9 SROM Controller
9.1 Overview
Exynos 5250 SROM Controller (SROMC) support external 8/16-bit NOR Flash/PROM/SRAM memory.
Exynos 5250 SROM Controller supports 4-bank memory up to maximum 128 Kbyte per bank.
9.2 Features
Supports SRAM, various ROMs and NOR flash memory
Supports only 8 or 16-bit data bus
Address space: Up to 128 KB per Bank
Supports 4 banks.
Fixed memory bank start address
External wait to extend the bus cycle
Supports byte and half-word access for external memory
9.3 Block Diagram
Figure 9-1 Block Diagram of SROM Controller Introduction
SROM
DECODER
SFR
CONTROL&STATE MACHINE
SROM I/FSIGNALGENERATON
AHB I/F for SROM SFR
AHB I/F for SROM MEM
SROM MEM I/F
DATA PATH
Samsung Confidential
Exynos 5250_UM 9 SROM Controller
9-2
9.4 Functional Description
SROM Controller supports SROM interface for Bank0 to Bank3.
9.4.1 nWAIT Pin Operation
If the W AIT signal corresponding to each memory bank is enabled, the external nWAIT pin should prolong the
duration of nOE while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the
next clock after sampling nWAIT is high. The nW E signal has the same relation with nOE signal.
Figure 9-2 SROM Controller nWAIT Timing Diagram tRC
Tacs
Tcos
Tacc=4
HCLK
ADDR
nGCS
nOE
nWAIT
DATA(R)
Delayed
Sampling nWAIT
Samsung Confidential
Exynos 5250_UM 9 SROM Controller
9-3
9.4.2 Programmable Access Cycle
Figure 9-3 SROM Controller Read Timing Diagram
SROM controller supports page read operations for 32-bit 1 word. Figure 9-3 shows an example timing diagram of
16-bit data page read operation. Figure 9-4 shows an example timing diagram of 8-bit data page read operation.
Figure 9-4 SROM Controller Page Read Timing Diagram HCLK
ADDR
nGCS
DATA(R)
Tacs
Tacc
ADDRESS 0
DATA 0
nOETcos
Tacp
DATA 1
ADDRESS 1
Tacs = 2-cycleTacp = 2-cycleTcos = 2-cycleTcoh = 2-cycleTacc = 3-cycleTcah = 2-cycle
Tacp
DATA 2
Tacp
DATA 3
ADDRESS 2ADDRESS 3 HCLK
ADDR
nGCS
DATA(R)
Tacs
Tacc
Tcoh
Tcah
ADDRESS 0
DATA 0
nOETcos
Tacp
DATA 1
ADDRESS 1
Tacs = 2-cycleTacp = 2-cycleTcos = 2-cycleTcoh = 2-cycleTacc = 3-cycleTcah = 2-cycle
Samsung Confidential
Exynos 5250_UM 9 SROM Controller
9-4
Figure 9-5 SROM Controller Write Timing Diagram
HCLK
ADDR
nGCS
DATA(W)
Tacs
Tacc
Tcoh
Tcah
ADDRESS
nW ETcos
DATA
Tacs=2-cycleTacp=don’tcareTcos=2-cycleTcoh=2-cycleTacc=3-cycleTcah=2-cycle
Samsung Confidential Exynos 5250_UM 9 SROM Controller 9-5 9.5 I/O Description Signal I/O Description Pad Type nGCS[3:0] Output Bank selection signal XsramCSn[3:0] muxed ADDR[15:0] Output SROM address bus XsramADDR[15:0] muxed nOE Output SROM output enable XsramOEn muxed nW E Output SROM write enable XsramWEn muxed nW BE/nBE[1:0] Output SROM byte write enable/byte enable XsramBEn[1:0] muxed DATA[15:0] In/Out SROM data bus XsramDATA[15:0] muxed nW AIT Input SROM wait input XsramWAITn muxed
Samsung Confidential Exynos 5250_UM 9 SROM Controller 9-6 9.6 Register Description 9.6.1 Register Map Summary Base Address: 0x1225_0000 Register Offset Description Reset Value SROM_BW 0x0000 Specifies the SROM bus width & wait control 0x0000_0009 SROM_BC0 0x0004 Specifies the SROM bank 0 control register 0x000F_0000 SROM_BC1 0x0008 Specifies the SROM bank 1 control register 0x000F_0000 SROM_BC2 0x000C Specifies the SROM bank 2 control register 0x000F_0000 SROM_BC3 0x0010 Specifies the SROM bank 3 control register 0x000F_0000