Home > Samsung > Processor > Samsung Exynos 5 User Manual

Samsung Exynos 5 User Manual

Add to Favourites
    Download as PDF Print this page Share this page

    Have a look at the manual Samsung Exynos 5 User Manual online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 1705 Samsung manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.

    View all the pages
    Page
    of 881
    Add page 471 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-105  
5.9.1.88 GPLL_CON1 
ο‚· Base Address: 0x1002_0000 
ο‚· Address = Base Address + 0x0154, Reset Value = 0x0020_3800 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x0=
DCC_ENB=[21]=RW=
Enables Duty Cycle Corrector=
(only for monitoring)=
0 = Enables DCC=
1 = Disables DCC=
0x1=
AFC_ENB=x20]=RW=
Decides=whether AFC is enabled or not (Active-
low)=
0 = Enables AFC=
1 = Disables AFC=
0x0=
RSVD=x19:17]=–=Reserved=0x0=
FEED_EN=[16]=RW=Enable pin for FEED_OUT (Active-high)=0x0=
LOCK_CON_OUT=[15:14]=RW=Lock detector setting of the output margin=0x0=
LOCK_CON_IN=[13:12]=RW=Lock detector setting of the input margin=0x3=
LOCK_CON_DLY=[11:8]=RW=Lock detector setting of the detection=resolution=0x8=
RSVD=[7:5]=–=Reserved=0x0=
EXTAFC=[4:0]=RW=Enable pin for FVCO_OUT (Active-high)=0x0=
=
AFC automatically selects adaptive frequency curve of VCO using switched=current bank for:=
ο‚· Wide range  
ο‚· High phase noise (or Jitter) 
ο‚· Fast lock time 
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on 
recommended AFC_ENB and EXTAFC values.
    Add page 472 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-106  
5.9.1.89 CLK_SRC_TOP0 
ο‚· Base Address: 0x1002_0000 
ο‚· Address = Base Address + 0x0210, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0x0=
MUX_ACLK_300=
_GSCL_SEi=[25]=RW=
Control MUu_ACLK_300=
0== MUX_ACLK_300_GSCL_MIa=
1 = MUX_ACLK_300_GSCL_MID1=
0x0=
MUX_ACLK_300=
_GSCL_MID_SEi=[24]=RW=
Control MUX_ACLK_300_GSCL_MIa=
0== SCLK_MPLL_USER=
1 = SCLK_BPLL_USER=
0x0=
RSVD=[23:21]=–=Reserved=0x0=
MUX_ACLK_400_
G3D_MID_SEi=[20]=RW=
Control MUX_ACLK_400=
0== SCLK_MPLL_USER=
1 = SCLK_BPLL_USER=
0x0=
RSVD=[19:17]=–=Reserved=0x0=
MUX_ACLK_333=
_SEL=[16]=RW=
Control MUX_ACLK_333=
0== SCLK_CPLi=
1 = SCLK_MPLL_USER=
0x0=
MUX_ACLK_300=
_DISP1_SEL=[15]=RW=
Control MUX_ACLK_300=
0== MUX_ACLK_300_DISP1_MID=
1 = MUX_ACLK_300_DISP1_MID1=
0x0=
MUX_ACLK_300=
_DISP1_MID_SEL=[14]=RW=
Control MUX_ACLK_300_DISP1_MID=
0== SCLK_MPLL_USER=
1 = SCLK_BPLL_USER=
0x0=
RSVD=[13]=–=Reserved=0x0=
MUX_ACLK_200=
_SEL=[12]=RW=
Control MUX_ACLK_200=
0== SCLK_MPLL_USER=
1 = SCLK_BPLL_USER=
0x0=
RSVD=[11:9]=–=Reserved=0x0=
MUX_ACLK_166=
_SEL=[8]=RW=
Control MUX_ACLK_166=
0== SCLK_CPLi=
1 = SCLK_MPLL_USER=
0x0=
RSVD=[7:0]=–=Reserved=0x0=
=
=
    Add page 473 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-107  
5.9.1.90 CLK_SRC_TOP1 
ο‚· Base Address: 0x1002_0000 
ο‚· Address = Base Address + 0x0214, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x0=
MUX_ACLK_400_=
G3D_SEi=[28]=RW=
Control MUX_ACLK_400_G3D=
0 = MUX_ACLK_400_G3D_MID=
1 = SCLK_GPLi=
0x0=
RSVD=x27:25]=–=Reserved=0x0=
MUX_ACLK_400_=
ISP_SEi=[24]=RW=
Control MUX_ACLK_400_ISP=
0 = SCLK_MPLL_USER=
1 = SCLK_BPLL_USER=
0x0=
RSVD=[23:21]=–=Reserved=0x0=
MUX_ACLK_400_=
IOP_SEi=[20]=RW=
Control MUX_ACLK_400_IOP=
0 = SCLK_MPLL_USER=
1 = SCLK_BPLL_USER=
0x0=
RSVD=[19:17]=–=Reserved=0x0=
MUX_ACLK_MIPI_
HSI_TXBASE_SEL=[16]=RW=
Control MUX_ACLK_MIPI_HSI_TXBASE=
0 = SCLK_MPLL_USER=
1 = SCLK_BPLL_USER=
0x0=
RSVD=[15:13]=–=Reserved=0x0=
MUX_ACLK_300_
GSCL_MID1_SEi=[12]=RW=
Control MUX_ACLK_300_GSCL_MID1=
0 = SCLK_VPLi=
1 = SCLK_CPLi=
0x0=
RSVD=x11:9]=–=Reserved=0x0=
MUX_ACLK_300_
DISP1_MID1_SEL=x8]=RW=
Control MUX_ACLK_300_DISP1_MID1=
0 = SCLK_VPLi=
1 = SCLK_CPLi=
0x0=
RSVD=[7:0]=–=Reserved=0x0=
=
=
    Add page 474 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-108  
5.9.1.91 CLK_SRC_TOP2 
ο‚· Base Address: 0x1002_0000 
ο‚· Address = Base Address + 0x0218, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:29] –=Reserved=0x0=
MUX_GPLL _SEi=x28]=RW=
Control MUX_GPLL_USEo=
0 = XXTI=
1 = FOUT_GPLi=
0x0=
RSVD=x27:25]=–=Reserved=0x0=
MUX_BPLL_USEo
_SEL=x24]=RW=
Control MUX_BPLL_USEo=
0 = XXTI=
1 = MOUT_BPLi=
0x0=
RSVD=[23:21]=–=Reserved=0x0=
MUX_MPLL_USEo
_SEL=x20]=RW=
Control MUX_MPLL_USEo=
0 = XXTI=
1 = MOUT_MPLi=
0x0=
RSVD=[19:17]=–=Reserved=0x0=
MUX_VPLL_SEL=x16]=RW=
Control MUX_VPLL=
0 = XXTI=
1 = FOUT_VPLi=
0x0=
RSVD=[15:13]=–=Reserved=0x0=
MUX_EPLL_SEL=x12]=RW=
Control MUX_EPLL=
0 = XXTI=
1 = FOUT_EPLi=
0x0=
RSVD=[11:9]=–=Reserved=0x0=
MUX_CPLL_SEL=x8]=RW=
Control MUX_CPLL=
0 = XXTI=
1 = FOUT_CPLi=
0x0=
RSVD=[7:1]=–=Reserved=0x0=
VPLLSRC_SEi=[0]=RW=
Control MUX_VPLLSRC=
0 = XXTI=
1 = SCLK_HDMI24M=
0x0=
=
=
=
    Add page 475 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-109  
5.9.1.92 CLK_SRC_TOP3 
ο‚· Base Address: 0x1002_0000 
ο‚· Address = Base Address + 0x021C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x0=
MUX_ACLK_333=
_SUB_SEL=[24]=RWu=
Control MUX_ACLK_333_SUB=
0 = XXTI=
1 = ACLK_333=
This bit is cleared when MFC power goes off with=
CMU_SYSCLK_MFC_SYS_PWR_REG registers 
SYS_PW R_CFd=bit is 0=
0x0=
RSVD=[23:21]=–=Reserved=0x0=
MUX_ACLK_400=
_ISP_SUB_SEL=[20]=RWu=
Control MUX_ACLK_400_ISP_SUB=
0== XXTI=
1 = ACLK_400_ISP=
This bit is cleared when ISP power goes off with=
CMU_SYSCLK_ISP_SYS_PWR_REG registers 
SYS_PW R_CFG bit is 0=
0x0=
RSVD=[19:17]=–=Reserved=0x0=
MUX_ACLK_266=
_ISP_SUB_SEL=[16]=RWu=
Control MUX_ACLK_266_ISP_SUB=
0== XXTI=
1 = ACLK_266_ISP=
This bit is cleared when ISP power goes off with=
CMU_SYSCLK_ISP_SYS_PWR_REG registers 
SYS_PW R_CFG bit is 0=
0x0=
RSVD=[15:11]=–=Reserved=0x0=
MUX_ACLK_300=
_GSCL_SUB_SEi=[10]=RWu=
Control MUX_ACLK_300_GSCL_SUB=
0== XXTI=
1 = ACLK_300_GSCi=
This bit is cleared when GSCL power goes off with 
CMU_SYSCLK_GSCL_SYS_PWR_REG 
registers SYS_PWR_CFG bit is 0=
0x0=
RSVD=[9]=–=Reserved=0x0=
MUX_ACLK_266=
_GSCL_SUB_SEi=[8]=RWu=
Control MUX_ACLK_266_GSCL_SUB=
0== XXTI=
1 = ACLK_266_GSCi=
This bit is cleared when GSCL power goes off with 
CMU_SYSCLK_GSCL_SYS_PWR_REG 
registers SYS_PWR_CFG bit is 0=
0x0=
RSVD=[7]=–=Reserved=0x0=
MUX_ACLK_300=
_DISP1_SUB_SEL=[6]=RWu=
Control MUX_ACLK_300_DISP1_SUB=
0== XXTI=
1 = ACLK_300_DISP1=
This bit is cleared when DISP1 power goes off 
0x0=
    Add page 476 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-110  
Name Bit Type Description Reset Value 
with CMU_SYSCLK_DISP1_SYS_PWR_REG 
registers SYS_PWR_CFG bit is 0 
RSVD [5] – Reserved 0x0 
MUX_ACLK_200 
_DISP1_SUB_SEL [4] RWX 
Control MUX_ACLK_200_DISP1_SUB 
0 = XXTI 
1 = ACLK_200_DISP1 
This bit is cleared when DISP1 power goes off 
with CMU_SYSCLK_DISP1_SYS_PWR_REG 
registers SYS_PWR_CFG bit is 0 
0x0 
RSVD [3:0] – Reserved 0x0
    Add page 477 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-111  
5.9.1.93 CLK_SRC_GSCL 
ο‚· Base Address: 0x1002_0000 
ο‚· Address = Base Address + 0x0220, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GSCL_WRAP 
_B_SEL [31:28] RW 
Control MUX_GSCL_WRAP_B, the source clock of 
GSCL_WRAP_B 
0000 = XXTI 
0001 = XXTI 
0010 = SCLK_HDMI24M 
0011 = SCLK_DPTXPHY 
0100 = SCLK_USBHOST20PHY 
0101 = SCLK_HDMIPHY 
0110 = SCLK_MPLL_USER 
0111 = SCLK_EPLL 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved 
0x0 
GSCL_WRAP 
_A_SEL [27:24] RW 
Control MUX_GSCL_WRAP_A, the source clock of 
GSCL_WRAP_A 
0000 = XXTI 
0001 = XXTI 
0010 = SCLK_HDMI24M 
0011 = SCLK_DPTXPHY 
0100 = SCLK_USBHOST20PHY 
0101 = SCLK_HDMIPHY 
0110 = SCLK_MPLL_USER 
0111 = SCLK_EPLL 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved 
0x0 
RSVD [23:20] - Reserved 0x0 
CAM0_SEL [19:16] RW 
Control MUX_CAM0, the source clock of 
CAM_A_CLKOUT 
0000 = XXTI 
0001 = XXTI 
0010 = SCLK_HDMI24M 
0011 = SCLK_DPTXPHY 
0100 = SCLK_USBHOST20PHY 
0101 = SCLK_HDMIPHY 
0110 = SCLK_MPLL_USER 
0111 = SCLK_EPLL 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved 
0x0 
CAM_BAYER_SEL [15:12] RW 
Control MUX_CAM_BAYER, the source clock of 
CAM_BAYER_MCLK 
0000 = XXTI 
0001 = XXTI 
0x0
    Add page 478 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-112  
Name Bit Type Description Reset Value 
0010 = SCLK_HDMI24M 
0011 = SCLK_DPTXPHY 
0100 = SCLK_USBHOST20PHY 
0101 = SCLK_HDMIPHY 
0110 = SCLK_MPLL_USER 
0111 = SCLK_EPLL 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved 
RSVD [11:0] – Reserved 0x0
    Add page 479 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-113  
5.9.1.94 CLK_SRC_DISP1_0 
ο‚· Base Address: 0x1002_0000 
ο‚· Address = Base Address + 0x022C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:21] –=Reserved=0x0=
HDMI_SEL=x20]=RW=
Control MUX_HDMI, the source clock of HDMI link=
0 = SCLK_PIXEL=
1 = SCLK_HDMIPHY=
0x0=
DP1_EXT_MST=
_VID_SEL=x19:1S]=RW=
Control MUX_DP1_EXT_MST_VIa, the source=
clock of=DP1_EXT_MST_VIa=
0000 = XXTf=
0001 = XXTI=
0010 = SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 ==SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 = SCLK_MPLL_USEo=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001== SCLK_CPLi=
Others = Reserved=
0x0=
MIPI1_SEL=x15:12]=RW=
Control MUX_MIPI1, the source clock of 
MIPI_DSIM1=
0000== XXTI=
0001 = XXTf=
0010 = SCLK_HDMI24M=
0011 ==SCLK_DPTXPHY=
0100 = SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 = SCLK_MPLL_USEo=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001== SCLK_CPLi=
Others = Reserved=
0x0=
RSVD=x11:4]=–=Reserved=0x0=
FIMD1_SEi=x3:0]=RW=
Control MUX_FIMD1, the source clock of FIMD1=
0000 ==XXTI=
0001 = XXTI=
0010 = SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 = SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 = SCLK_MPLL_USEo=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001== SCLK_CPLi=
Others = Reserved=
0x0=
=
    Add page 480 to Favourites
    image text
    Enable zoom 
    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-114  
5.9.1.95 CLK_SRC_MAU 
ο‚· Base Address: 0x1002_0000 
ο‚· Address = Base Address + 0x0240, Reset Value = 0x0000_0001 
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0x0=
AUDIO0_SEL=[3:0]=RW=
Control MUX_AUDIO0, the source clock of 
AUDIO0=
0000 = AUDIOCDCLK0=
0001 ==XTIPLL=
0010 ==SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 ==SCLK_UHOST20PHY=
0101 ==SCLK_HDMIPHY=
0110 = SCLK_MPLL_USEo=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001== SCLK_CPLi=
Others = Reserved=
0x1=
=
=
    All Samsung manuals Comments (0)