Samsung Exynos 5 User Manual

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Exynos 5250_UM 11 Watchdog Timer 
 11-4  
11.4 Register Description 
11.4.1 Register Map Summary  
 Base Address: 0x101D_0000 
Register Offset Description Reset Value 
WTCON 0x0000 Watchdog timer control register 0x0000_8021 
WTDAT 0x0004 Watchdog timer data register 0x0000_8000 
WTCNT 0x0008 Watchdog timer count register 0x0000_8000 
WTCLRINT 0x000C Watchdog timer interrupt clear register Undefined 
 
 
  
						

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Exynos 5250_UM 11 Watchdog Timer 
 11-5  
11.4.1.1 WTCON  
 Base Address: 0x101D_0000 
 Address = Base Address + 0x0000, Reset Value = 0x0000_8021 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved==0=
Prescaler value=[15:8]=RW=Prescaler value=
The valid range is=from 0 to (28-1). 0x80 
RSVD [7:6] –=
Reserved==
(These two bits must be set to 00 in normal=
operation.)=
00=
Watchdog timer=[5]=RW=
Enables or disables t atchdog timer bit=
0 = Disables WDT bit=
1 = Enables WDT bit=
1=
Clock select=[4:3]=RW=
Determines the clock division factor=
00== 16=
01 = 32=
10 = 64====
11 = 128=
00=
Interrupt 
generation=[2]=RW=
Enables=or disables interrupt bit=
0 = Disables interrupt bit=
1 = Enables interrupt bit=
0=
RSVD=[1]=–=Reserved=
This bit must be set to 0 in normal operation.=0=
Reset 
enable/disable=[0]=RW=
Enables or disables WDT output bit for reset signal.==
0 = Disables the reset function of=WDT.=
1 = Asserts reset signal of the Exynos 5250=at=
watchdog time-out=
1=
=
The WTCON register:=
 Allows you to enable/disable the watchdog timer 
 Selects the clock signal from four different sources 
 Enables/disables interrupts 
 Enables/disables the WDT output 
 
You can use WDT to restart the Exynos 5250 to recover from malfunction. If you do not want to restart the 
controller, disable the WDT. 
If you want to use the normal timer provided by the WDT, enable the interrupt and disable the W DT. 
  
						

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Exynos 5250_UM 11 Watchdog Timer 
 11-6  
11.4.1.2 WTDAT  
 Base Address: 0x101D_0000 
 Address = Base Address + 0x0004, Reset Value = 0x0000_8000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved==0=
Count reload value=[15:0]=RW=WDT count value for reload.=0x8000=
=
The WTDAT register=specifies=the time-out duration. You cannot load the content of WTDAT into the timer counter=
at initial=t DT=operation.=After the WDTs first time-out using 0x8000=(initial value), the value of WTDAT is=
automatically reloaded into WTCNT=and WDT use this value as next time-out target.=
=
11.4.1.3 WTCNT  
 Base Address: 0x101D_0000 
 Address = Base Address + 0x0008, Reset Value = 0x0000_8000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved==0=
Count value=[15:0]=o=The current count value of=WDT=0x8000=
=
The WTCNT register contains the current count values for=WDT=during normal operation.==
NOTE: The content of the WTDAT register cannot be automatically loaded into the timer count register if the watchdog timer 
is enabled initially. Therefore, ensure to set the WTCNT register to an initial value before enabling WDT. 
 
11.4.1.4 WTCLRINT  
 Base Address: 0x101D_0000 
 Address = Base Address + 0x000C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
Interrupt clear [31:0] RW Writes any value to clear the interrupt –=
=
You can use the WTCLRINT register to clear the interrupt.=Interrupt service routine clears the=relevant interrupt=
after the interrupt service is complete. Writing any values on this register clears the interrupt. Reading=on=this=
register is not allowed.=
=
= 
						

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-1  
12 Universal Asynchronous Receiver and 
Transmitter 
12.1 Overview 
The Universal Asynchronous Receiver and Transmitter (UART) in Exynos 5250 provide:  
Four independent channels with asynchronous and serial input/output ports for general purpose (Channel 0 to 3), 
and One channel in ISP (ISP-UART Channel 0) 
All ports operate in an Interrupt-based or a DMA-based mode. The UART generates an interrupt or a DMA 
request to transfer data to and from the CPU and the UART.  
The UART supports bit rates up to 3 Mbps. Each UART channel contains two FIFOs to receive and transmit data:  
 256 bytes in Channel 0 
 64 bytes in Channel 1 and ISP-UART Channel 0,  
 16 bytes in Channel 2 and Channel 3 
UART includes programmable Baud Rates, Infrared (IR) Transmitter/Receiver, one or two Stop Bit Insertion, 5-bit, 
6-bit, 7-bit, or 8-bit Data Width and Parity Checking. 
Each UART contains a Baud-rate generator, a Transmitter, a Receiver and a Control Unit. The Baud-rate 
generator uses SCLK_UART. The Transmitter and the Receiver contain FIFOs and data shifters. The data that is 
transmitted is written to Tx FIFO, and copied to the transmit shifter. The data is then shifted out by the transmit 
data pin (TxDn). The received data is shifted from the Receive Data Pin (RxDn), and copied to Rx FIFO from the 
shifter.  
  
						

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-2  
12.2 Features 
 All channels support Interrupt-based operation 
 All channels, except ISP-UART Channel 0, support DMA-based or Interrupt-based operation 
 UART Channel 0 with 256-byte FIFO, Channel 1 and ISP-UART Channel 0 with 64-byte FIFO, Channel 2 and 
3 with 16-byte FIFO 
 All channels, except UART Channel 3, support Auto Flow Control with nRTS and nCTS 
 Supports Handshake Transmit/Receive  
Figure 12-1 illustrates the block diagram of UART. 
 
    Figure 12-1   Block Diagram of UART Buad-rate
Generator
Control 
Unit
Transmitter
Receiver
Peripheral BUS
TXDn
Clock Source
RXDn
Transmit FIFO Register
(FIFO mode)
Transmit Holding Register
(Non-FIFO mode)
Receive FIFO Register
(FIFO mode)
Receive Holding Register
(Non-FIFO mode only)
In FIFO mode, all bytes of Buffer Register are used as FIFO register.        
In non-FIFO mode, only 1 byte of Buffer Register is used as Holding register.
Transmit Shifter
Transmit Buffer Register
Receive Shifter
Receive Buffer Register  
						

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-3  
12.3 UART Description 
This section describes UART operations, such as Data Transmission, Data Reception, Interrupt Generation, 
Baud-rate Generation, Loop-back mode, Infrared modes, and Auto Flow Control.  
 
12.3.1 Data Transmission 
The data frame for transmission is programmable. It consists of a start bit, five to eight data bits, an optional parity 
bit, and one to two stop bits, specified by the line control register (ULCONn). The transmitter can also produce a 
break condition that forces the serial output to logic 0 state, for one frame transmission time. This block transmits 
the break signals, after the present transmission word is transmitted completely. After the break signal 
transmission, the transmitter continuously transmits data to Tx FIFO (Tx holding register, in case of Non-FIFO 
mode). 
 
12.3.2 Data Reception 
Similar to data transmission, the data frame for reception is also programmable. It consists of a start bit, five to 
eight data bits, an optional parity bit, and one to two stop bits in the Line Control Register (ULCONn). The receiver 
detects Overrun Error, Parity Error, Frame Error and Break Condition. Each of this error sets an error flag. 
 Overrun Error indicates that new data has overwritten the old data before it was read 
 Parity Error indicates that the receiver has detected an unexpected parity condition  
 Frame Error indicates that the received data does not have a valid stop bit  
 Break Condition indicates that the RxDn input is held in the logic 0 state for more than one frame transmission 
time 
Receive time-out condition occurs when the Rx FIFO is not empty in the FIFO mode and no more data is received 
during the frame time specified in UCON. 
 
  
						

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-4  
12.3.3 Auto Flow Control (AFC) 
The UART0, 1 and 2 in Exynos 5250 support Auto Flow Control (AFC) using nRTS and nCTS signals. In this 
case, it can be connected to external UARTs. To connect UART to a Modem, disable the AFC bit in UMCONn 
register, and control the signal of nRTS using software.  
In AFC, the nRTS signal depends on the condition of the receiver, whereas the nCTS signal controls the operation 
of transmitter. The transmitter of UART transfers the data to FIFO when nCTS signals are activated (in AFC, 
nCTS signals indicates that FIFO of other UART is ready to receive data). Before UART receives data, the nRTS 
signals must be activated when its Receive FIFO has more than 2-byte as spare. The nRTS signals must be 
inactivated when its Receive FIFO has less than 1-byte as spare (in AFC, the nRTS signals indicate that its own 
Receive FIFO is ready to receive data).  
Figure 12-2 illustrates the UART AFC Interface. 
 
    Figure 12-2   UART AFC Interface 
 
 RxD
nRTS
UART A
TxD
nCTS
UART B
TxD
nCTS
UART A
RxD
nRTS
UART B
Transmission case in
UART A
Reception case in
UART A
   
						

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-5  
12.3.4 Non Auto-Flow Control (Controlling nRTS and nCTS by Software) 
12.3.4.1 Rx Operation with FIFO 
This procedures describes the Rx Operation with FIFO: 
1. Select the transmit mode (Interrupt or DMA mode) 
2. Check the value of Rx FIFO count in UFSTATn register. When the value is less than 16, you must set the  
 value of UMCONn[0] to 1 (activate nRTS). However, when the value is equal to or greater than 16,  
 you must set the value to 0 (inactivate nRTS). 
3. Repeat the Step 2 
 
12.3.4.2 Tx Operation with FIFO 
This procedure describes the Tx Operation with FIFO: 
1. Select the transmit mode (Interrupt or DMA mode) 
2. Check the value of UMSTATn[0]. When the value is 1 (activate nCTS), you must write data to Tx FIFO  
 register 
3. Repeat the Step 2 
 
  
						

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-6  
12.3.5 Interrupt/DMA Request Generation 
Each UART in Exynos 5250 comprises of seven status (Tx/Rx/Error) signals: Overrun Error, Parity Error, Frame 
Error, Break, Receive Buffer Data Ready, Transmit Buffer Empty, and Transmit Shifter Empty. These conditions 
are indicated by the corresponding UART status register (UTRSTATn/UERSTATn). 
The Overrun Error, Parity Error, Frame Error and Break Condition specify the receive error status. W hen the 
receive-error-status-interrupt-enable bit is set to 1 in the control register (UCONn), the receive error status 
generates receive-error-status-interrupt. When a receive-error-status-interrupt-request is detected, you can 
identify the source of interrupt by reading the value of UERSTATn. 
When the receiver transfers data of the receive shifter to the receive FIFO register in FIFO mode, and the amount 
of received data is greater than or equal to the Rx FIFO Trigger Level, Rx interrupt is generated if Receive mode 
in control register (UCONn) is set to 1 (Interrupt request or Polling mode).  
In Non-FIFO mode, transferring the data of receive shifter to receive holding register causes Rx interrupt in the 
Interrupt request and Polling modes. 
When the transmitter transfers data from its transmit FIFO register to transmit shifter, and the amount of data left 
in transmit FIFO is less than or equal to the Tx FIFO Trigger Level, Tx interrupt is generated (provided Transmit 
mode in control register is selected as Interrupt request or Polling mode). In Non-FIFO mode, transferring the data 
from transmit holding register to transmit shifter, causes Tx interrupt in the Interrupt request and Polling mode. 
The Tx interrupt is always requested when the amount of data in the transmit FIFO is less than the trigger level. 
This indicates that an interrupt is requested when you enable the Tx interrupt, unless you fill the Tx buffer. 
Therefore, It is recommended to fill the Tx buffer first and then enable the Tx interrupt. 
The interrupt controllers of Exynos 5250 are categorized as the level-triggered type. You must set the interrupt 
type as Level when you program the UART control registers.  
In this situation, when Receive and Transmit modes in control register are selected as DMAn request mode, the 
DMAn request occurs instead of Rx or Tx interrupt. 
Table 12-1 describes the interrupts in connection with FIFO. 
Table 12-1   Interrupts in Connection with FIFO 
Type FIFO Mode Non-FIFO Mode 
Rx interrupt 
Generated when Rx FIFO count is greater than or 
equal to the trigger level of received FIFO. 
Generated when the amount of data in FIFO does 
not reach Rx FIFO trigger level and does not 
receive any data during the time specified (receive 
time out) in UCON. 
Generated by receive holding register 
whenever receive buffer becomes full. 
Tx interrupt 
Generated when Tx FIFO count is less than or 
equal to the trigger level of transmit FIFO (Tx FIFO 
trigger Level). 
Generated by transmit holding register 
whenever transmit buffer becomes 
empty. 
Error 
interrupt 
Generated when Frame Error, Parity Error, or 
Break Signal are detected.  
Generated if UART receives new data when Rx 
FIFO is full (overrun error).  
Generated by all errors. However, when 
another error occurs at the same time, 
only one interrupt is generated. 
  
						

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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-7  
12.3.6 UART Error Status FIFO 
UART contains the error status FIFO besides the Rx FIFO register. The Error Status FIFO indicates the date that 
is received with an error, among FIFO registers. An error interrupt is issued only when the data that contains error 
is ready to read out. To clear the error status FIFO, URXHn with an error and UERSTATn must be read out. 
For example, it is assumed that the UART Rx FIFO receives A, B, C, D, and E characters sequentially, and the 
Frame Error occurs when receiving B and the Parity Error occurs when receiving D. 
The actual UART receive error does not generate any error interrupt, because the character, which was received 
with an error was not read. The error interrupt occurs when the character is read out. 
Time Sequence Flow Error Interrupt Note 
#0 When no character is read out –=–=
#1=A, B, C, D, and E is received=–=–=
#2=After A is read out=crame error (in B) interrupt occurs=The B=has to be read out=
#3=After B is read out=–=–=
#4=After C is read out=marity error (in D) interrupt occurs=The a=has to be read out=
#5=After D is read out=–=–=
#6=After E is read out=–=–=
=
Figure 12-3 illustrates the UART Error Status FIFO. 
 
    Figure 12-3   UART Receives the Five Characters Including Two Errors -
-
-
-
-
-
-
-
-
-
-
E
D
C
B
A
Rx FIFO
URXHnUERSTATn
break errorparity errorframe error
Error Status Generator Unit
Error Status FIFO