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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-129  
15.5.5.13 SIFCCON1 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01E4, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved (should be 0)=0=
SYS_WDATA=[23:0]=RW=Controls the LCD i80 System Interface Write Data.=0=
=
15.5.5.14 SIFCCON2 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01E8, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved (should be 0)=0=
SYS_RDATA=[23:0]=o=Controls the LCD i80 System Interface Write Data.=0=
=
15.5.5.15 CRCRDATA 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x0258, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0=
CRCRDATA=[15:0]=o=CRC Read Data.=0=
=
15.5.5.16 CRCCTRL 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x025C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0=
CRCIVSYNC [19] RW 
Inverts CRC_VSYNC polarity 
0 = Non-invert 
1 = Invert 
0 
CRCIHSYNC [18] RW 
Inverts CRC_HSYNC polarity 
0 = Non-invert 
1 = Invert 
0 
CRCIVDEN [17] RW 
Inverts CRC_VDEN polarity 
0 = Non-invert 
1 = Invert 
0 
CRCIVCLK [16] RW Inverts CRC_VCLK 
polarity 0
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0 = Non-invert 
1 = Invert 
RSVD [15:9] –=Reserved=0=
CRCMXSEL=[8:4]=RW=Specifies the CRC Data Mux. Selection.=
Select n th=(0 to 23) Video data (VD) for CRC.=0=
RSVD=[3]=–=Reserved=0=
CRCCLKEN=[2]=RW=
CRCCLK Enable control=
0 = Disable=
1 = Enable=
0=
CRCSTART_F [1] RW 
CRC start control  
0 = Disable CRC logic at next frame 
1 = Enable CRC logic at next frame 
0 
CRCEN [0] RW 
Enables the CRC check 
0 = Disables CRC check 
1 = Enables CRC check 
0 
 
15.5.5.17 I80IFCONn (n = 0 to 11) 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x0280, 0x0284, 0x0288, 0x028C, 0x0290, 0x0294, 0x0298, 0x029C, 0x02A0 , 
0x02A4 , 0x02A8 , 0x02AC, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0=
LDI_CMa=[23:0]=o=Specifies the LDI command.=0=
=
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    							Samsung Confidential  
Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-1  
16 Analog to Digital Converter (ADC) 
This chapter describes the functions and usage of ADC  
 
16.1 Overview 
The 10-bit or 12-bit CMOS Analog to Digital Converter (ADC) comprises of 8-channel analog inputs. It converts 
the analog input signal into 10-bit or 12-bit binary digital codes at a maximum conversion rate of 1MSPS with 
5MHz A/D converter clock. A/D converter operates with on-chip sample-and-hold function. ADC supports low 
power mode.  
 
16.2 Features 
The ADC includes the following features: 
 Resolution: 10-bit/12-bit (optional) 
 Differential Nonlinearity Error:  2.0 LSB (Max.) 
 Integral Nonlinearity Error:  4.0 LSB (Max.) 
 Maximum Conversion Rate: 1 MSPS 
 Low Power Consumption 
 Power Supply Voltage:1.8 V 
 Analog Input Range: 0 to 1.8 V 
 On-chip sample-and-hold function 
 Normal Conversion Mode 
 Waiting for Interrupt Mode
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Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-2  
16.3 ADC Interface Operation 
16.3.1 Block Diagram ADC 
Figure 16-1 is the functional block diagram of A/D converter.  
 
    Figure 16-1   ADC Functional Block Diagram 
 ADC input 
control
Interrupt 
generation
Waiting for interrupt
VDDA_ADC
8:1
MUX
A/D
Converter
ADC
interface
INT_ADC0
AIN0
AIN5
AIN4
AIN3
AIN2
AIN1
AIN6
AIN7
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Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-3  
16.4 Function Descriptions 
16.4.1 A/D Conversion Time 
When the PCLK frequency is 66 MHz and the prescaler value is 65, total 12-bit conversion time is as follows. 
 A/D converter freq. = 66 MHz/(65 + 1) = 1 MHz 
 Conversion time = 1/(1 MHz/5 cycles) = 1/200 kHz = 5 s 
NOTE: This A/D converter was designed to operate at maximum 5 MHz clock, so the conversion rate can go up to 1MSPS. 
 
16.4.2 ADC conversion Mode  
The operation of this mode is same as AIN0 to AIN7s. To initialize this mode, set the ADCCON (ADC control 
register). 
The converted data can be read out from ADCDATX (ADC conversion data X register).  
 
16.4.3 Standby Mode 
Standby mode is activated when STANDBY bit is 1 in ADCCON register. In this mode, A/D conversion operation 
is halted and ADCDATX registers hold their values. 
 
16.4.4 Programming Notes 
1. The A/D converted data can be accessed by means of interrupt or polling method. With interrupt method,  
 the overall conversion time – from A/D converter start to converted data read - may be delayed because of  
 the return time of interrupt service routine and data access time. With polling method, to determine the read 
 time for ADCDATX register, check the ADCCON[15] – end of conversion flag – bit. 
2.   A/D conversion can be activated in different way. After ADCCON[1] – A/D conversion start-by-read mode-
 is set to 1, A/D conversion starts simultaneously when converted data is read.
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Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-4  
16.5 ADC Input Clock Diagram 
 
    Figure 16-2   Input Clock Diagram for ADC PCLK1/NADCCLK
ADCCON[13:6]
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Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-5  
16.6 I/O Descriptions 
Signal I/O Description Pad Type 
AIN[7] Input ADC Channel[7] Analog input Xadc0AIN_7 Analog 
AIN[6] Input ADC Channel[6] Analog input Xadc0AIN_6 Analog 
AIN[5] Input ADC Channel[5] Analog input Xadc0AIN_5 Analog 
AIN[4] Input ADC Channel[4] Analog input Xadc0AIN_4 Analog 
AIN[3] Input ADC Channel[3] Analog input Xadc0AIN_3 Analog 
AIN[2] Input ADC Channel[2] Analog input Xadc0AIN_2 Analog 
AIN[1] Input ADC Channel[1] Analog input Xadc0AIN_1 Analog 
AIN[0] Input ADC Channel[0] Analog input Xadc0AIN_0 Analog
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Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-6  
16.7 Register Description 
16.7.1 Register Map Summary 
 Base Address = 0x12D1_0000 
Register Offset Description Reset Value 
ADCCON 0x0000 ADC control register 0x0000_3FC4 
RSVD 0x0004 Reserved 0x0000_0058 
ADCDLY 0x0008 ADC Start or interval delay register 0x0000_00FF 
ADCDATX 0x000C ADC conversion data  Undefined 
RSVD 0x0010 Reserved Undefined 
RSVD 0x0014 Reserved 0x0000_0000 
CLRINTADC 0x0018 Clear INT_ADC0 interrupt Undefined 
ADCMUX 0x001C Specifies the analog input channel selection 0x0000_0000 
RSVD 0x0020 Reserved Undefined
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Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-7  
16.7.1.1 ADCCON 
 Base Address: 0x12D1_0000 
 Address = Base Address + 0x0000, Reset Value = 0x0000_3FC4 
Name Bit Type Description Reset Value 
RES [16] RW 
ADC output resolution selection 
0 = 10-bit A/D conversion 
1 = 12-bit A/D conversion 
0 
ECFLG [15] RW 
End of conversion flag(Read only) 
0 = A/D conversion in process 
1 = End of A/D conversion 
0 
PRSCEN [14] RW 
A/D converter prescaler enable 
0 = Disable 
1 = Enable 
0 
PRSCVL [13:6] RW 
A/D converter prescaler value Data value: 19 to 255 
The division factor is (N + 1) when the prescaler value is N. 
For example, ADC frequency is 5 MHz if APB bus clock is 100 
MHz and the prescaler value is 19. 
NOTE: This A/D converter is designed to operate at maximum 
5 MHz clock, so the prescaler value should be set such that 
the resulting clock does not exceed 5 MHz. 
0xFF 
RSVD [5:3] RSVD Reserved 0 
STANDBY [2] RW 
Standby mode select 
0 = Normal operation mode 
1 = Standby mode 
NOTE: In standby mode, prescaler should be disabled to 
reduce more leakage power consumption. 
1 
READ_ 
START [1] RW 
A/D conversion start by read 
0 = Disables start by read operation 
1 = Enables start by read operation 
0 
ENABLE_ST
ART [0] RW 
A/D conversion starts by enable.  
If READ_START is enabled, this value is not valid. 
0 = No operation 
1 = A/D conversion starts and this bit is automatically cleared 
after the start-up. 
0
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Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-8  
16.7.1.2 ADCDLY 
 Base Address: 0x12D1_0000 
 Address = Base Address + 0x0008, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
DELAY [15:0] RW 
ADC conversion is delayed by counting this value. 
Counting clock is PCLK.  
 ADC conversion delay value. 
NOTE: Do not use zero value(0x0000) 
00ff 
 
 
16.7.1.3 ADCDATX 
 Base Address: 0x12D1_0000 
 Address = Base Address + 0x000C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
XPDATA     
(Normal ADC) [11:0] R normal ADC conversion data value 
Data value: 0x0 to 0xFFF    0 
 
 
16.7.1.4 CLRINTADC 
 Base Address: 0x12D1_0000 
 Address = Base Address + 0x0018, Reset Value = Undefined 
Name Bit Type Description Reset Value 
INTADCCLR [0] W INT_ADC0 interrupt clear. Cleared if any value is written. –=
=
This register is=used to clear the interrupt. Interrupt service routine is responsible to clear interrupt after the=
interrupt service is completed. Writing any value on this register will clear up the=relevant=interrupt asserted. When=
it is read, undefined value will be returned=
=
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