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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-307  
4.4.1.446 EXT_INT50CON 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0700, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
RSVD=[27]=–=Reserved=0x0=
EXT_INT50=
_CON[6]=[26:24]=RW=
Setting the signaling method=of EXT_INT50[6]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[23]=–=Reserved=0x0=
EXT_INT50=
_CON[5]=[22:20]=RW=
Setting the signaling method=of EXT_INT50[5]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge=
0x5 to 0x7 = Reserved=
0x0=
RSVD=[19]=–=Reserved=0x0=
EXT_INT50=
_CON[4]=[18:16]=RW=
Setting the signaling method=of EXT_INT50[4]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[15]=–=Reserved=0x0=
EXT_INT50=
_CON[3]=[14:12]=RW=
Setting the signaling method=of EXT_INT50[3]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[11]=–=Reserved=0x0=
EXT_INT50=
_CON[2]=[10:8]=RW=
Setting the signaling method=of EXT_INT50[2]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[7]=–=Reserved=0x0=
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Exynos 5250_UM 4 Pad Control 
 4-308  
Name Bit Type Description Reset Value 
EXT_INT50 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT50[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT50 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT50[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0
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Exynos 5250_UM 4 Pad Control 
 4-309  
4.4.1.447 EXT_INT50_FLTCON0 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0800, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN1[3] [31] RW 
Enables Filter for EXT_INT50[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[3] [30:24] RW Filtering width of EXT_INT50[3] 0x00 
FLTEN1[2] [23] RW 
Enables Filter for EXT_INT50[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[2] [22:16] RW Filtering width of EXT_INT50[2] 0x00 
FLTEN1[1] [15] RW 
Enables Filter for EXT_INT50[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[1] [14:8] RW Filtering width of EXT_INT50[1] 0x00 
FLTEN1[0] [7] RW 
Enables Filter for EXT_INT50[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[0] [6:0] RW Filtering width of EXT_INT50[0] 0x00 
 
4.4.1.448 EXT_INT50_FLTCON1 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0804, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0x00=
FLTEN1[6]=[23]=RW=
Enables Filter=for EXT_INT50[6]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH1[6]=[22:16]=RW=Filtering width of EXT_INT50[6]=0x00=
FLTEN1[5]=[15]=RW=
Enables Filter=for EXT_INT50[5]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH1[5]=[14:8]=RW=Filtering width of EXT_INT50[5]=0x00=
FLTEN1[4]=[7]=RW=
Enables Filter=for EXT_INT50[4]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH1[4]=[6:0]=RW=Filtering width of EXT_INT50[4]=0x00=
=
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Exynos 5250_UM 4 Pad Control 
 4-310  
4.4.1.449 EXT_INT50_MASK 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0900, Reset Value = 0x0000_007F 
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0x0000000=
EXT_INT50=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT50=
_MASK[5]=[5]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT50=
_MASK[4]=[4]=RW=0x0 = Enables Interrupt=
0x1 ==Masks Interrupt=0x1=
EXT_INT50=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT50=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT50=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT50=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
4.4.1.450 EXT_INT50_PEND 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0A00, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0x0000000=
EXT_INT50=
_PEND[6]=[6]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT50=
_PEND[5]=[5]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT50=
_PEND[4]=[4]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT50=
_PEND[3]=[3]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT50=
_PEND[2]=[2]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT50=
_PEND[1]=[1]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT50=
_PEND[0]=[0]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
=
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Exynos 5250_UM 4 Pad Control 
 4-311  
4.4.1.451 EXT_INT_GRPPRI_XD 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B00, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x00000000=
EXT_INT=
_GRPPRf=[0]=RW=
EXT_INT groups priority rotate enable=
0x0===Does not=rotate (Fixed),=
0x1===Enables rotate=
0x0=
=
4.4.1.452 EXT_INT_PRIORITY_XD 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x00000000=
EXT_INT50_PRf=[0]=RW=
EXT_INT group 1 priority rotate enable=
0===Does not=rotate=(Fixed)=
1===Enables rotate=
0x0=
=
4.4.1.453 EXT_INT_SERVICE_XD 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B08, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:8] RW Reserved 0x0000000 
SVC_Group 
_Num [7:3] RW EXT_INT Service group number 0x00 
SVC_Num [2:0] RW Services this Interrupt number  0x0
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Exynos 5250_UM 4 Pad Control 
 4-312  
4.4.1.454 EXT_INT_SERVICE_PEND_XD 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B0C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:8] RW Reserved 0x0000000 
SVC_PEND [7:0] RW 0x0 = Does not occur 
0x1 = Interrupt occurs 0x00 
 
4.4.1.455 EXT_INT_GRPFIXPRI_XD 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B10, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0000000=
Highest_GRm=
_NUM=[4:0]=RW=Group number of the highest priority when fixed group=
priority mode: 1=to=25=0x00=
=
4.4.1.456 EXT_INT50_FIXPRI 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B14, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:3] –=Reserved=0x00000000=
Highest_EINT=
_NUM=[2:0]=RW=Interrupt number of the highest priority in External=Interrupt 
Group 1 (EXT_INT50) when fixed priority mode: 0=to=7=0x0=
=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-1  
5 Clock Controller 
This chapter describes the Clock Management Units (CMUs) of Exynos 5250. These CMUs control Phase Locked 
Loops (PLLs) and generate system clocks for CPU, buses, and function clocks for individual IPs in Exynos 5250. 
They also communicate with Power Management Unit (PMU) to stop clocks before entering certain low power 
mode. It results in reducing power consumption by minimizing clock toggling.
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Exynos 5250_UM 5 Clock Controller 
 5-2  
5.1 Clock Domains 
In Exynos 5250, function blocks are clocked asynchronously with each other. Therefore they provide more 
freedom in choosing operating frequencies and make physical implementation easier. 
 CPU block contains ARM A15 Dual-core processor (E4D), L2 cache controller, and CoreSight. E4D Dual-core 
operates at 1.7 GHz and CoreSight at 200 MHz. CMU in CPU block (CMU_CPU) generates all the necessary 
clocks for IPs in CPU block. It also generates certain clock enable signals for E4D Dual-core. 
DMC block contains a DRAM memory controller (DREXII), Security Sub-System (SSS), and Generic Interrupt 
Controller (GIC). DMC block has three CMUs such as CMU_CDREX, CMU_CORE, and CMU_ACP. 
CMU_CDREX generates 400 MHz/533 MHz/800 MHz DRAM clock, 266/400 MHz AXI bus clock which is 
synchronized with the DRAM clock, and 133 MHz clock for register accesses. CMU_CORE generates 266 MHz 
clock for AXI interconnector where GIC, Internal RAM, and asynchronous bridge communicates with 
CDREX_BLK, LEX_BLK, and ACP_BLK. CMU_ACP generates 266 MHz clock for Accelerator Coherency Port 
(ACP) bus. The ACP is used for memory coherency checking and connects CPU and SSS bus masters. 
 LEX_BLK, R0X_BLK and R1X_BLK blocks contain global data buses that are clocked at 266 MHz. These 
blocks transfer data between DRAM and various sub-blocks. They also contain global peripheral buses that 
are clocked at133 MHz and used for register accesses. Each block contains CMU_LEX and CMU_R0X/R1X, 
respectively, to generate necessary clocks for those buses. 
 CMU_ISP generates 266 MHz bus clock and function clock for ISP_BLK, which include FIMC_ISP, 
FIMC_SCALERC/P, and FIMC_FD. CMU_ISP also generates 133/66 MHz for register accesses. ISP_BLK 
has a separate Cortex-A5 sub-processor, which operates at 400 MHz clock that CMU_ISP generates. 
 CMU_TOP generates clocks for all the remaining function blocks, which include G3D, MFC, DISP1, GSCL, 
GEN, FSYS, MAUDIO, PERIC, and PERIS. CMU_TOP generates bus clocks, that is 400/333/300/266/200/ 
166/133/100/66 MHz, and various special clocks to operate IPs in Exynos 5250. 
NOTE: Asynchronous bus bridges are inserted between two different function blocks. 
 
Clock domains in Exynos 5250 are illustrated in Figure 5-1. 
 
    Figure 5-1   Exynos 5250 Clock Domains LEX_BLK (266/133MHz)R0X_BLK (266/133MHz)
DMCDRAM 400/533/667/800MHzBus 400/266/333MHz
CPU 1.7GHzBus 200/100MHz
PERIC 66MHzMFC (L)333MHzG3D533 MHz
ISP400/266MHz
PERIS66MHz
MFC (R)333MHz
GSCL266/333MHz
FSYS400/200MHz
DISP1200/333MHz
MAUDIO192/96MHz
GEN266/166MHz
R1X_BLK(266MHz)
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Exynos 5250_UM 5 Clock Controller 
 5-3  
Typical operating frequencies for each function block are described in Table 5-1. 
Table 5-1   Operating Frequencies in Exynos 5250 
Function Block Description Typical Operating Frequency 
CPU E4D Dual-core 1.7 GHz 
CoreSight 200 MHz 
DMC DREXII 400 MHz/533 MHz/800 MHz 
SSS, MIU 266 MHz/400 MHz 
LEX Data Bus/Peripheral Bus 266 MHz/133 MHz 
R0X/R1X Data Bus/Peripheral Bus 266 MHz/133 MHz 
G3D 3D Graphics Engine 533 MHz 
MFC Multi-format Codec 333 MHz 
ISP Image Signal Processing 266 MHz, 400 MHz for MCU_ISP 
GEN Rotator, MDMA, JPEG 266 MHz (up to 166 MHz for JPEG) 
DISP1 FIMD1, MIE1, MIPI DSI1, VP, MIXER, TVENC 200 MHz/333 MHz 
GSCL GSCL0 to 3 266 MHz/333 MHz 
FSYS USB, SATA, SDMMC, SROMC, PDMA0, PDMA1 200 MHz, 400 MHz for MCU_FSYS 
MAU AudioSS(MAUDIO) 192 MHz 
PERIC UART, I2C, SPI, I2S, PCM, SPDIF, PW M 66 MHz 
PERIS CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, 
MCTimer, WDT, RTC, KEYIF, SECKEY, TZPC 66 MHz 
NOTE: Refer to Chapter 37 Audio Subsystem for more information on MAUDIO block clocks.
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Exynos 5250_UM 5 Clock Controller 
 5-4  
5.2 Clock Declaration 
The top-level clocks in Exynos 5250 are: 
 Clocks from clock pads, that is, XRTCXTI and XXTI. 
 Clocks from CMUs (for example, ARMCLK, ACLK, HCLK, and SCLK) 
ARMCLK specifies clock for E4D Dual-core. 
SCLK (special clock) specifies all the clocks except bus clocks and processor core clock. 
 Clocks from USB PHY 
 Clocks from GPIO pads 
 
5.2.1 Clocks from Clock Pads 
Clock pads provide these clocks.  
 XRTCXTI: Specifies a clock from 32.768 kHz crystal pad with XRTCXTI and XRTCXTO pins. RTC uses this 
clock as the source of a real-time clock. The 10 M parallel resistance is required between XRTCXTI and 
XRTCXTO. 
 XXTI: Specifies a clock from external oscillator with XXTI pins. XXTI use wide-range OSC pads. This clock is 
supplied to APLL, MPLL, BPLL, CPLL, VPLL, EPLL, GPLL and USB PHY. Refer to Chapter 34 
USB2.0_HOST and 35 USB2.0_DEVICE for more information on USB PHY clock. It is recommended to 
use 24 MHz crystal because iROM was designed based on the 24 MHz input clock.
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