Samsung Exynos 5 User Manual
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Samsung Confidential Exynos 5250_UM 1 Product Overview 1-17 1.4.7 High Speed Interfaces This section includes: ï‚· USB DRD (Dual Role Device) 3.0 Interface ï‚· USB Host 2.0 Interface ï‚· USB Device 2.0 Interface ï‚· USB HSIC 1.0 Interface ï‚· SATA 3.0 Interface 1.4.7.1 USB DRD (Dual Role Device) 3.0 Interface ï‚· Both USB Device 3.0 and USB Device 2.0 compliant ï‚· Both USB HOST 3.0 and USB HOST 2.0 compliant ï‚· Supports both USB Device 3.0 interface and USB Device 2.0 interface ï‚· Supports both USB Host 3.0 interface and USB Host 2.0 interface ï‚· Supports full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB Device 2.0 interface ï‚· Supports super-speed (5 Gbps) mode with USB Device 3.0 interface ï‚· Supports one USB port (you can use USB 3.0 or USB 2.0 at a time) ï‚· On-chip USB PHY transceiver ï‚· Supports flexible endpoint configuration ï‚· Supports up to 16 bidirectional endpoints, including control endpoint 0 1.4.7.2 USB Host 2.0 Interface ï‚· USB Host 2.0 compliant ï‚· Supports low-speed (1.5 Mbps), full-speed (12 Mbps), and high-speed (480 Mbps) modes ï‚· Supports one USB Host port ï‚· On-chip USB PHY transceiver ï‚· Supports EHCI asynchronous schedule park capability ï‚· Supports EHCI programmable frame list flag
Samsung Confidential Exynos 5250_UM 1 Product Overview 1-18 1.4.7.3 USB Device 2.0 Interface ï‚· USB Device 2.0 compliant ï‚· Supports low-speed (1.5 Mbps), full-speed (12 Mbps), and high-speed (480 Mbps) modes ï‚· Supports one USB device port. (muxed with USB2.0 Host) ï‚· One Control Endpoint 0 for control transfer ï‚· 15 Device Mode programmable Endpoints 1.4.7.4 USB HSIC 1.0 Interface ï‚· USB HSIC 1.0 compliant ï‚· Supports 480 Mbps ï‚· Supports two HSIC ports ï‚· On-chip USB PHY transceiver ï‚· HSIC enable/disable control setting 1.4.7.5 SATA 3.0 Interface ï‚· Supports SATA 1.0/2.0/3.0 interface ï‚· Supports one AHCI port ï‚· On-chip SATA PHY transceiver ï‚· Supports 1.5/3.0/6.0 Gbps ï‚· Support Spread Spectrum Clocking in SATA PHY transceiver
Samsung Confidential Exynos 5250_UM 1 Product Overview 1-19 1.4.8 External Peripheral This section includes: ï‚· eMMC and SD Interface ï‚· UART Interface ï‚· UART Interface in ISP ï‚· SPI Interface ï‚· SPI Interface in ISP ï‚· I2S Bus Interface ï‚· PCM Audio Interface ï‚· AC97 Audio Interface ï‚· S/PDIF Interface ï‚· I2C Bus Interface ï‚· HS-I2C ï‚· Configurable GPIOs ï‚· Global A/D Converter 1.4.8.1 eMMC and SD Interface ï‚· Multimedia Card Protocol version 4.5 compatible (eMMC) ï‚· Secure Digital I/O (SDIO-Version 3.0) ï‚· Secure Digital Memory (SD mem-Version 2.0) ï‚· Pin configuration: 1-channel 8-bit eMMC4.5 and 1-channel SDIO3.0 and 2-channel 4-bit eMMC4.3/SD2.0 ï‚· DMA-based or Interrupt-based operation ï‚· 512 bytes FIFO for Tx/Rx 1.4.8.2 UART Interface ï‚· Four-port high-speed UART with DMA-based or interrupt-based operation ï‚· UART FIFO: 256 bytes 1-port, 64 bytes 2-port, and 16 bytes 2-port ï‚· Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit and receive ï‚· Programmable baud rate ï‚· Supports IrDA 1.0 SIR (115.2 Kbps) mode ï‚· Loop back mode for testing ï‚· Non-integer clock divide in Baud clock generation (BRM)
Samsung Confidential Exynos 5250_UM 1 Product Overview 1-20 1.4.8.3 UART Interface in ISP ï‚· One-port high-speed UART with DMA-based or interrupt-based operation ï‚· UART FIFO: 64 bytes one-port ï‚· Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit and receive ï‚· Programmable baud rate ï‚· Supports IrDA 1.0 SIR (115.2 Kbps) mode ï‚· Loop back mode for testing ï‚· Non-integer clock divide in Baud clock generation (BRM) 1.4.8.4 SPI Interface ï‚· Three-channel Serial Peripheral Interface ï‚· Up to 50 Mbps full duplex ï‚· SPI FIFO: 256 bytes 1-port, 64 bytes 2-port ï‚· DMA-based or interrupt-based operation 1.4.8.5 SPI Interface in ISP ï‚· Two-channel Serial Peripheral Interface ï‚· Up to 50 Mbps full duplex ï‚· SPI FIFO: 256 bytes 2-port ï‚· DMA-based or interrupt-based operation 1.4.8.6 I2S Bus Interface ï‚· Three-channel I2S for audio codec interface with DMA-based operation ï‚· Serial, 8/16/20/24-bit per channel data transfers ï‚· Supports I2S, MSB-justified, and LSB-justified data formats ï‚· Supports 5.1 channel (1-channel) ï‚· Various bit clock frequency and codec clock frequency support ï€ 16, 24, 32, 48, 64 fs of bit clock frequency ï€ 256, 384, 512, 768 fs of codec clock frequency
Samsung Confidential Exynos 5250_UM 1 Product Overview 1-21 1.4.8.7 PCM Audio Interface ï‚· 16-bit mono audio interface ï‚· Master mode only 1.4.8.8 AC97 Audio Interface ï‚· Independent channels for stereo PCM In, stereo PCM Out, and mono MIC In ï‚· 16-bit stereo (2-channel) audio ï‚· Variable sampling rate AC97 Codec interface (48 KHz and below) ï‚· Supports AC97 Full Specification 1.4.8.9 S/PDIF Interface ï‚· Linear PCM up to 24-bit per sample support ï‚· Non-linear PCM formats such as AC3, MPEG1, and MPEG2 support ï‚· 2x24-bit buffers that are alternately filled with data 1.4.8.10 I2C Bus Interface ï‚· Four-channel Multi-Master I2C ï‚· Serial, 8-bit oriented, and bi-directional data transfers (up to 100K-bit/s in the standard mode) ï‚· Up to 400K-bit/s in the fast mode
Samsung Confidential Exynos 5250_UM 1 Product Overview 1-22 1.4.8.11 HS-I2C ï‚· Support four channel high speed I2C mode (up to 3.1 Mbps) ï‚· Supports operation based on DMA or interrupt ï‚· Transmits and receives data separately ï‚· Supports non-integer clock division ï‚· Operates in two modes: Master and slave 1.4.8.12 Configurable GPIOs ï‚· Controls 205 External Interrupts ï‚· Controls 32 External Wake-up Interrupts ï‚· 253 multi-functional input/output ports ï‚· Controls pin states in Sleep Mode, except GPX0, GPX1, GPX2, and GPX3 (GPX0/1/2/3 pins are alive-pads) 1.4.8.13 Global A/D Converter ï‚· Eight-channel multiplexed 12-bit resolution ADC ï‚· Maximum 1M samples/sec with 5 MHz clock
Samsung Confidential Exynos 5250_UM 1 Product Overview 1-23 1.4.9 Modem Interfaces This section includes: ï‚· HSIC ï‚· MIPI HSI ï‚· C2C 1.4.9.1 HSIC ï‚· USB HSIC 1.0 compliant ï‚· Supports two HSIC ports ï‚· Supports 480 Mbps with half duplex transfer ï‚· Supports maximum 10 Cm trace length 1.4.9.2 MIPI HSI ï‚· Compliant to HSI specification version 1.0 ï‚· Full-Duplex High Speed Serial Interface ï‚· Supports eight-logical channels for both transmit and receive operations ï‚· Maximum bandwidth of 200 Mbs in both transmit and receive directions 1.4.9.3 C2C ï‚· Two DDR clock signals per direction for TX and RX paths ï‚· Scalable up to 16-bit inputs/16-bit outputs ï‚· Support for two different PHY voltages: 1.2 V and 1.8 V ï‚· Bit rates/signal: Up to 400 Mb/s per TX output signals and 400 Mb/s per RX input signals ï‚· Protocol supports In Band Flow Control without extra pins ï‚· Supports multiple outstanding transactions Reads, Writes and Interrupts ï‚· Provides signals for system to manage power management ï‚· Actively controls serial clock for power management
Samsung Confidential Exynos 5250_UM 1 Product Overview 1-24 1.4.10 Low Power Co-Processor This section includes: ï‚· Samsung Reconfigurable Processor ï‚· Cortex-A5 1.4.10.1 Samsung Reconfigurable Processor ï‚· Low power and ultra low power audio mode 1.4.10.2 Cortex-A5 ï‚· Low power co-processor unit ï‚· ARM Cortex-A5 core processor uses ARMv7-A architecture ï‚· 16 KB instruction cache and 16 KB data cache
Samsung Confidential Exynos 5250_UM 1 Product Overview 1-25 1.4.11 System Peripheral This section includes: ï‚· Real Time Clock ï‚· PLL ï‚· Timer with Pulse Width Modulation ï‚· Multi-Core Timer ï‚· 16-bit W atch Dog Timer ï‚· DMA ï‚· Generic Interrupt Controller ï‚· Power Management 1.4.11.1 Real Time Clock ï‚· Full clock features: Second, minute, hour, date, day, week, month, and year ï‚· 32.768 kHz operation ï‚· Alarm interrupt ï‚· Time-tick interrupt 1.4.11.2 PLL ï‚· Seven on-chip PLLs: APLL, MPLL, BPLL, CPLL, GPLL, EPLL, VPLL (dithered PLL) ï‚· APLL generates clock for ARM core ï‚· MPLL generates system bus clock for memory controller ï‚· BPLL generates Graphic 3D processor clock and 1066 MHz clock for memory controller if necessary ï‚· CPLL generates the clock for Multi Format Video Hardware Codec ï‚· GPLL generates the clock for Graphic 3D processor or other clocks for DVFS flexibility ï‚· EPLL generates the clocks for audio interface and other external device interfaces ï‚· VPLL generates the dithered PLL and helps to reduce the EMI of display and camera
Samsung Confidential Exynos 5250_UM 1 Product Overview 1-26 1.4.11.3 Timer with Pulse Width Modulation ï‚· Four channel 32-bit timer with PW M ï‚· One channel 32-bit internal timer with DMA-based or interrupt-based operation ï‚· Programmable duty cycle, frequency, and polarity ï‚· Dead-zone generation ï‚· Supports external clock source 1.4.11.4 Multi-Core Timer ï‚· Two private timers ï€ A 32-bit counter that generates an interrupt when it reaches zero ï€ Configurable single-shot or auto-reload modes ï€ Configurable starting values for the counter ï‚· A global timer ï€ A 64-bit incrementing counter with an auto-incrementing feature ï€ Accessible to all Cortex-A15 processor 1.4.11.5 16-bit Watch Dog Timer ï‚· Supports normal interval timer mode with interrupt request ï‚· Activates internal reset signal if the timer count value reaches 0 (time-out). ï‚· Supports level-triggered interrupt mechanism 1.4.11.6 DMA ï‚· MDMA0/MDMA1 ï€ Eight channels simultaneously for each MDMA ï€ Burst transfer mode to enhance transfer rate ï‚· PDMA ï€ 16 channels simultaneously ï€ 16 channel IO to memory, memory to IO, and IO to IO support ï€ Burst transfer mode to enhance the transfer rate