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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-8  
12.3.6.1 Infra-Red Mode 
The Exynos 5250 UART block supports both Infra-Red (IR) transmission and reception. It is selected by setting 
the Infra-red-mode bit in the UART line control register (ULCONn). Figure 12-4 illustrates how to implement the IR 
mode.  
In IR transmit mode, the transmit pulse comes out at the rate of 3/16, that is, normal serial transmit rate (when the 
transmit data bit is 0). However, in IR receive mode, the receiver must detect the 3/16 pulsed period to recognize 
a 0 value.  
Figure 12-5 illustrates the IrDA function block diagram. 
 
    Figure 12-4   IrDA Function Block Diagram 
Figure 12-5 illustrates the Serial I/O Frame Timing diagram. 
 
    Figure 12-5   Serial I/O Frame Timing Diagram (Normal UART) 
 IrDA TxEncoder
0
1
0
1
IrDA RxDecoder
TxD
RxD
TxD
IRS
RxD
RE
UART
Block
  Start
Bit
Stop
Bit
Data Bits
SIO Frame
0101001101
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-9  
Figure 12-6 illustrates the Infra-Red Transmit Mode Frame Timing diagram. 
 
    Figure 12-6   Infra-Red Transmit Mode Frame Timing Diagram 
 
Figure 12-7 illustrates the Infra-Red Receive Mode Frame Timing diagram. 
 
    Figure 12-7   Infra-Red Receive Mode Frame Timing Diagram 
 0
Start
Bit
Stop
Bit
Data  Bit s
IR  Trans mit  Frame
Bit
TimePuls e W idth  = 3/16  Bit  Fram e
000011111 0
Start
Bit
Stop
Bit
Data  Bit s
IR  Receiv e Frame
000011111
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-10  
12.4 UART Input Clock  
Figure 12-8 illustrates the Input Clock diagram for UART. 
 
  
    Figure 12-8   Input Clock Diagram for UART 
Exynos 5250 provides UART with a variety of clocks. The UART uses SCLK_UART clock which is from clock 
controller. You can also select SCLK_UART from various clock sources. Refer to Chapter 7 Clock Controller for 
more information on SCLK_UART. 
 System Controller 
DIVUART0~3(1~16)
MUXUART0~3
MOUTUART0~3
XXTIXusbXTISCLK_HDMI27MSCLK_USBPHY0SCLK_USBPHY1SCLK_HDMIPHYSCLKMPLLSCLKEPLLSCLKVPLL
UCLKUCLK Generator
UBRDIVnUFRACVALn
UART
SCLK UART
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-11  
12.5 I/O Description 
Signal I/O Description Pad Type 
UART_0_RXD Input Receives data for UART0 XuRXD_0 muxed 
UART_0_TXD Output Transmits data for UART0 XuTXD_0 muxed 
UART_0_CTSn Input Clears to send (active low) for UART0 XuCTSn_0 muxed 
UART_0_RTSn Output Requests to send (active low) for UART0 XuRTSn_0 muxed 
UART_1_RXD Input Receives data for UART1 XGPIO_URXD_1 muxed 
UART_1_TXD Output Transmits data for UART1 XGPIO_UTXD_1 muxed 
UART_1_CTSn Input Clears to send (active low) for UART1 XGPIO_UCTSN_1 muxed 
UART_1_RTSn Output Requests to send (active low) for UART1 XGPIO_URTSN_! muxed 
UART_2_RXD Input Receives data for UART2 XuRXD_2 muxed 
UART_2_TXD Output Transmits data for UART2 XuTXD_2 muxed 
UART_2_CTSn Input Clears to send (active low) for UART2 XuCTSn_2 muxed 
UART_2_RTSn Output Requests to send (active low) for UART2 XuRTSn_2 muxed 
UART_3_RXD Input Receives data for UART3 XuRXD_3 muxed 
UART_3_TXD Output Transmits data for UART3 XuTXD_3 muxed 
ISP_UART_RXD Input Receives data for ISP-UART XispGP6 muxed 
ISP_UART_TXD Output Transmits data for ISP-UART XispGP7 muxed 
ISP_UART_CTSn Input Clears to send (active low) for ISP-UART XispGP8 muxed 
ISP_UART_RTSn Output Requests to send (active low) for ISP-UART XispGP9 muxed 
NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals. 
UART external pads are shared with IrDA. To use these pads, GPIO must be set before the start of UART. 
Refer to Chapter 6 GPIO for exact settings.
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-12  
12.6 Register Description 
12.6.1 Register Map Summary  
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
Register Offset Description Reset Value 
ULCONn 0x0000 Specifies line control 0x0000_0000 
UCONn 0x0004 Specifies control 0x0000_3000 
UFCONn 0x0008 Specifies FIFO control 0x0000_0000 
UMCONn 0x000C Specifies modem control 0x0000_0000 
UTRSTATn 0x0010 Specifies Tx/Rx status 0x0000_0006 
UERSTATn 0x0014 Specifies Rx error status 0x0000_0000 
UFSTATn 0x0018 Specifies FIFO status 0x0000_0000 
UMSTATn 0x001C Specifies modem status 0x0000_0000 
UTXHn 0x0020 Specifies transmit buffer Undefined 
URXHn 0x0024 Specifies receive buffer 0x0000_0000 
UBRDIVn 0x0028 Specifies baud rate divisor 0x0000_0000 
UFRACVALn 0x002C Specifies divisor fractional value 0x0000_0000 
UINTPn 0x0030 Specifies interrupt pending 0x0000_0000 
UINTSn 0x0034 Specifies interrupt source 0x0000_0000 
UINTMn 0x0038 Specifies interrupt mask 0x0000_0000
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-13  
12.6.1.1 ULCONn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0=
Infrared=
mode=[6]=RW=
Determines=whether to use the Infrared mode =
0 = Normal mode operation=
1 = Infrared Tx/Rx mode=
0=
Parity mode=[5:3]=RW=
Specifies=the type of parity generation to be performed and 
checking during UART transmit and receive operation=
0xx = No parity=
100 = Odd parity=
101 = Even parity=
110 = Parity forced/=checked as 1=
111 = Parity forced/=checked as 0=
000=
Number of 
stop bit=[2]=RW=
Specifies=the number of stop bits that are used to signal=end-
of-frame signal=
0 = One stop bit per frame=
1 = Two stop bit per frame=
0=
Word=length=x1:0]=RW=
Indicates=the number of data bits to be transmitted or=
received per frame=
00 = 5-bit=
01 = 6-bit=
10 = 7-bit=
11== 8-bit=
00=
=
=
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-14  
12.6.1.2 UCONn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0004, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:23] –=Reserved=0=
Tx DMA=burst 
size=[22:20]=RW=
Tx DMA Burst Size=
Indicates the data transfer size of one DMA transaction 
which is triggered by a Tx=DMA request. The DMA program=
must be programmed to transfer the same data size as this 
value for a single Tx=DMA request.=
000 = 1 byte (Single)=
001 = 4 bytes=
010 = 8 bytes=
011 = Reserved==
100 = Reserved=
101 = Reserved==
110 = Reserved=
111 = Reserved=
000=
oSVa=[19]=–=Reserved=0=
Rx DMA=burst 
size=[18:16]=RW=
Rx DMA Burst Size=
Indicates=the data transfer size of one DMA transaction that=
is triggered by a ox=DMA request. The DMA program must 
be programmed to transfer the same data size as this value=
for a single Rx=DMA request.=
000 = 1 byte (Single) =
001 = 4 bytes=
010 = 8 bytes=
011 = 16 bytes=
100 = Reserved=
101 = Reserved=
110 = Reserved=
111 = Reserved=
000=
Rx=timeout 
interrupt 
interval=
[15:12]=RW=
Rx Timeout Interrupt Interval=
Rx interrupt occurs when=no data is received during 8= (N + 
1) frame time. 
The default value of this field is 3 and it indicates the timeout 
interval is 32 frame time. 
0x3 
R Time-out 
with empty R 
FIFO (4) 
[11] R/W 
Enables RX time-out feature when Rx FIFO counter is 0 
This bit is valid only when UCONn[7] is 1. 
0 = Disables Rx time-out feature when Rx FIFO is empty 
1 = Enables Rx time-out feature when Rx FIFO is empty 
0
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-15  
Name Bit Type Description Reset Value 
Rx Time-out 
DMA suspend 
enable 
[10] R/W 
Enables Rx DMA FSM to suspend when Rx Time-out occurs 
0 = Disables suspending Rx DMA FSM 
1 = Enables suspending Rx DMA FSM 
0 
Tx Interrupt 
Type [9] RW 
Interrupt request type(2) 
0 = Pulse (interrupt is requested when the Tx buffer is empty 
in the Non-FIFO mode, or when it reaches Tx FIFO Trigger 
Level in the FIFO mode) 
1 = Level (interrupt is requested when Tx buffer is empty in 
the Non-FIFO mode, or when it reaches Tx FIFO Trigger 
Level in the FIFO mode) 
0 
Rx Interrupt 
Type [8] RW 
Interrupt request type (2) 
0 = Pulse (interrupt is requested when instant Rx buffer 
receives data in the Non-FIFO mode, or when it reaches Rx 
FIFO Trigger Level in the FIFO mode) 
1 = Level (interrupt is requested when Rx buffer receives 
data in the Non-FIFO mode, or when it reaches Rx FIFO 
Trigger Level in the FIFO mode) 
0 
Rx Time Out 
Enable [7] RW 
Enables/Disables Rx time-out interrupts when UART FIFO is 
enabled. The interrupt is a receive interrupt. 
0 = Disables Rx Time-out interrupt 
1 = Enables Rx Time-out interrupt 
0 
Rx Error 
Status 
Interrupt 
Enable 
[6] RW 
Enables the UART to generate an interrupt upon an 
exception, such as, a Break, Frame Error, Parity Error, or 
Overrun Error during a receive operation. 
0 = Does not generate receive error status interrupt 
1 = Generates receive error status interrupt 
0 
Loop-back 
Mode [5] RW 
Setting loop-back bit to 1 triggers the UART to enter the 
loop-back mode. This mode is provided for test only. 
0 = Normal operation            
1 = Loop-back mode 
0 
Send Break 
Signal [4] RW 
Setting this bit triggers the UART to send a break during 1 
frame time. This bit is automatically cleared after sending the 
break signal.  
0 = Normal transmit             
1 = Sends the break signal 
0 
Transmit 
Mode [3:2] RW 
Determines which function is able to write Tx data to the 
UART transmit buffer 
00 = Disables 
01 = Interrupt request or Polling mode 
10 = DMA mode  
11 = Reserved 
00 
Receive Mode [1:0] RW 
Determines which function is able to read data from UART 
receive buffer 
00 = Disables 
01 = Interrupt request or Polling mode 
10 = DMA mode  
00
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-16  
Name Bit Type Description Reset Value 
11 = Reserved 
NOTE:  
1. DIV_VAL = UBRDIVn + UFRACVAL/16. Refer to Section 12.6.1.11 UBRDIVn (n = 0 to 4) and 
 12.6.1.12 UFRACVALn (n = 0 to 4) for more information.  
2. Exynos 5250 uses a level-triggered interrupt controller. Therefore, these bits must be set to 1 for every transfer. 
3. When the UART does not reach the FIFO trigger level, and it does not receive data during the time specified at the 
 Rx Timeout Interrupt Interval field in DMA receive mode with FIFO, the Rx interrupt is generated (receive time out). 
 You must check the FIFO status and read out the rest. 
4. UCONn[11] and UCONn[7] should be set to 1 to enable Rx time-out feature when Rx FIFO counter is 0.
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-17  
12.6.1.3 UFCONn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0008, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:11] –=Reserved=0=
Tx=FIFO=
Trigger Level=x10:8]=RW=
Determines=the trigger level of=Tx=FIFO.=When=data count of 
Tx FIFO is less than or equal to the trigger level, Tx=
interrupt occurs.=
[Channel 0]=
000== 0 byte=
001 = 32=bytes=
010 ==64=bytes=
011 ==96=bytes=
100== 128 bytes=
101 = 160 bytes=
110 ==192 bytes=
111 ==224 bytes=
[Channel 1]=
000== 0 byte=
001 = 8 bytes=
010 ==16=bytes=
011 ==24=bytes=
100== 32 bytes=
101 = 40=bytes=
110 ==48=bytes=
111 ==56=bytes=
[Channel 2, 3]=
000== 0 byte=
001 = 2 bytes=
010 ==4 bytes=
011 ==6 bytes=
100== 8 bytes=
101 = 10=bytes=
110 ==12=bytes=
111 ==14=bytes=
000=
oSVa=[7]=–=Reserved=0=
Rx=FIFO=
Trigger Level=xS:4]=RW=
Determines=the trigger level of=Rx=FIFO.=When=data count=
of Rx FIFO is greater=than or equal to the trigger level, Rx=
interrupt occurs.=
[Channel 0]=
000== 32 byte=
001 = 64=bytes=
000=
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