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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-7  
9.6.1.1 SROM_BW 
 Base Address: 0x1225_0000 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0009 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0=
ByteEnable3=[15]=RW=
nW BE/nBE (for UB/LB) control for Memory Bank3=
0 = Not using UB/LB (XsramBEn[1:0] is dedicated 
nW BE[1:0])=
1 = Using UB/LB (XsramBEn[1:0]=is dedicated=
nBE[1:0])=
0=
WaitEnable3=[14]=RW=
Wait enable control for Memory Bank3==
0 = Disables WAIT=
1 = Enables t AIT=
0=
AddrMode3=[13]=RW=
Select SROM ADDR Base for Memory Bank3=
0 = SROM_ADDR is Half-word base address.==
(SROM_ADDR[15:0]= HADDR[16:1]) 
1 = SROM_ADDR is byte base address 
(SROM_ADDR[15:0]  HADDR[15:0]) 
NOTE: When DataW idth3 is 0, SROM_ADDR is 
byte base address. (Ignored this bit.) 
0 
DataWidth3 [12] RW 
Data bus width control for Memory Bank3 
0 = 8-bit 
1 = 16-bit 
0 
ByteEnable2 [11] RW 
nW BE/nBE (for UB/LB) control for Memory Bank2 
0 = Not using UB/LB (XsramBEn[1:0] is dedicated 
nW BE[1:0]) 
1 = Using UB/LB (XsramBEn[1:0] is dedicated 
nBE[1:0]) 
0 
WaitEnable2 [10] RW 
Wait enable control for Memory Bank2 
0 = Disables WAIT 
1 = Enables W AIT 
0 
AddrMode2 [9] RW 
Select SROM ADDR Base for Memory Bank2 
0 = SROM_ADDR is Half-word base address.  
(SROM_ADDR[15:0]  HADDR[16:1]) 
1 = SROM_ADDR is byte base address 
(SROM_ADDR[15:0]  HADDR[15:0]) 
NOTE: When DataW idth2 is 0, SROM_ADDR is 
byte base address. (Ignored this bit.) 
0 
DataWidth2 [8] RW 
Data bus width control for Memory Bank2 
0 = 8-bit 
1 = 16-bit 
0 
ByteEnable1 [7] RW 
nW BE/nBE (for UB/LB) control for Memory Bank1 
0 = Not using UB/LB (XsramBEn[1:0] is dedicated 
nW BE[1:0]) 
0
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Exynos 5250_UM 9 SROM Controller 
 9-8  
Name Bit Type Description Reset Value 
1 = Using UB/LB (XsramBEn[1:0] is dedicated 
nBE[1:0]) 
WaitEnable1 [6] RW 
Wait enable control for Memory Bank1 
0 = Disables WAIT 
1 = Enables W AIT 
0 
AddrMode1 [5] RW 
Select SROM ADDR Base for Memory Bank1 
0 = SROM_ADDR is Half-word base address.  
(SROM_ADDR[15:0]  HADDR[16:1]) 
1 = SROM_ADDR is byte base address 
(SROM_ADDR[15:0]  HADDR[15:0]) 
NOTE: When DataW idth1 is 0, SROM_ADDR is 
byte base address. (Ignored this bit.) 
0 
DataWidth1 [4] RW 
Data bus width control for Memory Bank1 
0 = 8-bit 
1 = 16-bit 
0 
ByteEnable0 [3] RW 
nW BE/nBE (for UB/LB) control for Memory Bank0 
0 = Not using UB/LB (XsramBEn[1:0] is dedicated 
nW BE[1:0]) 
1 = Using UB/LB (XsramBEn[1:0] is dedicated 
nBE[1:0]) 
1 
WaitEnable0 [2] RW 
Wait enable control for Memory Bank0  
0 = Disables WAIT 
1 = Enables W AIT 
0 
AddrMode0 [1] RW 
Select SROM ADDR Base for Memory Bank0 
0 = SROM_ADDR is Half-word base address. 
(SROM_ADDR[15:0]  HADDR[16:1]) 
1 = SROM_ADDR is byte base address 
(SROM_ADDR[15:0]  HADDR[15:0]) 
NOTE: When DataW idth0 is 0, SROM_ADDR is 
byte base address. (Ignored this bit.) 
0 
DataWidth0 [0] RW 
Data bus width control for Memory Bank0 
0 = 8-bit 
1 = 16-bit 
1
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Exynos 5250_UM 9 SROM Controller 
 9-9  
9.6.1.2 SROM_BCn (n = 0 to 3) 
 Base Address: 0x1225_0000 
 Address = Base Address + 0x0004, 0x0008, 0x000C, 0x0010, Reset Value = 0x000F_0000 
Name Bit Type Description Reset Value 
Tacs [31:28] RW 
Address set-up before nGCS 
0000 = 0 Clock 
0001 = 1 Clocks 
0010 = 2 Clocks 
0011 = 3 Clocks 
………….=
1100 ==12 Clocks=
1101== 13 Clocks=
1110 = 14 Clocks=
1111 = 15 Clocks=
NOTE: More 1=–=2 cycles according to bus i/f status=
0000=
Tcos=[27:24]=RW=
Chip selection set-up before nOb=
0000 ==0 Clock=
0001 = 1 Clocks=
0010 = 2 Clocks=
0011 = 3 Clocks=
………….=
1100 ==12 Clocks=
1101 = 13 Clocks=
1110 = 14 Clocks=
1111 = 15 Clocks=
0000=
RSVD=[23:21]=–=Reserved=000=
Tacc=[20:16]=RW=
Access cycle=
00000 = 1 Clock=
00001 = 2 Clocks=
00001 = 3 Clocks=
00010 = 4 Clocks=
………….=
11100 = 29 Clocks=
11101 = 30 Clocks=
11110 = 31 Clocks=
11111 = 32 Clocks=
01111=
Tcoh=[15:12]=RW=
Chip selection hold on nOE=
0000== 0 Clock=
0001 = 1 Clocks=
0010 = 2 Clocks=
0011 = 3 Clocks=
………….=
1100 = 12 Clocks=
1101 = 13 Clocks=
1110 = 14 Clocks=
1111 = 15 Clocks=
0000=
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Exynos 5250_UM 9 SROM Controller 
 9-10  
Name Bit Type Description Reset Value 
Tcah [11:8] RW 
Address holding time after nGCSn 
0000 = 0 Clock 
0001 = 1 Clocks 
0010 = 2 Clocks 
0011 = 3 Clocks 
…………. 
1100 = 12 Clocks 
1101 = 13 Clocks 
1110 = 14 Clocks 
1111 = 15 Clocks 
NOTE: More 1 – 2 cycles according to bus I/F status 
0000 
Tacp [7:4] RW 
Page mode access cycle @ Page mode 
0000 = 0 Clock 
0001 = 1 Clocks 
0010 = 2 Clocks 
0011 = 3 Clocks 
…………. 
1100 = 12 Clocks 
1101 = 13 Clocks 
1110 = 14 Clocks 
1111 = 15 Clocks 
0000 
RSVD [3:2] – Reserved – 
PMC [1:0] RW 
Page mode configuration 
00 = Normal (1 Data) 
01 = 4 Data 
10 = Reserved 
11 = Reserved 
00
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-1  
10 Pulse Width Modulation Timer 
10.1 Overview 
The Exynos 5250 has five 32-bit Pulse Width Modulation (PWM) timers. These Timers generate internal interrupts 
for the ARM subsystem. Additionally, Timers 0, 1, 2 and 3 include a PWM function that drives an external I/O 
signal. The PWM in Timer 0 has an optional dead-zone generator capability to support a large current device. 
Timer 4 is internal timer without output pins. 
The Timers use the APB-PCLK as source clock. Timers 0 and 1 share a programmable 8-bit prescaler that 
provides the first level of division for the PCLK. Timers 2, 3, and 4 share a different 8-bit prescaler. Each timer has 
its own private clock-divider that provides a second level of clock division (prescaler divided by 2, 4, 8, or 16). 
Each Timer has its own 32-bit down-counter which is driven by the timer clock. The down-counter is initially 
loaded from the Timer Count Buffer register (TCNTBn). When the down-counter reaches zero, the timer interrupt 
request is generated to inform the CPU that the Timer operation is complete. When the Timer down-counter 
reaches zero, the value of corresponding TCNTBn automatically reloads into the down-counter to start the next 
cycle. However, when the Timer stops, for example, by clearing the timer enable bit of TCONn during the Timer 
running mode, the value of TCNTBn is not reloaded into the counter. 
The PWM function uses the value of the TCMPBn register. The Timer Control Logic changes the output level if 
down-counter value matches the value of the compare register in Timer Control Logic. Therefore, the compare 
register determines the turn-on time or turn-off time of a PWM output.  
The TCNTBn and TCMPBn registers are double buffered so that it allows the Timer parameters to be updated in 
the middle of a cycle. The new values do not take effect until the current Timer cycle is completed.
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-2  
Figure 10-1 illustrates an example of a PW M cycle: 
 
    Figure 10-1   PWM Cycle 
Steps in PWM Cycle: 
 Initialize the TCNTBn register with 159 (50 + 109) and TCMPBn with 109.  
 Start Timer: Sets the start bit and manually updates this bit to OFF. 
The TCNTBn value of 159 is loaded into the down-counter. Then, the output TOUTn is set to low. 
 When down-counter counts down the value from TCNTBn to value in the TCMPBn register 109, the output 
changes from low to high. 
 When the down-counter reaches 0, it generates an interrupt request.  
 The down-counter automatically reloads TCNTBn. This restarts the cycle. TOUTn
1234
5
50109
110
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-3  
Figure 10-2 illustrates the clock generation scheme for individual PWM Channels: 
 
    Figure 10-2   PWM TIMER Clock Tree Diagram 
The Figure 10-2 shows the clock generation scheme for individual PWM Channels. 
Each Timer can generate level interrupts. 
 6:1MUXControlLogic 0
ControlLogic 4
ControlLogic 3
ControlLogic 2
ControlLogic 1
8BITPRESCALER0
DeadZoneGenerator
TCNTB0TCMPB0
TCNTB1TCMPB1
TCNTB2TCMPB2
TCNTB3TCMPB3
TCNTB4
8BITPRESCALER1
6:1MUX
6:1MUX
6:1MUX
6:1MUX
PCLKXpwmTOUT0
No pin
DeadZone
1/1
1/2
1/16
1/8
1/4
1/1
1/2
1/16
1/8
1/4
DeadZone
XpwmTOUT1
XpwmTOUT3
XpwmTOUT2
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-4  
10.2 Features 
PW M supports these features: 
 Five 32-bit Timers 
 Two 8-bit Clock Prescalers that provide first level of division for the PCLK, and five Clock Dividers and 
Multiplexers that provide second level of division for the Prescaler clock 
 Programmable Clock Select Logic for individual PWM Channels 
 Four Independent PW M Channels with Programmable Duty Control and Polarity 
 Static Configuration: PWM is stopped 
 Dynamic Configuration: PWM is running 
 Auto-Reload and One-Shot Pulse Mode 
 Dead Zone Generator on two PWM Outputs  
 Level Interrupt Generation 
The PWM has two modes of operation: 
 Auto-Reload Mode: In this mode, continuous PW M pulses are generated based on Programmed Duty Cycle 
and Polarity. 
 One-Shot Pulse Mode: In this mode, only one PWM pulse is generated based on Programmed Duty Cycle 
and Polarity. 
To control the functionality of PWM, 18 special function registers are provided. The PWM is a programmable 
output and a clock input AMBA slave module. It connects to the Advanced Peripheral Bus (APB). These 18 
special function registers within PWM are accessed through APB transactions.
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-5  
10.3 PWM Operation 
10.3.1 Prescaler and Divider 
An 8-bit prescaler and 3-bit divider generates these output frequencies. Table 10-1 lists the minimum and 
maximum resolution based on Prescaler and Clock Divider values: 
Table 10-1   Minimum and Maximum Resolution based on Prescaler and Clock Divider Values 
4-bit Divider Settings Minimum Resolution 
(Prescaler Value = 1) 
Maximum Resolution 
(Prescaler Value = 255) 
Maximum Interval 
(TCNTBn = 4294967295) 
1/1 (PCLK = 66 MHz ) 0.030 s (33.0 MHz) 3.879 s (257.8 kHz) 16659.27 s 
1/2 (PCLK = 66 MHz ) 0.061 s (16.5 MHz ) 7.758 s (128.9 kHz ) 33318.53 s 
1/4 (PCLK = 66 MHz ) 0.121 s (8.25 MHz ) 15.515 s (64.5 kHz ) 66637.07 s 
1/8 (PCLK = 66 MHz ) 0.242 s (4.13 MHz ) 31.03 s (32.2 kHz ) 133274.14 s 
1/16 (PCLK = 66 MHz ) 0.485 s (2.06 MHz ) 62.061 s (16.1 kHz ) 266548.27 s 
 
10.3.2 Basic Timer Operation 
Figure 10-2 illustrates the Basic Timer Operation: 
 
    Figure 10-3   Timer Operations 
The Timer (except Timer channel 4) comprises of four registers: TCNTBn, TCNTn, TCMPBn and TCMPn. When 
the Timer reaches 0, the TCNTBn and TCMPBn registers are loaded into TCNTn and TCMPn. When TCNTn 
reaches 0, the interrupt request occurs if the interrupt is enabled. TCNTn and TCMPn are the names of the 
internal registers. The TCNTn register is read from the TCNTOn register. 332
01
102100
TCNTBn=2
TCMPBn=0
manual update=0
auto-reload=1
interrupt requestinterrupt requestTCNTBn=3
TCMPBn=1
manual update=1
auto-reload=1
TOUTn
TCMPn
TCNTn
auto-reload=0
command
status
timer is startedTCNTn=TCMPnauto-reloadstart bit=1TCNTn=TCMPntimer is stopped.
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-6  
To generate interrupt at intervals three-cycle of XpwmTOUTn, set TCNTBn, TCMPBn and TCON.    
Steps to generate interrupt:  
1. Set TCNTBn = 3 and TCMPBn = 1. 
2. Set auto-reload = 1 and manual update = 1.  
 When manual update bit is 1, the TCNTBn and TCMPBn values are loaded to TCNTn and TCMPn. 
3. Set TCNTBn = 2 and TCMPBn = 0 for the next operation.  
4. Set auto-reload = 1 and manual update = 0.  
 If you set manual update = 1, TCNTn is changed to 2 and TCMP is changed to 0.  
 Therefore, interrupt is generated at interval two-cycle instead of three-cycle.  
 Set auto-reload = 1 automatically, for the next operation. 
5. Set start = 1 for starting the operation. Then, TCNTn is down counting.  
 When TCNTn is 0, interrupt is generated and if auto-reload is enable, TCNTn is loaded 2 (TCNTBn value)  
 and TCMPn is loaded 0 (TCMPn value). 
6. TCNTn is down counting before it stops.
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