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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-69  
15.5.2.7 WINCON3 
ï‚· Base Address: 0x1440_0000 
ï‚· Address = Base Address + 0x002C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
BUFSTATUS 
_H [31] R 
Specifies the Buffer Status (Read-only). 
NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} 
00 = Buffer set 0 
01 = Buffer set 1 
10 = Buffer set 2 
 
BUFSEL_H [30] RW 
Selects the Buffer set. 
NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} 
00 = Buffer set 0 
01 = Buffer set 1 
10 = Buffer set 2 (available only when BUF_MODE == 1’b1)=
=
RSVD=x29:2S]=–=Reserved (should be 0)==
TRIGSTATUS=[25]=o=
Specifies the Trigger Status (Read-only).=
0 = Does not trigger=
1 = Triggers=
=
RSVD=x24:22]=–=Reserved (should be 0).==
BUFSTATUp=
_L=[21]=o=Specifies the Buffer Status (Read-only).=
NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L}==
BUFSEL_L=[20]=RW=Selects the=Buffer=set.=
NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L}==
BUFAUTOEN=[19]=RW=
Specifies the Double Buffer Auto control bit.=
0 = Fixed=by BUFSEL =
1 = Auto changed by Trigger Input=
=
BITSWP_F=[18]=RW=
Specifies the Bit Swap control bit.=
0 = Disables swap =
1 = Enables swap=
0=
BYTSt m_F=[17]=RW=
Specifies the Byte=Swap control bit.=
0 = Disables swap =
1 = Enables swap=
0=
HAt SWm_F=[16]=RW=
Specifies the Half-Word=Swap control bit.=
0 = Disables swap  ==
1 = Enables swap=
0=
WSWP_F=[15]=RW=
Specifies the Word=Swap control bit.=
0 = Disables swap =
1 = Enables swap=
=
BUF_MODE=[14]=RW=
pelects the=Auto-buffering mode.=
0 = Double==
1 = Triple=
0=
RSVD=[13:11]=–=Reserved (should be 0)=0=
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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-70  
Name Bit Type Description Reset Value 
BURSTLEN [10:9] RW 
Selects the maximum length of the DMA Burst.  
00 = 16 word-burst 
01 = 8 word-burst 
10 = 4 word-burst 
0 
RSVD [8] – Reserved (should be 0) 0 
ALPHA_MUL 
_F [7] RW 
Specifies the Multiplied Alpha value mode. 
0 = Disables multiple mode 
1 = Enables multiplied mode 
When ALPHA_MUL is set to 1, set BLD_PIX = 1, 
ALPHA_SEL = 1, and BPPMODE_F[5:2] = 4’b1101 or 
4’b1110. 
NOTE: Alpha value = alpha_pixel (from data) ï‚´ 
ALPHA0_R/G/B 
0 
BLD_PIX_F [6] RW 
Selects the blending category. 
0 = Per plane blending 
1 = Per pixel blending 
 
BPPMODE 
_F [5:2] RW 
Selects the Bits Per Pixel (bpp) mode in window image.  
0000 = 1-bpp  
0001 = 2-bpp  
0010 = 4-bpp  
0011 = 8-bpp (palletized) 
0100 = 8-bpp (non-palletized, A: 1-R:2-G:3-B:2) 
0101 = 16-bpp (non-palletized, R:5-G:6-B:5) 
0110 = 16-bpp (non-palletized, A:1-R:5-G:5-B:5) 
0111 = 16-bpp (non-palletized, I :1-R:5-G:5-B:5) 
1000 = Unpacked 18-bpp (non-palletized, R:6-G:6-B:6 )  
1001 = Unpacked 18-bpp (non-palletized, A:1-R:6-G:6-B:5)  
1010 = Unpacked 19-bpp (non-palletized, A:1-R:6-G:6-B:6) 
1011 = Unpacked 24-bpp (non-palletized R:8-G:8-B:8)  
1100 = Unpacked 24-bpp (non-palletized A:1-R:8-G:8-B:7)  
*1101 = Unpacked 25-bpp (non-palletized A:1-R:8-G:8-B:8) 
*1110 = Unpacked 13-bpp (non-palletized A:1-R:4-G:4-B:4) 
1111 = Unpacked 15-bpp (non-palletized R:5-G:5-B:5) 
NOTE:  
*1101 = Supports unpacked 32-bpp (non-palletized A:8-R:8-
G:8-B:8) for per pixel blending 
*1110 = Supports 16-bpp (non-palletized A: 4-R:4-G:4-B:4) 
for per pixel blending (16 level blending) 
0 
ALPHA_SEL 
_F [1] RW 
Selects the Alpha value. 
For per plane blending BLD_PIX == 0: 
0 = Uses ALPHA0_R/G/B values 
1 = Uses ALPHA1_R/G/B values  
 
For per pixel blending BLD_PIX == 1: 
0 = Selected by AEN (A value)  
1 = Uses DATA[31:24] data in word boundary (only when 
BPPMODE_F = 4’b1101)  
0
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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-71  
Name Bit Type Description Reset Value 
DATA[31:28], [15:12] data in word boundary (only when 
BPPMODE_F = 4’b1110) 
ENW IN_F [0] RW 
Enables/disables video output and logic. 
0 = Disables the video output and video control signal 
1 = Enables the video output and video control signal 
0
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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-72  
15.5.2.8 WINCON4 
ï‚· Base Address: 0x1440_0000 
ï‚· Address = Base Address + 0x0030, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
BUFSTATUS 
_H [31] R 
Specifies the Buffer Status (Read-only). 
NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L} 
00 = Buffer set 0 
01 = Buffer set 1 
10 = Buffer set 2 
0 
BUFSEL_H [30] RW 
Selects the Buffer set. 
NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L} 
00 = Buffer set 0 
01 = Buffer set 1 
10 = Buffer set 2 (only available where BUF_MODE == 1’b1)=
0=
RSVD=x29:2S]=–=Reserved (should be 0)=0=
TRIGSTATUS=[25]=o=
Specifies the Trigger Status (Read-only).=
0 = Does not trigger==
1 = Triggers=
0=
oSVa=x24:22]=–=Reserved (should be 0)=0=
BUFSTATUp=
_L=[21]=o=Specifies the Buffer Status (Read-only).=
NOTE: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L}=0=
BUFSEL_L=[20]=RW=Selects the=Buffer=set.=
NOTE: BUFSEL = {BUFSEL_H, BUFSEL_L}=0=
BUFAUTOEN=[19]=RW=
Specifies the Double=Buffer Auto control bit.=
0 = Fixed=by BUFSEL  ==
1 = Auto changed by Trigger Input=
0=
BITSWP_F=[18]=RW=
Specifies the Bit Swap control bit.=
0 = Disables swap =
1 = Enables swap=
0=
BYTSt m_F=[17]=RW=
Specifies the Byte=Swap control bit.=
0 = Disables swap  ==
1 = Enables swap=
0=
HAt SWm_F=[16]=RW=
Specifies the Half-Word=Swap control bit.=
0 = Disables swap  ==
1 = Enables swap=
0=
WSWP_F=[15]=RW=
Specifies the Word=Swap control bit.=
0 = Disables swap  ==
1 = Enables swap=
0=
BUF_MODE=[14]=RW=
pelects the=Auto-buffering mode.=
0 = Double= = = ==
1 = Triple=
0=
oSVa=[13:11]=–=Reserved (should be 0)=0=
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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-73  
Name Bit Type Description Reset Value 
BURSTLEN [10:9] RW 
Selects the maximum length of the DMA Burst. 
00 = 16 word-burst 
01 = 8 word-burst 
10 = 4 word-burst 
0 
RSVD [8] RW Reserved (should be 0) 0 
ALPHA_MUL 
_F [7] RW 
Specifies the Multiplied Alpha value mode. 
0 = Disables multiple mode 
1 = Enables multiplied mode 
When ALPHA_MUL is set to 1, set BLD_PIX = 1, 
ALPHA_SEL = 1, and BPPMODE_F[5:2] = 4’b1101 or 
4’b1110. 
NOTE: Alpha value = alpha_pixel (from data) ï‚´ 
ALPHA0_R/G/B  
0 
BLD_PIX_F [6] RW 
Selects the blending category. 
0 = Per plane blending 
1 = Per pixel blending 
0 
BPPMODE_F [5:2] RW 
Selects the Bits Per Pixel (bpp) mode in window image.  
0000 = 1-bpp  
0001 = 2-bpp  
0010 = 4-bpp  
0011 = 8-bpp (palletized) 
0100 = 8-bpp (non-palletized, A: 1-R:2-G:3-B:2) 
0101 = 16-bpp (non-palletized, R:5-G:6-B:5) 
0110 = 16-bpp (non-palletized, A:1-R:5-G:5-B:5) 
0111 = 16-bpp (non-palletized, I :1-R:5-G:5-B:5) 
1000 = Unpacked 18-bpp (non-palletized, R:6-G:6-B:6)  
1001 = Unpacked 18-bpp (non-palletized, A:1-R:6-G:6-B:5)  
1010 = Unpacked 19-bpp (non-palletized, A:1-R:6-G:6-B:6) 
1011 = Unpacked 24-bpp (non-palletized, R:8-G:8-B:8)  
1100 = Unpacked 24-bpp (non-palletized, A:1-R:8-G:8-B:7)  
*1101 = Unpacked 25-bpp (non-palletized, A:1-R:8-G:8-B:8) 
*1110 = Unpacked 13-bpp (non-palletized, A:1-R:4-G:4-B:4) 
1111 = Unpacked 15-bpp (non-palletized, R:5-G:5-B:5) 
NOTE:  
ï‚· 1101 = Support unpacked 32-bpp (non-palletized, A: 8-
R:8-G:8-B:8) for per pixel blending 
ï‚· 1110 = Support 16-bpp (non-palletized A:4-R:4-G:4-B:4) 
for per pixel blending(16 level blending) 
0 
ALPHA_SEL 
_F [1] RW 
Selects the Alpha value. 
For per plane blending BLD_PIX == 0: 
0 = Uses ALPHA0_R/G/B values 
1 = Uses ALPHA1_R/G/B values  
 
For per pixel blending BLD_PIX == 1: 
0 = Selected by AEN (A value)  
1 = Uses DATA[31:24] data in word boundary (only when 
BPPMODE_F = 4’b1101)  
0
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Exynos 5250_UM 15 Display Controller 
 15-74  
Name Bit Type Description Reset Value 
DATA[31:28], [15:12] data in word boundary (only when 
BPPMODE_F = 4’b1110) 
ENW IN_F [0] RW 
Enables/disables video output and logic. 
0 = Disables the video output and video control signal 
1 = Enables the video output and video control signal 
0
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Exynos 5250_UM 15 Display Controller 
 15-75  
15.5.2.9 SHADOWCON 
ï‚· Base Address: 0x1440_0000 
ï‚· Address = Base Address + 0x0034, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:15] –=Reserved (should be 0)=0=
W4_SHADOt =
_PROTECT=[14]=RW=
mrotects=tindow 4 phadow register (xxx_F).=
0 = Updates shadow register per frame=
1 = Protects to update register (Updates=shadow register in=
the=next frame,=after=SHADOW_PROTECT turns to 1’b0)=
0=
W3_SHADOt =
_PROTECT=[13]=RW=
mrotects=tindow 3 phadow register (xxx_F).=
0 = Updates shadow register per frame=
1 = Protects to update register (Updates=shadow register in=
the=next frame,=after=SHADOW_PROTECT turns to 1’b0)=
0=
W2_SHADOt =
_PROTECT=[12]=RW=
mrotects=tindow 2 phadow register (xxx_F).=
0 = Updates shadow register per frame=
1 = Protects to update register (Updates=shadow register in=
the next frame,=after=SHADOW_PROTECT turns to 1’b0)=
0=
W1_SHADOt =
_PROTECT=[11]=RW=
mrotects=tindow 1 phadow register (xxx_F).=
0 = Updates shadow register per frame=
1 = Protects to update register (Updates=shadow register in=
the next frame,=after SHADOW_PROTECT turns to 1’b0=
0=
W0_SHADOt =
_PROTECT=[10]=RW=
mrotects=tindow 0 phadow register (xxx_F).=
0 = Updates shadow register per frame=
1 = Protects to update register (Updates=shadow register in=
the=next frame,=after=SHADOW_PROTECT turns to  =
1’b0)=
0=
oSVa=[9:8]=–=Reserved=0=
C2_ENLOCAL=
_F=7=RW=
Enables Local path of Channel 2=
0===Disables local path =
1===Enables local path=
0=
C1_ENLOCAL=
_F=S=RW=
Enables Local path of Channel 1=
0===Disables local path =
1===Enables local path=
0=
C0_ENLOCAL=
_F=5=RW=
Enables Local path of Channel 0=
0===Disables local path =
1===Enables local path=
0=
C4_EN_c=4=RW=
Enables Channel 4=
0===Disables channel=
1===Enables channel=
0=
C3_EN_c=3=RW=
Enables Channel 3=
0===Disables channel=
1===Enables channel=
0=
C2_EN_c=2=RW=Enables Channel 2=
0===Disables channel= = ==0=
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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-76  
Name Bit Type Description Reset Value 
1 = Enables channel 
C1_EN_F 1 RW 
Enables Channel 1 
0 = Disables channel 
1 = Enables channel 
0 
C0_EN_F 0 RW 
Enables Channel 0 
0 = Disables channel    
1 = Enables channel 
0
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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-77  
15.5.2.10 VIDOSD0A  
ï‚· Base Address: 0x1440_0000 
ï‚· Address = Base Address + 0x0040, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_LeftTopX 
_F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Left Top pixel of OSD image. 0 
OSD_LeftTopY 
_F_E [22] RW Specifies the extended vertical screen coordinate for the 
Left Top pixel of OSD image. 0 
OSD_LeftTopX_F [21:11] RW Specifies the horizontal screen coordinate for the Left 
Top pixel of OSD image. 0 
OSD_LeftTopY_F [10:0] RW Specifies the vertical screen coordinate for the Left Top 
pixel of OSD image. 0 
 
15.5.2.11 VIDOSD0B 
ï‚· Base Address: 0x1440_0000 
ï‚· Address = Base Address + 0x0044, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_RightBotX 
_F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Right Bottom pixel of OSD image. 0 
OSD_RightBotY 
_F_E [22] RW Specifies the extended vertical screen coordinate for the 
Rght Bottom pixel of OSD image. 0 
OSD_RightBotX_F [21:11] RW Specifies the horizontal screen coordinate for the Right 
Bottom pixel of OSD image. 0 
OSD_RightBotY_F [10:0] RW Specifies the vertical screen coordinate for the Right 
Bottom pixel of OSD image. 0 
NOTE: Registers must contain word boundary X position. Therefore, ensure that the:  
  24-bpp mode contains X position by 1 pixel (for example, X = 0, 1, 2, 3….) 
  16-bpp mode contains X position by 2 pixel (for example, X = 0, 2, 4, 6….) 
  8-bpp mode contains X position by 4 pixels (for example, X = 0, 4, 8, 12….)
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Exynos 5250_UM 15 Display Controller 
 15-78  
15.5.2.12 VIDOSD0C 
ï‚· Base Address: 0x1440_0000 
ï‚· Address = Base Address + 0x0048, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [25:24] –=Reserved (should be 0)=0=
OSDSIZb=[23:0]=RW=Specifies the Window Size.=
For example,=Height=ï‚´ W idth (number of words) 0 
 
15.5.2.13 VIDOSD1A 
ï‚· Base Address: 0x1440_0000 
ï‚· Address = Base Address + 0x0050, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_LeftTopX 
_F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Left Top pixel of OSD image. 0 
OSD_LeftTopY 
_F_E [22] RW Specifies the extended vertical screen coordinate for 
the Left Top pixel of OSD image. 0 
OSD_LeftTopX_F [21:11] RW Specifies the horizontal screen coordinate for the Left 
Top pixel of OSD image. 0 
OSD_LeftTopY_F [10:0] RW Specifies the vertical screen coordinate for the Left Top 
pixel of OSD image. 0
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