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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
    Exynos 5250_UM 15 Display Controller 
     15-49  
    15.4 Programmers Model 
    15.4.1  Overview 
    Registers to configure the display controller: 
    1. VIDCON0: Configures video output format and displays enable/disable 
    2. VIDCON1: Specifies the RGB I/F control signal 
    3. VIDCON2: Specifies the output data format control 
    4. VIDCON3: Specifies the image enhancement control 
    5. I80IFCONx: Specifies CPU interface control signal. 
    6. VIDTCONx: Configures video output timing and determines the size of display 
    7. WINCONx: Specifies the setting of each window feature  
    8. VIDOSDxA, VIDOSDxB: Specifies the setting of each window position  
    9. VIDOSDxC,D: Specifies the setting of OSD size 
    10. VIDWxALPHA0/1: Specifies the setting of alpha value 
    11. BLENDEQx: Specifies the setting of blending equation 
    12. VIDWxxADDx: Specifies the setting of source image address  
    13. WxKEYCONx: Specifies the Color Key Setting register  
    14. WxKEYALPHA: Specifies the setting of color key alpha value 
    15. WINxMAP: Specifies the window color control  
    16. COLORGAINCON: Specifies the setting of color gain value 
    17. WPALCON: Specifies the Palette Control register  
    18. WxPDATAxx: Specifies the window palette data of each index  
    19. SHDOW CON: Specifies the Shadow Control register 
     
      
    						
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    15.5 Register Description 
    15.5.1 Register Map Summary 
      Base Address: 0x1440_0000 
    Register Offset Description Reset Value 
    MIXER Registers 
    VIDCON0 0x0000 Specifies the video control 0 register 0x0000_0000 
    VIDCON2 0x0008 Specifies the video control 2 register 0x0000_0000 
    VIDCON3 0x000C Specifies the video control 3 register 0x0000_0000 
    WINCON0 0x0020 Specifies the window control 0 register 0x0000_0000 
    WINCON1 0x0024 Specifies the window control 1 register 0x0000_0000 
    WINCON2 0x0028 Specifies the window control 2 register 0x0000_0000 
    WINCON3 0x002C Specifies the window control 3 register 0x0000_0000 
    WINCON4 0x0030 Specifies the window control 4 register 0x0000_0000 
    SHADOWCON 0x0034 Specifies the window shadow control register 0x0000_0000 
    VIDOSD0A 0x0040 Specifies the video window 0 position control register 0x0000_0000 
    VIDOSD0B 0x0044 Specifies the video window 0 position control register 0x0000_0000 
    VIDOSD0C 0x0048 Specifies the video window 0 size control register 0x0000_0000 
    VIDOSD1A 0x0050 Specifies the video window 1 position control register 0x0000_0000 
    VIDOSD1B 0x0054 Specifies the video window 1 position control register 0x0000_0000 
    VIDOSD1C 0x0058 Specifies the video window 1 alpha control register 0x0000_0000 
    VIDOSD1D 0x005C Specifies the video window 1 size control register 0x0000_0000 
    VIDOSD2A 0x0060 Specifies the video window 2 position control register 0x0000_0000 
    VIDOSD2B 0x0064 Specifies the video window 2 position control register 0x0000_0000 
    VIDOSD2C 0x0068 Specifies the video window 2 alpha control register 0x0000_0000 
    VIDOSD2D 0x006C Specifies the video window 2 size control register 0x0000_0000 
    VIDOSD3A 0x0070 Specifies the video window 3 position control register 0x0000_0000 
    VIDOSD3B 0x0074 Specifies the video window 3 position control register 0x0000_0000 
    VIDOSD3C 0x0078 Specifies the video window 3 alpha control register 0x0000_0000 
    VIDOSD4A 0x0080 Specifies the video window 4 position control register 0x0000_0000 
    VIDOSD4B 0x0084 Specifies the video window 4 position control register 0x0000_0000 
    VIDOSD4C 0x0088 Specifies the video window 4 alpha control register 0x0000_0000 
    VIDW00ADD0B0 0x00A0 Specifies the window 0 buffer start address register, buffer 0 0x0000_0000 
    VIDW00ADD0B1 0x00A4 Specifies the window 0 buffer start address register, buffer 1 0x0000_0000 
    VIDW00ADD0B2 0x20A0 Specifies the window 0 buffer start address register, buffer 2 0x0000_0000 
    VIDW01ADD0B0 0x00A8 Specifies the window 1 buffer start address register, buffer 0 0x0000_0000 
    VIDW01ADD0B1 0x00AC Specifies the window 1 buffer start address register, buffer 1 0x0000_0000 
    VIDW01ADD0B2 0x20A8 Specifies the window 1 buffer start address register, buffer 2 0x0000_0000  
    						
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    Register Offset Description Reset Value 
    VIDW02ADD0B0 0x00B0 Specifies the window 2 buffer start address register, buffer 0 0x0000_0000 
    VIDW02ADD0B1 0x00B4 Specifies the window 2 buffer start address register, buffer 1 0x0000_0000 
    VIDW02ADD0B2 0x20B0 Specifies the window 2 buffer start address register, buffer 2 0x0000_0000 
    VIDW03ADD0B0 0x00B8 Specifies the window 3 buffer start address register, buffer 0 0x0000_0000 
    VIDW03ADD0B1 0x00BC Specifies the window 3 buffer start address register, buffer 1 0x0000_0000 
    VIDW03ADD0B2 0x20B8 Specifies the window 3 buffer start address register, buffer 2 0x0000_0000 
    VIDW04ADD0B0 0x00C0 Specifies the window 4 buffer start address register, buffer 0 0x0000_0000 
    VIDW04ADD0B1 0x00C4 Specifies the window 4 buffer start address register, buffer 1 0x0000_0000 
    VIDW04ADD0B2 0x20C0 Specifies the window 4 buffer start address register, buffer 2 0x0000_0000 
    VIDW00ADD1B0 0x00D0 Specifies the window 0 buffer end address register, buffer 0 0x0000_0000 
    VIDW00ADD1B1 0x00D4 Specifies the window 0 buffer end address register, buffer 1 0x0000_0000 
    VIDW00ADD1B2 0x20D0 Specifies the window 0 buffer end address register, buffer 2 0x0000_0000 
    VIDW01ADD1B0 0x00D8 Specifies the window 1 buffer end address register, buffer 0 0x0000_0000 
    VIDW01ADD1B1 0x00DC Specifies the window 1 buffer end address register, buffer 1 0x0000_0000 
    VIDW01ADD1B2 0x20D8 Specifies the window 1 buffer end address register, buffer 2 0x0000_0000 
    VIDW02ADD1B0 0x00E0 Specifies the window 2 buffer end address register, buffer 0 0x0000_0000 
    VIDW02ADD1B1 0x00E4 Specifies the window 2 buffer end address register, buffer 1 0x0000_0000 
    VIDW02ADD1B2 0x20E0 Specifies the window 2 buffer end address register, buffer 2 0x0000_0000 
    VIDW03ADD1B0 0x00E8 Specifies the window 3 buffer end address register, buffer 0 0x0000_0000 
    VIDW03ADD1B1 0x00EC Specifies the window 3 buffer end address register, buffer 1 0x0000_0000 
    VIDW03ADD1B2 0x20E8 Specifies the window 3 buffer end address register, buffer 2 0x0000_0000 
    VIDW04ADD1B0 0x00F0 Specifies the window 4 buffer end address register, buffer 0 0x0000_0000 
    VIDW04ADD1B1 0x00F4 Specifies the window 4 buffer end address register, buffer 1 0x0000_0000 
    VIDW04ADD1B2 0x20F0 Specifies the window 4 buffer end address register, buffer 2 0x0000_0000 
    VIDW00ADD2 0x0100 Specifies the window 0 buffer size register 0x0000_0000 
    VIDW01ADD2 0x0104 Specifies the window 1 buffer size register 0x0000_0000 
    VIDW02ADD2 0x0108 Specifies the window 2 buffer size register 0x0000_0000 
    VIDW03ADD2 0x010C Specifies the window 3 buffer size register 0x0000_0000 
    VIDW04ADD2 0x0110 Specifies the window 4 buffer size register 0x0000_0000 
    VIDINTCON0 0x0130 Specifies the video interrupt control register 0x0000_0000 
    VIDINTCON1 0x0134 Specifies the video interrupt pending register 0x0000_0000 
    W1KEYCON0 0x0140 Specifies the color key control register 0x0000_0000 
    W1KEYCON1 0x0144 Specifies the color key value (transparent value) register 0x0000_0000 
    W2KEYCON0 0x0148 Specifies the color key control register 0x0000_0000 
    W2KEYCON1 0x014C Specifies the color key value (transparent value) register 0x0000_0000 
    W3KEYCON0 0x0150 Specifies the color key control register 0x0000_0000 
    W3KEYCON1 0x0154 Specifies the color key value (transparent value) register 0x0000_0000  
    						
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    Register Offset Description Reset Value 
    W4KEYCON0 0x0158 Specifies the color key control register 0x0000_0000 
    W4KEYCON1 0x015C Specifies the color key value (transparent value) register 0x0000_0000 
    W1KEYALPHA 0x0160 Specifies the color key alpha value register 0x0000_0000 
    W2KEYALPHA 0x0164 Specifies the color key alpha value register 0x0000_0000 
    W3KEYALPHA 0x0168 Specifies the color key alpha value register 0x0000_0000 
    W4KEYALPHA 0x016C Specifies the color key alpha value register 0x0000_0000 
    WIN0MAP 0x0180 Specifies the window 0 color control 0x0000_0000 
    WIN1MAP 0x0184 Specifies the window 1 color control 0x0000_0000 
    WIN2MAP 0x0188 Specifies the window 2 color control 0x0000_0000 
    WIN3MAP 0x018C Specifies the window 3 color control 0x0000_0000 
    WIN4MAP 0x0190 Specifies the window 4 color control 0x0000_0000 
    WPALCON_H 0x019C Specifies the window palette control register 0x0000_0000 
    WPALCON_L 0x01A0 Specifies the window palette control register 0x0000_0000 
    LAYERSYNC_CON 0x01C0 LayerSync for 3D display control register 0xFFFF_FF00 
    VIDW0ALPHA0 0x021C Specifies the window 0 alpha value 0 register 0x0000_0000 
    VIDW0ALPHA1 0x0220 Specifies the window 0 alpha value 1 register 0x0000_0000 
    VIDW1ALPHA0 0x0224 Specifies the window 1 alpha value 0 register 0x0000_0000 
    VIDW1ALPHA1 0x0228 Specifies the window 1 alpha value 1 register 0x0000_0000 
    VIDW2ALPHA0 0x022c Specifies the window 2 alpha value 0 register 0x0000_0000 
    VIDW2ALPHA1 0x0230 Specifies the window 2 alpha value 1 register 0x0000_0000 
    VIDW3ALPHA0 0x0234 Specifies the window 3 alpha value 0 register 0x0000_0000 
    VIDW3ALPHA1 0x0238 Specifies the window 3 alpha value 1 register 0x0000_0000 
    VIDW4ALPHA0 0x023c Specifies the window 4 alpha value 0 register 0x0000_0000 
    VIDW4ALPHA1 0x0240 Specifies the window 4 alpha value 1 register 0x0000_0000 
    BLENDEQ1 0x0244 Specifies the window 1 blending equation control register 0x0000_00c2 
    BLENDEQ2 0x0248 Specifies the window 2 blending equation control register 0x0000_00c2 
    BLENDEQ3 0x024C Specifies the window 3 blending equation control register 0x0000_00c2 
    BLENDEQ4 0x0250 Specifies the window 4 blending equation control register 0x0000_00c2 
    BLENDCON 0x0260 Specifies the blending control register 0x0000_0000 
    W013DSTREOCON 0x0254 Specifies the window 0/1 3D stereoscopic control register 0x0000_0000 
    W233DSTREOCON 0x0258 Specifies the window 2/3 3D stereoscopic control register 0x0000_0000 
    SHD_VIDW00ADD
    0 0x40A0 Specifies the window 0 buffer atart address register 
    (shadow) 0x0000_0000 
    SHD_VIDW01ADD
    0 0x40A8 Specifies the window 1 buffer start address register 
    (shadow) 0x0000_0000 
    SHD_VIDW02ADD
    0 0x40B0 Specifies the window 2 buffer start address register 
    (shadow) 0x0000_0000  
    						
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    Register Offset Description Reset Value 
    SHD_VIDW03ADD
    0 0x40B8 Specifies the window 3 buffer start address register 
    (shadow) 0x0000_0000 
    SHD_VIDW04ADD
    0 0x40C0 Specifies the window 4 buffer start address register 
    (shadow) 0x0000_0000 
    SHD_VIDW00ADD
    1 0x40D0 Specifies the window 0 buffer end address register (shadow) 0x0000_0000 
    SHD_VIDW01ADD
    1 0x40D8 Specifies the window 1 buffer end address register (shadow) 0x0000_0000 
    SHD_VIDW02ADD
    1 0x40E0 Specifies the window 2 buffer end address register (shadow) 0x0000_0000 
    SHD_VIDW03ADD
    1 0x40E8 Specifies the window 3 buffer end address register (shadow) 0x0000_0000 
    SHD_VIDW04ADD
    1 0x40F0 Specifies the window 4 buffer end address register (shadow) 0x0000_0000 
    SHD_VIDW00ADD
    2 0x4100 Specifies the window 0 buffer size register (shadow) 0x0000_0000 
    SHD_VIDW01ADD
    2 0x4104 Specifies the window 1 buffer size register (shadow) 0x0000_0000 
    SHD_VIDW02ADD
    2 0x4108 Specifies the window 2 buffer size register (shadow) 0x0000_0000 
    SHD_VIDW03ADD
    2 0x410C Specifies the window 3 buffer size register (shadow) 0x0000_0000 
    SHD_VIDW04ADD
    2 0x4110 Specifies the window 4 buffer size register (shadow) 0x0000_0000 
     
      
    						
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     Base Address: 0x1440_0000 
    Register Start Offset End Offset Description Reset Value 
    Palette Memory (PalRam) 
    Win0 alRam 0x2400 0x27FC Specifies 0 to 255 entry palette data Undefined 
    Win1 alRam 0x2800 0x2BFC Specifies 0 to 255 entry palette data Undefined 
    Win2 alRam 0x2C00 0x2FFC Specifies 0 to 255 entry palette data Undefined 
    Win3 alRam 0x3000 0x33FC Specifies 0 to 255 entry palette data Undefined 
    Win4 alRam 0x3400 0x37FC Specifies 0 to 255 entry palette data Undefined 
     
     Base Address: 0x1441_0000 
    Register Offset Description Reset Value 
    Enhancer Registers 
    COLORGAINCON 0x01C0 Specifies the color gain control register 0x1004_0100 
     
     Base Address: 0x1442_0000 
    Register Offset Description Reset Value 
    LCDIF Registers 
    VIDOUT_CON 0x0000 Display mode change control register 0x0000_0000 
    VIDCON1 0x0004 Specifies the video control 1 register 0x0000_0000 
    VIDTCON0 0x0010 Specifies the video time control 0 register. 0x0000_0000 
    VIDTCON1 0x0014 Specifies the video time control 1 register 0x0000_0000 
    VIDTCON2 0x0018 Specifies the video time control 2 register 0x0000_0000 
    VIDTCON3 0x001C Specifies the video time control 3 register 0x0000_0000 
    TRIGCON 0x01A4 Specifies the i80/RGB trigger control register 0x0000_0000 
    I80IFCONA0 0x01B0 Specifies i80 interface control 0 for main LDI. 0x0000_0000 
    I80IFCONA1 0x01B4 Specifies i80 interface control 0 for sub LDI. 0x0000_0000 
    I80IFCONB0 0x01B8 Specifies i80 interface control 1 for main LDI. 0x0000_0000 
    I80IFCONB1 0x01BC Specifies i80 interface control 1 for sub LDI. 0x0000_0000 
    LDI_CMDCON0 0x01D0 Specifies i80 interface LDI command control 0. 0x0000_0000 
    LDI_CMDCON1 0x01D4 Specifies i80 interface LDI command control 1. 0x0000_0000 
    SIFCCON0 0x01E0 Specifies LCD i80 system interface command control 0. 0x0000_0000 
    SIFCCON1 0x01E4 Specifies LCD i80 system interface command control 1. 0x0000_0000 
    SIFCCON2 0x01E8 Specifies LCD i80 system interface command control 2. 0x????_???? 
    CRCRDATA 0x0258 CRC read data 0x0000_0000 
    CRCCTRL 0x025C CRC control register 0x0000_0000 
    LDI_CMD0 0x0280 Specifies i80 interface LDI command 0. 0x0000_0000  
    						
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    Register Offset Description Reset Value 
    LDI_CMD1 0x0284 Specifies i80 interface LDI command 1. 0x0000_0000 
    LDI_CMD2 0x0288 Specifies i80 interface LDI command 2. 0x0000_0000 
    LDI_CMD3 0x028C Specifies i80 interface LDI command 3. 0x0000_0000 
    LDI_CMD4 0x0290 Specifies i80 interface LDI command 4. 0x0000_0000 
    LDI_CMD5 0x0294 Specifies i80 interface LDI command 5. 0x0000_0000 
    LDI_CMD6 0x0298 Specifies i80 interface LDI command 6. 0x0000_0000 
    LDI_CMD7 0x029C Specifies i80 interface LDI command 7. 0x0000_0000 
    LDI_CMD8 0x02A0 Specifies i80 interface LDI command 8. 0x0000_0000 
    LDI_CMD9 0x02A4 Specifies i80 interface LDI command 9. 0x0000_0000 
    LDI_CMD10 0x02A8 Specifies i80 interface LDI command 10. 0x0000_0000 
    LDI_CMD11 0x02AC Specifies i80 interface LDI command 11. 0x0000_0000 
     
      
    						
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    15.5.2 MIXER Register 
    15.5.2.1 VIDCON0 
     Base Address: 0x1440_0000 
     Address = Base Address + 0x0000, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31] –=Reserved (should be 0)=0=
    I80_EN=[30]=–=
    bnables=I80 interface.==
    0 = Disables=
    1 = Enables (i80 24-bit data=interface, SYS_ADD[1])=
    0=
    RSVD=[29:17]=–=Reserved (should be 0)=0=
    CLKVALUP=[16]=RW=
    Selects the CLKVAL_F update timing control.=
    0 = Always=
    1 = Start of a frame (only once per frame)=
    0=
    oSVa=[15:14]=–=Reserved=0=
    CLKVAL_F=[13:6]=RW=
    Determines the rates of VCLK and=CLKVAL[7:0].=
    VCLK = HCLK/(CLKVAi=+ 1),=where CLKVAL >= 1 =
    NOTE:=
     The maximum frequency of VCLK is 300 MHz.  
     CLKSEL_F register selects Video Clock Source. 
    0 
    VCLKFREE [5] RW 
    Controls VCLK Free Run (only valid at RGB IF mode). 
    0 = Normal mode (controls using ENVID) 
    1 = Free-run mode 
    0 
    RSVD [4:2] –=Should be 0=0x0=
    ENVIa=[1]=RW=
    Enables/disables=video output and logic.=
    0 = Disables=the video output and display=control signal=
    1 = Enables=the video output and display=control signal=
    0=
    ENVID_c=[0]=RW=
    Enables/disables=video output and logic at current 
    frame end.=
    0 = Disables=the video output and displays control 
    signal=
    1 = Enables=the video output and displays control 
    signal=
    NOTE:=When=this bit is set=to=ON=and OFc, the e=
    is Read and enables video=controller till the end of=
    current frame.=
    0=
    =====
    NOTE: Display ON: ENVID and ENVID_F are set to 1 
    Direct OFF: ENVID and ENVID_F are simultaneously set to 0 
    Per Frame OFF: ENVID_F is set to 0 and ENVID is set to 1 
     
    Caution: 1: When the display controller is turned-off by using Direct OFF, you cannot turn-on the display   
    						
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      controller without a reset. 
     
      
    						
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    15.5.2.2 VIDCON2 
     Base Address: 0x1440_0000 
     Address = Base Address + 0x0008, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:14] –=Reserved(should=be 0)=0=
    TVFORMATSEi=x13:12]=RW=
    Specifies the output format of YUV data.=
    00== Reserved= = = ==
    01 = Reserved=
    1x== YUV444=
    0=
    oSVa=[11:9]=–=Reserved=0=
    OrgYCbCr=x8]=RW=
    Specifies the order of YUV data.=
    0 = Y-CbCr==
    1 = CbCr-Y =
    0=
    YUVOrd=x7]=RW=
    Specifies the order of Chroma data.=
    0 = Cb-Cr==
    1 = Cr-Cb=
    0=
    oSVa=[6:5]=–=Reserved=0=
    WB_FRAME_SKIm=[4:0]=RW=
    Controls=the t B crame=pkip rate. The maximum=rate=
    is up to 1:30 xonly=where (VIDOUT[2:0] == 3’b100)].=
    00000 = No=skip (1:1)=
    00001 = Skip=rate = 1:2=
    00010 = Skip=rate = 1:3=
    …=
    11101 = Skip=rate = 1:30=
    1111x = Reserved=
    0=
    =
    = 
    						
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