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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-17  
14.5.1.10 SWAP_CFGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0028, Reset Value = 0x0 
Name Bit Type Description Reset Value 
RX_HWORD_SWAP [7] RW 0 = Off      
1 = Swap 0 
RX_BYTE_SW AP [6] RW 0 = Off        
1 = Swap 0 
RX_BIT_SW AP [5] RW 0 = Off      
1 = Swap 0 
RX_SW AP_EN [4] RW 
Swap enable 
0 = Normal      
1 = Swap 
0 
TX_HWORD_SWAP [3] RW 0 = Off        
1 = Swap 0 
TX_BYTE_SW AP [2] RW 0 = Off      
1 = Swap 0 
TX_BIT_SW AP [1] RW 0 = Off          
1 = Swap 0 
TX_SW AP_EN [0] RW 
Swap enable 
0 = Normal      
1 = Swap 
0 
NOTE: Data size must be larger than swap size.
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-18  
14.5.1.11 FB_CLK_SELn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x002C, Reset Value = 0x0 
Name Bit Type Description Reset Value 
FB_CLK_SEL [1:0] RW 
In master mode, SPI uses a clock which is 
feedback from the SPICLK. The feedback clock is 
intended to capture the slave Tx signal safely that 
can be lagged if slave device is very far. 
There are four kinds of feedback clocks that 
experience different path delays. This register 
selects one of the feedback clocks to use.  
NOTE: This register value is meaningless when 
SPI operates in slave mode. 
00 = SPICLK bypass (do not use feedback clock) 
01 = A feedback clock with 90 degree phase 
lagging 
10 = A feedback clock with 180 degree phase 
lagging 
11 = A feedback clock with 270 degree phase 
lagging 
90 degree phase lagging means 5 ns delay in 50 
MHz operating frequency. 
0x0 
 
 
14.5.1.12 PAD Driving Strength 
PAD driving strength of SPI is controlled by setting drive strength control register in GPIO SPI related SFRs are: 
 GPA2DRV (for SPI port 0, 1)  
 GPB1DRV (for SPI port 2)  
 GPF1DRV (for ISP-SPI port 0)  
 GPE0DRV and GPF0DRV (for ISP-SPI port 1)
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Exynos 5250_UM 15 Display Controller 
 15-1  
15 Display Controller 
15.1 Overview 
The display controller consists of logic to transfer image data from a local bus or a video buffer (located in system 
memory) to an internal LCD driver interface. The LCD driver interface supp15-1orts three kinds of interfaces: 
 RGB interface 
 Indirect-i80 interface 
 YUV interface for write-back  
NOTE: RGB interface and Indirect-i80 interface are not connected to LCD driver directly. They are connected to other IPs 
internally. 
 
The display controller uses up to five overlay image windows that support various color formats, such as 256 level 
alpha blending, color key, x-y position control, soft scrolling, variable window size, and so on. 
The display controller supports RGB (1-bpp to 24-bpp) and YCbCr 4:4:4 (only local bus) color formats. It is 
programmed to support different requirements on screen, which are related to the number of horizontal and 
vertical pixels, data line width for the data interface, interface timing, and refresh rate.  
The display controller transfers the video data and generates essential control signals, such as RGB_VSYNC, 
RGB_HSYNC, RGB_VCLK, RGB_VDEN and SYS_CS0, SYS_CS1, SYS_W E. Additionally, the display controller 
contains data ports for video data (RGB_VD[23:0], SYS_VD and WB_YUV), as illustrated in Figure 15-1. 
 
    Figure 15-1   Block Diagram of Display Controller PIXSCHED
(5-ch
.)
Blender
(5-ch
. Overlay
)
VTIME_RGB_TVVTIME_i80
AHBSlave I/F
Local
I/F
(3-ch.)
FIFO
(5-ch.)
ARBITER + DMA
FIFO I/F(8bit * 3)
AXIMaster I/F
Color GainRGB I/F
I80 I/F
RGB_VD(Internal only)
SYS_VD(Internal only)
MIX_SFR
ENH_SFR
LCDIF_SFR
YUV IFWB_YUV(Internal only)
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Exynos 5250_UM 15 Display Controller 
 15-2  
15.2 Features 
Features of the display controller are: 
Table 15-1 describes the features of display controller. 
Table 15-1   Features of the Display Controller 
Bus Interface AMBA AXI 64-bit Master/AHB 32-bit Slave 
Local Video Bus (YCbCr/RGB) 
Video Output Interface 
RGB Interface (24-bit Parallel) (Not used in Exynos 5250) 
Indirect i80 interface (Not used in Exynos 5250) 
Write-back interface (YUV444 24-bit) 
Dual Output Mode Supports RGB and Write-back 
Supports i80 and WriteBack 
PIP (OSD) function 
Supports 8-bpp (bit per pixel) palletized color 
Supports 16-bpp non-palletized color 
Supports unpacked 18-bpp non-palletized color 
Supports unpacked 24-bpp non-palletized color 
Supports X, Y indexed position 
Supports 8-bit Alpha blending (Plane/Pixel) 
CSC (Internal) RGB to YCbCr (4:2:2)  
Source format 
Window 0  
Supports 1, 2, 4, or 8-bpp palletized color 
Supports 16, 18, or 24-bpp non-palletized color 
Supports YUV444/RGB (8:8:8) local input from Local Bus  
Window 1  
Supports 1, 2, 4, or 8-bpp palletized color 
Supports 16, 18, or 24-bpp non-palletized color 
Supports YUV444/RGB (8:8:8) local input from Local Bus 
Window 2 
Supports 1, 2, 4, or 8-bpp palletized color 
Supports 16, 18, or 24-bpp non-palletized color 
Supports YUV444/RGB (8:8:8) local input from Local Bus 
Window 3/4 
Supports 1, 2, 4, or 8-bpp palletized color 
Supports 16, 18, or 24-bpp non-palletized color 
Configurable Burst Length Programmable 4/8/16 Burst DMA 
Palette 
Window 0/1/2/3/4  
Supports 256  32 bits palette memory (5ea: one palette memory for each 
window) 
Soft Scrolling Horizontal = 1 byte resolution 
Vertical = 1 pixel resolution 
Virtual Screen Virtual image can contain up to 16 MB image size 
Each window can contain its own virtual area
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Exynos 5250_UM 15 Display Controller 
 15-3  
Transparent Overlay Supports Transparent Overlay 
Color Key (Chroma Key) Supports Color Key function 
Supports color key and blending function simultaneously 
Image Enhancement Supports color gain control
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Exynos 5250_UM 15 Display Controller 
 15-4  
15.3 Functional Description of Display Controller 
15.3.1 Sub-Block 
The display controller consists of:  
 VSFR: To configure the display controller, the VSFR contains i80 command register set (12 registers) and five 
256  32 palette memories.  
 VDMA: It is a dedicated display DMA that transfers video data in frame memory to VPRCS. By using this 
DMA, you can display video data on screen without CPU intervention. 
 VPRCS: It receives video data from VDMA, converts the video data into a suitable data format, and sends it to 
display link through RGB_VD. For example, the video data format is 8-bit per pixel mode (8-bpp mode) or 16-
bit per pixel mode (16-bpp mode). 
 VTIME: It consists of programmable logic to support the variable requirement of interface timing and rates that 
is found in various LCD drivers. The VTIME block generates RGB_VSYNC, RGB_HSYNC, RGB_VCLK, 
RGB_VDEN, VEN_VSYNC, VEN_HSYNC, VEN_FIELD, VEN_HREF and SYS_CS0, SYS_CS1, SYS_WE, 
and so on.  
 Video clock generator 
 
15.3.2 Data Flow 
FIFO is located in the VDMA. When FIFO is empty or partially empty, the VDMA requests data from frame 
memory based on the burst memory transfer mode. The data transfer rate determines the size of FIFO. 
The display controller contains five FIFOs (three local FIFOs and two DMA FIFOs), to support the overlay window 
display mode. You should use a FIFO for a screen display mode. 
VPRCS obtains data from FIFO. It performs blending, image enhancing, scheduling, and overlay functions for final 
image data. VPRCS can overlay up to five window images. It can blend a smaller or same sized window image 
with the main window image that contains programmable alpha blending color (chroma) key function. 
VDMA consists of:  
 Five DMA channels (Ch0 to Ch4)  
 Three local input interfaces  
The Color Space Conversion (CSC) block converts Hue (YCbCr, local input only) data to RGB data to perform 
blending. The alpha values written in SFR determine the level of blending. Data from output buffer appears in the 
Video Data Port.
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Exynos 5250_UM 15 Display Controller 
 15-5  
Figure 15-2 illustrates the data flow from system bus to output buffer. 
 
    Figure 15-2   Block Diagram of the Data Flow 
 Local Path 0
(YUV/RGB)
Local Path 1
(YUV/RGB)
Local Path 2
(YUV/RGB)
LIMITERLIMITERLIMITER
CSCCSCCSC
WIN0 (RGB)WIN1 (RGB)WIN2 (RGB)WIN3 (RGB)WIN4 (RGB)
BlendingColor Keying
BlendingColor Keying
BlendingColor Keying
BlendingColor Keying
Color Gain (RGB)
AXI
RGBe
YUV 444/ RGB888YUV 444/ RGB888YUV 444/ RGB888
RGB888RGB888RGB888RGB888RGB888
RGB888
RGB888
RGB888
RGB888
RGB888
RGBb
RGB888
CH-RGB0CH-RGB1
RGBRGB
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Exynos 5250_UM 15 Display Controller 
 15-6  
15.3.2.1 Interface 
The display controller supports three types of interfaces: 
 Conventional RGB: It uses RGB data, vertical/horizontal sync, data valid signal, and data sync clock. 
 Indirect i80: It uses address, data, chip select, read/ write control, and register/status indicating signal. The 
LCD driver using i80 Interface contains a frame buffer and can self-refresh, so the display controller updates 
one still image by writing only one time to the LCD 
 FIFO: It is used to send YUV444 data to local path for writeback. 
Figure 15-3 illustrates the block diagram of the interface. 
 
    Figure 15-3   Block Diagram of the Interface 
 
 (24 bit)
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Exynos 5250_UM 15 Display Controller 
 15-7  
15.3.3 Color Data  
15.3.3.1 RGB Data Format 
The display controller requests for the specified memory format of frame buffer.  
These tables describe examples of each display mode: 
 
15.3.3.1.1 25-bpp Display (A888) 
 
NOTE:  
1. AEN = specifies the transparency selection bit 
  AEN: 0 = selects ALPHA0 
  AEN: 1 = selects ALPHA1 
  When the per-pixel blending is set, it blends with the alpha value that AEN selects. 
  SFR selects the alpha value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, and ALPHA1_B.  
  Refer to SFR section for more information. 
2. D[23:16] = Red data, D[15:8] = Green data, and D[7:0] = Blue data.
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Exynos 5250_UM 15 Display Controller 
 15-8  
15.3.3.1.2 32-bpp (8888) Mode  
Pixel data contains alpha value. 
 
 
  000H
008H
010H
…
D[63:56]D[55:32]
ALPHA valueP1
ALPHA valueP3
ALPHA valueP5
( BYSWP=0, HWSWP=0, WSWP=0 )
( BYSWP=0, HWSWP=0, WSWP=1 )
ALPHA valueP2
ALPHA valueP4
ALPHA valueP6
D[31:24]D[23:0]
000H
008H
010H
…
ALPHA valueP2
ALPHA valueP4
ALPHA valueP6
ALPHA valueP1
ALPHA valueP3
ALPHA valueP5
D[63:56]D[55:32]D[31:24]D[23:0]
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