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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-109  
15.5.2.64 BLENDEQ3 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x024C, Reset Value = 0x0000_00C2 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x000=
Q_FUNC_F=[21:18]=RW=
Specifies the constant that is used in alphaB=(alpha=
value of background (1)) 
0000 = 0 (zero) 
0001 = 1 (maximum) 
0010 = alphaA (2) (alpha value of foreground (1)) 
0011 = 1 –=alphaA=
0100 = alphaB =
0101 = 1=–=alphaB=
0110 = ALPHA0=
0111 = Reserved=
100x = Reserved=
1010 = A (foreground color data)=
1011 = 1=–=A=
1100 = B (background color data)=
1101 = 1=–=B=
111x = Reserved=
0x0=
oSVa=[17:16]=–=oeserved=00=
P_FUNC_F=[15:12]=RW=
Specifies the constant that is used in alpha.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information).=
0x0=
oSVa=[11:10]=–=oeserved=00=
B_FUNC_F=[9:6]=RW=
Specifies the constant that is used in B.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information).=
0x3=
oSVa=[5:4]=–=oeserved=00=
A_FUNC_F=[3:0]=RW=
Specifies the constant that is used in A.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information).=
0x2=
NOTE: Refer to Figure 15-5, Blending Equation for more information. 
1. Background = Window 012, foreground = Window 3 (in blend equation 3) 
2. BPPMODE_F, BLD_PIX, ALPHA_SEL at WINCONx, and WxPAL at WPALCON decides alphaA and alphaB.
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Exynos 5250_UM 15 Display Controller 
 15-110  
15.5.2.65 BLENDEQ4 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0250, Reset Value = 0x0000_00C2 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x000=
Q_FUNC_F=[21:18]=RW=
Specifies the constant that is used in alphaB=(alpha=
value of background (1)) 
0000 = 0 (zero) 
0001 = 1 (maximum) 
0010 = alphaA (2) (alpha value of foreground (1)) 
0011 = 1 –=alphaA=
0100 = alphaB =
0101 = 1=–=alphaB=
0110 = ALPHA0=
0111 = Reserved=
100x = Reserved=
1010 = A (foreground color data)=
1011 = 1=–=A=
1100 = B (background color data)=
1101 = 1=–=B=
111x = Reserved=
0x0=
oSVa=[17:16]=–=oeserved=00=
P_FUNC_F=[15:12]=RW=
Specifies the=constant that is used in alpha.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information).=
0x0=
RSVD=[11:10]=–=oeserved=00=
B_FUNC_F=[9:6]=RW=
Specifies the=constant that is used in B.=
The values are same as=described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information).=
0x3=
RSVD=[5:4]=–=oeserved=00=
A_FUNC_F=[3:0]=RW=
Specifies the=constant that is used in A.=
The values are same as described in Q_FUNC_F field.=
(Refer to=COEF_Q=for more information).=
0x2=
NOTE: Refer to Figure 15-5, Blending equation, for more information. 
1. Background = Window 0123, foreground = Window 4 (in blend equation 4) 
2. BPPMODE_F, BLD_PIX, ALPHA_SEL at WINCONx, and WxPAL at WPALCON decides alphaA and alphaB.
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Exynos 5250_UM 15 Display Controller 
 15-111  
15.5.2.66 BLENDCON 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0260, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x000=
BLEND_NEt=[0]=RW=
Specifies the=width=of alpha value.=
0 = 4-bit alpha value =
1 = 8-bit alpha value =
0x0=
=
=
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Exynos 5250_UM 15 Display Controller 
 15-112  
15.5.2.67 W013DSTERECON 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0254, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:19] –=Reserved==0=
WIDTe=[18:7]=RW=Specifies the Width of=frame image. W IDTH = image width=
–=1=0=
MERGE_EN=[6]=RW=Specifies the enable signal for ieft frame and Right frame 
merging block.=0=
A_L_FIRST=[5]=RW=Specifies the ieft cirst signal for Alpha data.=0=
R_L_FIRST=[4]=RW=Specifies the ieft cirst signal for oed data.=0=
G_L_FIRST=[3]=RW=Specifies the ieft cirst signal for dreen data.=0=
B_L_FIRST=[2]=RW=Specifies the ieft cirst signal for Blue data.=0=
INTERPOL_EN=[1]=RW=Specifies the fnterpolation enable signal.=0=
LINE_SWAm=[0]=RW=Specifies the iine pwapping enable signal.=0=
=
15.5.2.68 W233DSTEREOCON 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0258, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:19] –=Reserved==0=
WIDTe=[18:7]=RW=Specifies the Width of=frame image.=
WIDTH = image width –=1=0=
MERGE_EN=[6]=RW=Specifies the enable signal for L frame and R frame 
merging block.=0=
A_L_FIRST=[5]=RW=Specifies the ieft cirst signal for Alpha data.=0=
R_L_FIRST=[4]=RW=Specifies the ieft cirst signal for oed data.=0=
G_L_FIRST=[3]=RW=Specifies the ieft cirst signal for dreen data.=0=
B_L_FIRST=[2]=RW=Specifies the ieft cirst signal for Blue data.=0=
INTERPOL_EN=[1]=RW=Specifies the fnterpolation enable signal.=0=
LINE_SWAm=[0]=RW=Specifies the iine pwapping enable signal.=0=
=
=
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Exynos 5250_UM 15 Display Controller 
 15-113  
15.5.2.69 SHD_VIDW0nADD0 (n = 0 to 4) 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x40A0, 0x40A8, 0x40B0, 0x40B8, 0x40C0, Reset Value = 0x0000_0000 
(SHD_VIDW00ADD0, SHD_VIDW01ADD0, SHD_VIDW02ADD0, SHD_VIDW03ADD0, SHD_VIDW04ADD0) 
Name Bit Type Description Reset Value 
VBASEU_F [31:0] R Specifies A[31:0] of the start address for Video Frame 
Buffer (Shadow). 0 
 
15.5.2.70 SHD_VIDW0nADD1 (n = 0 to 4) 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x40D0, 0x40D8, 0x40D0, 0x40D8, 0x40D0, Reset Value = 0x0000_0000 
(SHD_VIDW00ADD1, SHD_VIDW01ADD1, SHD_VIDW02ADD1, SHD_VIDW03ADD1, SHD_VIDW04ADD1) 
Name Bit Type Description Reset Value 
VBASEL_F [31:0] R 
Specifies A[31:0] of the end address for Video Frame 
Buffer.  
VBASEL = VBASEU + (PAGEWIDTH + OFFSIZE)  
(LINEVAL + 1) 
0x0 
 
15.5.2.71 SHD_VIDW0nADD2 (n = 0 to 4) 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x40A0, 0x40A8, 0x40B0, 0x40B8, 0x40C0, Reset Value = 0x0000_0000 
(SHD_VIDW00ADD2, SHD_VIDW01ADD2, SHD_VIDW02ADD2, SHD_VIDW03ADD2, SHD_VIDW04ADD2) 
Name Bit Type Description Reset Value 
OFFSIZE_F_E [27] R Specifies the extended virtual screen Offset Size 
(number of byte). 0 
PAGEWIDTH_F_E [26] R Specifies the extended virtual screen Page W idth 
(number of byte). 0 
OFFSIZE_F [25:13] R Specifies the virtual screen Offset Size (number of byte 
- Shadow). 0 
PAGEWIDTH_F [12:0] R 
Specifies the virtual screen Page W idth (number of 
byte). 
This value defines the width of view port in the frame 
(Shadow). 
0
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Exynos 5250_UM 15 Display Controller 
 15-114  
15.5.3 Palette Memory (PalRam) 
15.5.3.1 Win0 PalRam (not SFR) 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x2400 to 0x27FC, Reset Value = 0x0000_0000 
Register Offset Type Description Reset Value 
00 0x2400 
(0x0400) RW Specifies the Window 0 Palette entry 0 address. Undefined 
01 0x2404 
(0x0404) RW Specifies the Window 0 Palette entry 1 address. Undefined 
: : : : : 
FF 0x27FC 
(0x07FC) RW Specifies the Window 0 Palette entry 255 address. Undefined 
 
15.5.3.2 Win1 PalRam (not SFR) 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x2800 to 0x2BFC, Reset Value = 0x0000_0000 
Register Offset Type Description Reset Value 
00 0x2800 
(0x0800) RW Specifies the Window 1 Palette entry 0 address. Undefined 
01 0x2804 
(0x0804) RW Specifies the Window 1 Palette entry 1 address. Undefined 
: : : : : 
FF 0x2BFC 
(0x0BFC) RW Specifies the Window 1 Palette entry 255 address. Undefined
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Exynos 5250_UM 15 Display Controller 
 15-115  
15.5.3.3 Win2 PalRam (not SFR) 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x2C00 to 0x2FFC, Reset Value = 0x0000_0000 
Register Offset Type Description Reset Value 
00 0x2C00 RW Specifies the Window 2 Palette entry 0 address. Undefined 
01 0x2C04 RW Specifies the Window 2 Palette entry 1 address. Undefined 
: : : : : 
FF 0x2FFC RW Specifies the Window 2 Palette entry 255 address. Undefined 
 
15.5.3.4 Win3 PalRam (not SFR) 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x3000 to 0x33FC, Reset Value = 0x0000_0000 
Register Offset Type Description Reset Value 
00 0x3000 RW Specifies the Window 3 Palette entry 0 address. Undefined 
01 0x3004 RW Specifies the Window 3 Palette entry 1 address. Undefined 
: : : : : 
FF 0x33FC RW Specifies the Window 3 Palette entry 255 address. Undefined
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Exynos 5250_UM 15 Display Controller 
 15-116  
15.5.4 Enhancer Register 
15.5.4.1 COLORGAINCON 
 Base Address: 0x1441_0000 
 Address = Base Address + 0x01C0, Reset Value = 0x1004_0100 
Name Bit Type Description Reset Value 
RSVD [31:30] –=Reserved=0=
CG_RGAIN=[29:20]=RW=
Specifies=the Color=dain value of Red=data (maximum=
4, 8-bit resolution).=
0h000 = 0=
0h001 = 0.00390625 (1/256)=
0h002 = 0.0078125 (2/256)=
…=
0h0FF = 0.99609375 (255/256)=
0h100 = 1.0=
…=
0x3FF = 3.99609375 (maximum)=
0x100=
CG_GGAIN=[19:10]=RW=
Specifies the Color=dain value of Green data 
(maximum=4, 8-bit resolution).=
0h000 = 0=
0h001 = 0.00390625 (1/256)=
0h002 = 0.0078125 (2/256)=
…=
0h0FF = 0.99609375 (255/256)=
0h100 = 1.0=
…=
0x3FF = 3.99609375 (maximum)=
0x100=
CG_BGAIN=[9:0]=RW=
Specifies the Color=dain value of Blue data (maximum=
4, 8-bit resolution).=
0h000 = 0=
0h001 = 0.00390625 (1/256)=
0h002 = 0.0078125 (2/256)=
…=
0h0FF = 0.99609375 (255/256)=
0h100 = 1.0=
…=
0x3FF = 3.99609375 (maximum)=
0x100=
=
=
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Exynos 5250_UM 15 Display Controller 
 15-117  
15.5.5 LCDIF Register 
15.5.5.1 VIDOUT_CON 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0=
VIDOUT_Um=[16]=RW=
Selects VIDOUT_F update timing control.=
0 = Always=
1 = Start of a frame (only once per frame)=
0=
RSVD=[15:11]=–=Reserved=0=
VIDOUT_F=[10:8]=RW=
aetermines the output format of Video Controller.=
000== RGB interface=
001== Reserved=
010== Indirect I80=interface=for LDI0=
011== Indirect I80=interface=for LDI1=
100 = WB=interface=and  = RGB interface=
101 = Reserved=
110 = WB Interface and i80=interface=for LDI0=
111 = WB Interface and i80=interface=for LDI1=
0=
RSVD=[7:0]=RW=Reserved=0=
=
=
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Exynos 5250_UM 15 Display Controller 
 15-118  
15.5.5.2 VIDCON1 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x0004, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
LINECNT (read only) [26:16] R Specifies the status of the Line Counter (Read-only). 
Count upwards from 0 to LINEVAL 0 
FSTATUS [15] R 
Specifies the Field Status (Read-only). 
0 = ODD field  
1 = EVEN field 
0 
VSTATUS [14:13] R 
Specifies the Vertical Status (Read-only). 
00 = VSYNC  
01 = BACK Porch  
10 = ACTIVE  
11 = FRONT Porch 
0 
RSVD [12:11] –=Reserved=0=
FIXVCLh=[10:9]=RW=
Specifies the VCLK hold scheme at data=under-flow.=
00 = VCLK hold=
01 = VCLK running=
11 = VCLK running and VDEN disable=
0=
RSVD=[8]=–=Reserved=0=
IVCLh=[7]=RW=
Controls the polarity of the VCLK active edge.=
0 = Fetches video data at VCLK falling edge=
1 = Fetches video data at VCLK rising edge=
0=
IHSYNC=[6]=RW=
Specifies the pulse polarity=of HSYNC.=
0 = Normal =
1 = fnverted=
0=
IVSYNC=[5]=RW=
Specifies the pulse polarity of VSYNC.=
0 = Normal =
1 = fnverted=
0=
IVDEN=[4]=RW=
Specifies the signal polarity=of VDEN.=
0 = Normal =
1 = fnverted=
0=
RSVD=x3:0]=–=Reserved=0x0=
=
=
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