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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-65  
5.9.1.22 APLL_CON0_L4 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1110, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
5.9.1.23 APLL_CON0_L3 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1114, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-66  
5.9.1.24 APLL_CON0_L2 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1118, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
5.9.1.25 APLL_CON0_L1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x111C, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-67  
5.9.1.26 APLL_CON1_L8 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1200, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
AFC_ENB [31] RW 
Decides whether AFC is enabled or not (Active-
low) 
0 = Enables AFC 
1 = Disables AFC 
0x0 
RSVD [30:5] –=Reserved=0x0=
AFC=[4:0]=RW=AFC value=0x0=
=
5.9.1.27 APLL_CON1_L7 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1204, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
AFC_ENB [31] RW 
Decides whether AFC is enabled or not (Active-
low) 
0 = Enables AFC 
1 = Disables AFC 
0x0 
RSVD [30:5] –=Reserved=0x0=
AFC=[4:0]=RW=AFC value=0x0=
=
5.9.1.28 APLL_CON1_L6 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1208, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
AFC_ENB [31] RW 
Decides whether AFC is enabled or not (Active-
low) 
0 = Enables AFC 
1 = Disables AFC 
0x0 
RSVD [30:5] –=Reserved=0x0=
AFC=[4:0]=RW=AFC value=0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-68  
5.9.1.29 APLL_CON1_L5 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x120C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
AFC_ENB [31] RW 
Decides whether AFC is enabled or not (Active-
low) 
0 = Enables AFC 
1 = Disables AFC 
0x0 
RSVD [30:5] –=Reserved=0x0=
AFC=[4:0]=RW=AFC value=0x0=
=
5.9.1.30 APLL_CON1_L4 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1210, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
AFC_ENB [31] RW 
Decides whether AFC is enabled or not (Active-
low) 
0 = Enables AFC 
1 = Disables AFC 
0x0 
RSVD [30:5] –=Reserved=0x0=
AFC=[4:0]=RW=AFC value=0x0=
=
5.9.1.31 APLL_CON1_L3 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1214, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
AFC_ENB [31] RW 
Decides whether AFC is enabled or not (Active-
low 
0 = Enables AFC 
1 = Disables AFC 
0x0 
RSVD [30:5] –=Reserved=0x0=
AFC=[4:0]=RW=AFC value=0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-69  
5.9.1.32 APLL_CON1_L2 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1218, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
AFC_ENB [31] RW 
Decides whether AFC is enabled or not (Active-
low) 
0 = Enables AFC 
1 = Disables AFC 
0x0 
RSVD [30:5] –=Reserved=0x0=
AFC=[4:0]=RW=AFC value=0x0=
=
5.9.1.33 APLL_CON1_L1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x121C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
AFC_ENB [31] RW 
Decides whether AFC is enabled or not (Active-
low) 
0 = Enables AFC 
1 = Disables AFC 
0x0 
RSVD [30:5] –=Reserved=0x0=
AFC=[4:0]=RW=AFC value=0x0=
=
5.9.1.34 MPLL_LOCK 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4000, Reset Value = 0x0000_0FFF 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0x0=
PLL_LOCKTIME=[19:0]=RW=
Required period=(in cycles) to generate a stable=
clock output=
The maximum lock time can be up to 250= PDIV 
cycles of PLLs FIN (XXTI). 
0xF_FFFF
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Exynos 5250_UM 5 Clock Controller 
 5-70  
5.9.1.35 MPLL_CON0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4100, Reset Value = 0x00C8_0601 
Name Bit Type Description Reset Value 
ENABLE [31] RW 
PLL Enable control 
0 = Disables 
1 = Enables 
0x0 
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL Locking indication=
0 = Unlocks=
1 = Locks=
0x0=
RSVD=x28]=–=Reserved=0x0=
FSEL=[27]=RW=
Monitoring Frequency Select pin=
0 = FVCO_OUT = FREc=
1 = FVCO_OUT = FVCl=
0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=PLL M Divide value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=PLL P Divide value=0xS=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=PLL S Divide value=0x1=
=
The reset value of=MPLL_CON0=generates 400=MHz output clock=for the input clock frequency of=24=MHz.=
Equation to calculate the=output frequency=is:=
 FOUT = MDIV  FIN/(PDIV  2SDIV) 
MDIV, PDIV, SDIV for MPLL should conform to these conditions: 
 PDIV: 1  PDIV  63 
 MDIV: 64  MDIV  1023 
 SDIV: 0  SDIV  5 
 Fref (= FIN/PDIV): 2 MHz  Fref  12 MHz 
 FVCO (= MDIV  FIN/PDIV): 700 MHz  FVCO  1600 MHz 
 FOUT: 21.9 MHz  FOUT  1600 MHz
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Exynos 5250_UM 5 Clock Controller 
 5-71  
Do not set the value of PDIV[5:0] or MDIV[9:0] to all zeros 
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL for more information on recommended PMS 
values. 
SDIV[2:0] controls division ratio of Scaler as described in Table 5-15.
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Exynos 5250_UM 5 Clock Controller 
 5-72  
5.9.1.36 MPLL_CON1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4104, Reset Value = 0x0020_3800 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x0=
DCC_ENB=[21]=RW=
Enables Duty Cycle Corrector==
(only for monitoring)=
0 = Enables DCC =
1 = Disables=DCC =
0x1=
AFC_ENB=x20]=RW=
Decides=whether AFC is enabled or not (Active-
low)=
0 = Enables AFC =
1 = Disables AFC==
0x0=
RSVD=x19:17]=–=Reserved=0x0=
FEED_EN=[16]=RW=Enable pin for FEED_OUT (Active-high)=0x0=
LOCK_CON_OUT=[15:14]=RW=Lock detector setting of the output margin=0x0=
LOCK_CON_IN=[13:12]=RW=Lock detector setting of the input=margin=0x3=
LOCK_CON_DLY=[11:8]=RW=Lock detector setting of the detection resolution=0x8=
RSVD=[7:5]=–=Reserved=0x0=
EXTAFC=[4:0]=RW=Enable pin for FVCO_OUT (Active-high)=0x0=
=
AFC automatically selects adaptive frequency curve of VCO using switched=current bank for:=
 Wide range  
 High phase noise (or Jitter)    
 Fast lock time 
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on 
recommended AFC_ENB and EXTAFC values.
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Exynos 5250_UM 5 Clock Controller 
 5-73  
5.9.1.37 CLK_SRC_CORE0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4200, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0x0=
MUX_RSVD3=
_CORb_SEL=x19:1S]=RW=
Control MUu_RSVD3_CORb, the source clock of 
RSVD3_CORE=
0000 = XXTf=
0001 ==XXTI=
0010 = SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 = SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 = SCLK_MPLL=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
Others===Reserved=
0x0=
RSVD=x15:0]=–=Reserved=0x0=
=
5.9.1.38 CLK_SRC_CORE1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4204, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:9] –=Reserved=0x0=
MUX_MPLL_SEL=x8]=RW=
Control MUu_MPLi=
0 = XXTI=
1 = MPLi_FOUT_RGT=
0x0=
RSVD=[7:0]=–=Reserved=0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-74  
5.9.1.39 CLK_SRC_MASK_CORE 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4300, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
RSVD3_CORE_M
ASh=x16]=RW=
Mask=output clock of MUu_RSVD3_CORb=
0 = Masks MUX_RSVD3_CORE=
1 = Unmasks MUX_RSVD3_CORE=
0x0=
RSVD=[15:0]=–=Reserved=0x0=
=
5.9.1.40 CLK_MUX_STAT_CORE1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4404 Reset Value = 0x0000_0100 
Name Bit Type Description Reset Value 
RSVD [31:11] –=Reserved=0x0=
MPLL_SEL=x10:8]=o=
Selection signal status of MUX_MPLi=
001 = XXTI=
010 = MPLL_FOUT_RGT=
1xx = On changing=
0x1=
RSVD=x7:0]=–=Reserved=0x0=
=
=
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