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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-33  
Name Bit Type Description Reset Value 
0 = Masks 
1 = Enables
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Exynos 5250_UM 7 Interrupt Combiner 
 7-34  
7.5.1.26 IECR6 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0064, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0x0=
EINTx7]=[25]=RW=Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
EINTx6]=[24]=RW=0=
RSVD=x23:18]=–=Reserved=0x0=
EINTx5]=x17]=RW=Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
EINTx4]=x16]=RW=0=
RSVD=x15:12]=–=Reserved=0x0=
MCT_G3=[11]=RW=Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
MCT_G2=[10]=RW=0=
EINTx3]=x9]=RW=0=
EINTx2]=x8]=RW=0=
RSVD=x7]=–=Reserved=0x0=
pYSMMU_G2D[1]=xS]=RW=Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0=
pYSMMU_G2D[0]=x5]=RW=0=
RSVD=x4:3]=–=0=
pYSMMU_FIMC_LITE1[1]=x2]=RW=0=
pYSMMU_FIMC_LITE1[0]=x1]=RW=0=
EINTx1]=x0]=RW=0=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-35  
Name Bit Type Description Reset Value 
0 = Masks 
1 = Enables
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Exynos 5250_UM 7 Interrupt Combiner 
 7-36  
7.5.1.27 ISTR6 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0068, Reset Value = Undefined  
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=–=
EINTx7]=[25]=o=Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx6]=[24]=o=–=
RSVD=x23:18]=–=Reserved=–=
EINTx5]=x17]=o=Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx4]=x16]=o=–=
RSVD=x15:12]=–=Reserved=–=
MCT_G3=[11]=o=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
MCT_G2=[10]=o=–=
EINTx3]=x9]=o=–=
EINTx2]=x8]=o=–=
RSVD=x7]=–=Reserved=–=
pYSMMU_G2D[1]=xS]=o=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
pYSMMU_G2D[0]=x5]=o=–=
RSVD=x4:3]=–=–=
pYSMMU_FIMC_LITE1[1]=x2]=o=–=
pYSMMU_FIMC_LITE1[0]=x1]=o=–=
EINTx1]=x0]=o=–=
=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-37  
7.5.1.28 IMSR6 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x006C, Reset Value = Undefined  
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=–=
EINTx7]=[25]=o=Masked interrupt=pending status=
If the corresponding interrupt enable bit is=0,=
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx6]=[24]=o=–=
RSVD=x23:18]=–=Reserved=–=
EINTx5]=x17]=o=Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx4]=x16]=o=–=
RSVD=x15:12]=–=Reserved=–=
MCT_G3=[11]=o=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
-=
MCT_G2=[10]=o=-=
EINTx3]=x9]=o=–=
EINTx2]=x8]=o=–=
RSVD=x7]=–=Reserved=–=
pYSMMU_G2D[1]=xS]=o=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
pYSMMU_G2D[0]=x5]=o=–=
RSVD=x4:3]=–=–=
pYSMMU_FIMC_LITE1[1]=x2]=o=–=
pYSMMU_FIMC_LITE1[0]=x1]=o=–=
EINTx1]=x0]=o=–=
=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-38  
7.5.1.29 IESR7 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0070, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0x0=
EINTx15]=[25]=RW=
Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
EINTx14]=[24]=RW=0=
RSVD=x23:18]=–=Reserved=0x0=
EINTx13]=x17]=RW=
Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set=to1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
EINTx12]=x16]=RW=0=
RSVD=x15:10]=–=Reserved=0x0=
EINTx11]=x9]=RW=
Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit.=
0== Masks=
1===Enables=
0=
EINTx10]=[8]=RW=0=
RSVD=x7:2]=–=Reserved=0x0=
EINTx9]=x1]=RW=
Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-39  
Name Bit Type Description Reset Value 
EINT[8] [0] RW 
0 = Does not change the current setting 
1 = Sets the interrupt enable bit to 1 
Read 
The current interrupt enable bit. 
0 = Masks 
1 = Enables 
0
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Exynos 5250_UM 7 Interrupt Combiner 
 7-40  
7.5.1.30 IECR7 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0074, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0x0=
EINTx15]=[25]=RW=
Clear the corresponding interrupt enable bit to=
0. If the=interrupt enable bit is cleared, the=
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
EINTx14]=[24]=RW=0=
RSVD=x23:18]=–=Reserved=0x0=
EINTx13]=x17]=RW=
Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
EINTx12]=x16]=RW=0=
RSVD=x15:10]=–=Reserved=0x0=
EINTx11]=x9]=RW=
Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
EINTx10]=[8]=RW=0=
RSVD=x7:2]=–=Reserved=0x0=
EINTx9]=x1]=RW=
Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-41  
Name Bit Type Description Reset Value 
EINT[8] [0] RW 
0 = Does not change the current setting 
1 = Clears the interrupt enable bit to 0 
Read 
The current interrupt enable bit. 
0 = Masks 
1 = Enables 
0
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Exynos 5250_UM 7 Interrupt Combiner 
 7-42  
7.5.1.31 ISTR7 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0078, Reset Value = Undefined  
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=–=
EINTx15]=[25]=o=Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx14]=[24]=o=–=
RSVD=x23:18]=–=Reserved=–=
EINTx13]=x17]=o=Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx12]=x16]=o=–=
RSVD=x15:10]=–=Reserved=–=
EINTx11]=x9]=o=Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx10]=[8]=o=–=
RSVD=x7:2]=–=Reserved=–=
EINTx9]=x1]=o=Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx8]=[0]=o=–=
=
=
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