Samsung Exynos 5 User Manual
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Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-35 Register Offset Description Reset Value PWR_CTRL2 0x1024 Power Control register 0x0000_0000 RSVD 0x1028 to 0x10FC Reserved Undefined APLL_CON0_L8 0x1100 APLL Control (performance level-8) 0x00C8_0301 APLL_CON0_L7 0x1104 APLL Control (performance level-7) 0x00C8_0301 APLL_CON0_L6 0x1108 APLL Control (performance level-6) 0x00C8_0301 APLL_CON0_L5 0x110C APLL Control (performance level-5) 0x00C8_0301 APLL_CON0_L4 0x1110 APLL Control (performance level-4) 0x00C8_0301 APLL_CON0_L3 0x1114 APLL Control (performance level-3) 0x00C8_0301 APLL_CON0_L2 0x1118 APLL Control (performance level-2) 0x00C8_0301 APLL_CON0_L1 0x111C APLL Control (performance level-1) 0x00C8_0301 RSVD 0x1120 to 0x11FC Reserved Undefined APLL_CON1_L8 0x1200 Control PLL AFC (performance level-1) 0x0000_0000 APLL_CON1_L7 0x1204 Control PLL AFC (performance level-7) 0x0000_0000 APLL_CON1_L6 0x1208 Control PLL AFC (performance level-6) 0x0000_0000 APLL_CON1_L5 0x120C Control PLL AFC (performance level-5) 0x0000_0000 APLL_CON1_L4 0x1210 Control PLL AFC (performance level-4) 0x0000_0000 APLL_CON1_L3 0x1214 Control PLL AFC (performance level-3) 0x0000_0000 APLL_CON1_L2 0x1218 Control PLL AFC (performance level-2) 0x0000_0000 APLL_CON1_L1 0x121C Control PLL AFC (performance level-1) 0x0000_0000 RSVD 0x1220 to 0x3FFC Reserved Undefined MPLL_LOCK 0x4000 Control PLL Locking period for MPLL 0x0000_0FFF RSVD 0x4004 to 0x40FC Reserved Undefined MPLL_CON0 0x4100 Control PLL output frequency for MPLL 0x00C8_0601 MPLL_CON1 0x4104 Control PLL AFC 0x0020_3800 CLK_SRC_CORE0 0x4200 Select Clock Source for CMU_CORE (part1) 0x0000_0000 CLK_SRC_CORE1 0x4204 Select Clock Source for CMU_CORE (part2) 0x0000_0000 RSVD 0x4208 to 0x42FC Reserved Undefined CLK_SRC_MASK_CORE 0x4300 Clock source Mask for DMC_BLK (CORE) 0x0001_0000 RSVD 0x4304 to 0x4400 Reserved Undefined CLK_MUX_STAT_CORE1 0x4404 Clock MUX Status for CMU_CORE (part2) 0x0000_0100 RSVD 0x4408 to 0x44FC Reserved Undefined CLK_DIV_CORE0 0x4500 Set Clock Divider ratio for CMU_CORE (part1) 0x0000_0000
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-36 Register Offset Description Reset Value CLK_DIV_CORE1 0x4504 Set Clock Divider ratio for CMU_CORE (part2) 0x0000_0000 CLK_DIV_SYSRGT 0x4508 Set Clock Divider ratio for CMU_CORE (part3 : SYSMEM_RGT) 0x0000_0000 RSVD 0x450C to 0x45FC Reserved Undefined CLK_DIV_STAT_CORE0 0x4600 Clock Divider Status for CMU_CORE (part1) 0x0000_0000 CLK_DIV_STAT_CORE1 0x4604 Clock Divider Status for CMU_CORE (part2) 0x0000_0000 CLK_DIV_STAT_SYSRG T 0x4608 Clock Divider Status for CMU_CORE (part3: SYSMEM_RGT) 0x0000_0000 RSVD 0x460C to 0x48FC Reserved Undefined CLK_GATE_IP_CORE 0x4900 Control IP Clock Gating for DMC_BLK (CORE) 0xFFFF_FFFF CLK_GATE_IP_SYSRGT 0x4904 Control IP Clock Gating for SYSRGT (CORE) 0xFFFF_FFFF RSVD 0x4904 to 0x490C Reserved Undefined C2C_MONITOR 0x4910 Monitoring for C2C 0x0000_0000 RSVD 0x4904 to 0x49FC Reserved Undefined CLKOUT_CMU_CORE 0x4A00 CLKOUT control register 0x0001_0000 CLKOUT_CMU_CORE _DIV_STAT 0x4A04 Clock Divider Status for CLKOUT 0x0000_0000 RSVD 0x4A08 to 0x5FFC Reserved Undefined C2C_CONFIG 0x6000 C2C configurations 0x832A_AC04 RSVD 0x6004 to 0x840C Reserved Undefined CLK_DIV_ACP 0x8500 Set Clock Divider ratio for CMU_ACP 0x0000_0000 RSVD 0x8504 to 0x85FC Reserved Undefined CLK_DIV_STAT_ACP 0x8600 Clock Divider Status for CMU_ACP 0x0000_0000 RSVD 0x8604 to 0x87FC Reserved Undefined CLK_GATE_IP_ACP 0x8800 Control IP Clock Gating for DMC_BLK (ACP) 0xFFFF_FFFF RSVD 0x8804 to 0x88FC Reserved Undefined CLK_DIV_SYSLFT 0x8900 Set clock Divider ratio for CMU_SYSLFT 0x0000_0000 RSVD 0x8904 to 0x890C Reserved Undefined CLK_DIV_STAT_SYSLFT 0x8910 Clock Divider Status for CMU_SYSLFT 0x0000_0000 RSVD 0x8914 to 0x891C Reserved Undefined
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-37 Register Offset Description Reset Value CLK_GATE_BUS_SYSLF T 0x8920 Clock gating of clock for SYSLFT_BLK 0xFFFF_FFFF RSVD 0x8924 to 0x892C Reserved Undefined RSVD 0x8934 to 0x89FC Reserved Undefined CLKOUT_CMU_ACP 0x8A00 CLKOUT Control register 0x0001_0000 CLKOUT_CMU_ACP _DIV_STAT 0x8A04 Clock Divider Status for CLKOUT 0x0000_0000 RSVD 0x8A08 to 0x8A0C Reserved Undefined UFMC_CONFIG 0x8A10 UFMC Configuration 0x0000_0000 RSVD 0x8A14 to 0xC2FC Reserved Undefined CLK_DIV_ISP0 0xC300 Set clock Divider ratio for CMU_ISP (part1) 0x0000_0000 CLK_DIV_ISP1 0xC304 Set Clock Divider ratio for CMU_ISP (part2) 0x0000_0000 CLK_DIV_ISP2 0xC308 Set Clock Divider ratio for CMU_ISP (part3) 0x0000_0000 RSVD 0xC30C to 0xC3FC Reserved Undefined CLK_DIV_STAT_ISP0 0xC400 Clock Divider Status for CMU_ISP (part1) 0x0000_0000 CLK_DIV_STAT_ISP1 0xC404 Clock Divider Status for CMU_ISP (part2) 0x0000_0000 CLK_DIV_STAT_ISP2 0xC408 Clock Divider Status for CMU_ISP (part3) 0x0000_0000 RSVD 0xC40C to 0xC7FC Reserved Undefined CLK_GATE_IP_ISP0 0xC800 Control IP Clock Gating for ISP_BLK (part1) 0xFFFF_FFFF CLK_GATE_IP_ISP1 0xC804 Control IP Clock Gating for ISP_BLK (part2) 0xFFFF_FFFF RSVD 0xC808 to 0xC8FC Reserved Undefined CLK_GATE_SCLK_ISP 0xC900 Control Special Clock Gating for ISP_BLK 0xFFFF_FFFF RSVD 0xC904 to 0xC90C Reserved Undefined MCUISP_PWR_CTRL 0xC910 Power Control register 0x0000_0000 RSVD 0xC914 to 0xC9FC Reserved Undefined CLKOUT_CMU_ISP 0xCA00 CLKOUT Control register 0x0001_0000 CLKOUT_CMU_ISP _DIV_STAT 0xCA04 Clock Divider Status for CLKOUT 0x0000_0000 RSVD 0xCA14 to 0xFFFC Reserved Undefined
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-38 Base Address: 0x1002_0000 Register Offset Description Reset Value RSVD 0x0000 to 0x001C Reserved Undefined CPLL_LOCK 0x0020 Control PLL Locking period for CPLL 0x0000_0FFF RSVD 0x0024 to 0x002C Reserved Undefined EPLL_LOCK 0x0030 Control PLL Locking period for EPLL 0x0000_0FFF RSVD 0x0034 to 0x003C Reserved Undefined VPLL_LOCK 0x0040 Control PLL Locking period for VPLL 0x0000_0FFF RSVD 0x0044 to 0x004C Reserved Undefined GPLL_LOCK 0x0050 Control PLL Locking period for GPLL 0x0000_0FFF RSVD 0x0054 to 0x011C Reserved Undefined CPLL_CON0 0x0120 Control PLL output frequency for CPLL (part1) 0x00C8_0601 CPLL_CON1 0x0124 Control PLL output frequency for CPLL (part2) 0x0020_3800 RSVD 0x0128 to 0x012C Reserved Undefined EPLL_CON0 0x0130 Control PLL output frequency for EPLL (part1) 0x0030_0301 EPLL_CON1 0x0134 Control PLL output frequency for EPLL (part2) 0x0000_0000 EPLL_CON2 0x0138 Control PLL output frequency for EPLL (part3) 0x0000_0080 RSVD 0x013C Reserved Undefined VPLL_CON0 0x0140 Control PLL output frequency for EPLL (part1) 0x0024_0201 VPLL_CON1 0x0144 Control PLL output frequency for EPLL (part2) 0x0000_0000 VPLL_CON2 0x0148 Control PLL output frequency for EPLL (part3) 0x0000_0080 RSVD 0x014C Reserved Undefined GPLL_CON0 0x0150 Control PLL output frequency for GPLL (part1) 0x00C8_0601 GPLL_CON1 0x0154 Control PLL output frequency for GPLL (part2) 0x0020_3800 RSVD 0x014C to 0x020C Reserved Undefined CLK_SRC_TOP0 0x0210 Select Clock Source for CMU_TOP (part1) 0x0000_0000 CLK_SRC_TOP1 0x0214 Select Clock Source for CMU_TOP (part2) 0x0000_0000 CLK_SRC_TOP2 0x0218 Select Clock Source for CMU_TOP (part3) 0x0000_0000 CLK_SRC_TOP3 0x021C Select Clock Source for CMU_TOP (part4) 0x0000_0000 CLK_SRC_GSCL 0x0220 Select Clock Source for CMU_GSCL 0x0000_0000 RSVD 0x0224 to 0x0228 Reserved Undefined CLK_SRC_DISP1_0 0x022C Select Clock Source for DISP1_BLK (part1) 0x0000_0000
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-39 Register Offset Description Reset Value RSVD 0x0230 to 0x023C Reserved Undefined CLK_SRC_MAU 0x0240 Select Clock Source for MAUDIO_BLK 0x0000_0001 CLK_SRC_FSYS 0x0244 Select Clock Source for FSYS_BLK 0x0000_0000 CLK_SRC_GEN 0x0248 Select Clock Source for GEN_BLK 0x0000_0000 RSVD 0x024C Reserved Undefined CLK_SRC_PERIC0 0x0250 Select Clock Source for connectivity IPs (part1) 0x0000_0000 CLK_SRC_PERIC1 0x0254 Select clock source for connectivity IPs (part2) 0x0000_0011 RSVD 0x0258 to 0x026C Reserved Undefined SCLK_SRC_ISP 0x0270 Select Special Clock source for IPs in ISP_BLK 0x0000_0000 RSVD 0x0274 to 0x030C Reserved Undefined CLK_SRC_MASK_TOP 0x0310 Clock Source Mask for CMU_TOP 0x0000_0001 RSVD 0x0314 to 0x031C Reserved Undefined CLK_SRC_MASK_GSCL 0x0320 Clock Source Mask for GSCL_BLK 0x1111_1000 RSVD 0x0324 to 0x0328 Reserved Undefined CLK_SRC_MASK _DISP1_0 0x032C Clock Source Mask for DISP1_BLK (part1) 0x0001_1115 RSVD 0x0330 Reserved Undefined CLK_SRC_MASK_MAU 0x0334 Clock Source Mask for MAUDIO_BLK 0x0000_0001 RSVD 0x0338 to 0x033C Reserved Undefined CLK_SRC_MASK_FSYS 0x0340 Clock Source Mask for FSYS_BLK 0x1001_1111 CLK_SRC_MASK_GEN 0x0344 Clock Source Mask for GEN_BLK 0x0000_0001 RSVD 0x0348 to 0x034C Reserved Undefined CLK_SRC_MASK _PERIC0 0x0350 Clock Source Mask for PERIC_BLK 0x0101_1111 CLK_SRC_MASK _PERIC1 0x0354 Clock Source Mask for PERIC_BLK 0x0111_0111 RSVD 0x0358 to 0x036C Reserved Undefined SCLK_SRC_MASK_ISP 0x0370 Special lock Source Mask for ISP_BLK 0x0000_1111 RSVD 0x0374 to 0x040C Reserved Undefined CLK_MUX_STAT_TOP0 0x0410 Clock MUX Status for CM_TOP (part1) 0x1011_1100 CLK_MUX_STAT_TOP1 0x0414 Clock MUX Status for CM_TOP (part2) 0x0111_0000
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-40 Register Offset Description Reset Value CLK_MUX_STAT_TOP2 0x0418 Clock MUX Status for CM_TOP (part3) 0x0111_1100 CLK_MUX_STAT_TOP3 0x041C Clock MUX Status for CM_TOP (part4) 0x0111_1111 RSVD 0x0420 to 0x050C Reserved Undefined CLK_DIV_TOP0 0x0510 Set Clock Divider ratio for CMU_TOP (part1) 0x0000_0000 CLK_DIV_TOP1 0x0514 Set Clock Divider ratio for CMU_TOP (part2) 0x0000_0000 RSVD 0x0518 to 0x051C Reserved Undefined CLK_DIV_GSCL 0x0520 Set Clock Divider ratio for GSCL_BLK 0x0000_0000 RSVD 0x0524 to 0x0528 Reserved Undefined CLK_DIV_DISP1_0 0x052C Set Clock Divider ratio for DISP1_BLK (part1) 0x0070_0000 RSVD 0x0530 to 0x0538 Reserved Undefined CLK_DIV_GEN 0x053C Set Clock Divider ratio for GEN_BLK 0x0000_0000 RSVD 0x0540 Reserved Undefined CLK_DIV_MAU 0x0544 Set Clock Divider ratio for MAUDIO_BLK 0x0000_0000 CLK_DIV_FSYS0 0x0548 Set Clock Divider ratio for FSYS_BLK (part1) 0x00B0_0000 CLK_DIV_FSYS1 0x054C Set Clock Divider ratio for FSYS_BLK (part2) 0x0000_0000 CLK_DIV_FSYS2 0x0550 Set Clock Divider ratio for FSYS_BLK (part3) 0x0000_0000 RSVD 0x0554 Reserved Undefined CLK_DIV_PERIC0 0x0558 Set Clock Divider ratio for PERIC_BLK (part1) 0x0000_0000 CLK_DIV_PERIC1 0x055C Set Clock Divider ratio for PERIC_BLK (part2) 0x0000_0000 CLK_DIV_PERIC2 0x0560 Set Clock Divider ratio for PERIC_BLK (part3) 0x0000_0000 RSVD 0x0564 Reserved 0x0000_0000 CLK_DIV_PERIC4 0x0568 Set Clock Divider ratio for PERIC_BLK (part5) 0x0000_0000 CLK_DIV_PERIC5 0x056C Set Clock Divider ratio for PERIC_BLK (part6) 0x0000_0000 RSVD 0x0570 to 0x057C Reserved Undefined SCLK_DIV_ISP 0x0580 Set Special Clock Divider ratio for ISP_BLK 0x0000_0000 RSVD 0x0584 to 0x058C Reserved Undefined CLKDIV2_RATIO0 0x0590 Set PCLK Divider ratio for GSCL, GEN, DISP1 and MFC block 0x1011_1110 CLKDIV2_RATIO1 0x0594 Set ATCLK, PCLKDBG Divider ratio for FSYS block 0x0000_0005 RSVD 0x0598 to 0x059C Reserved Undefined CLKDIV4_RATIO 0x05A0 Set PCLK Divider Ratio in MFC block 0x0000_0003
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-41 Register Offset Description Reset Value RSVD 0x05A4 to 0x060C Reserved Undefined CLK_DIV_STAT_TOP0 0x0610 Clock Divider Status for CMU_TOP (part1) 0x0000_0000 CLK_DIV_STAT_TOP1 0x0614 Clock Divider Status for CMU_TOP (part2) 0x0000_0000 RSVD 0x0618 to 0x061C Reserved Undefined CLK_DIV_STAT_GSCL 0x0620 Clock Divider Status for GSCL_BLK 0x0000_0000 RSVD 0x0624 to 0x0628 Reserved Undefined CLK_DIV_STAT_DISP1_0 0x062C Clock Divider Status for DISP1_BLK (part1) 0x0000_0000 RSVD 0x0630 to 0x0638 Reserved Undefined CLK_DIV_STAT_GEN 0x063C Clock Divider Status for GEN_BLK 0x0000_0000 RSVD 0x0640 Reserved Undefined CLK_DIV_STAT_MAU 0x0644 Clock Divider Status for MAUDIO_BLK 0x0000_0000 CLK_DIV_STAT_FSYS0 0x0648 Clock Divider Status for FSYS_BLK (part1) 0x0000_0000 CLK_DIV_STAT_FSYS1 0x064C Clock Divider Status for FSYS_BLK (part2) 0x0000_0000 CLK_DIV_STAT_FSYS2 0x0650 Clock Divider Status for FSYS_BLK (part3) 0x0000_0000 RSVD 0x0654 Reserved Undefined CLK_DIV_STAT_PERIC0 0x0658 Clock Divider Status for PERIC_BLK (part1) 0x0000_0000 CLK_DIV_STAT_PERIC1 0x065C Clock Divider Status for PERIC_BLK (part2) 0x0000_0000 CLK_DIV_STAT_PERIC2 0x0660 Clock Divider Status for PERIC_BLK (part3) 0x0000_0000 CLK_DIV_STAT_PERIC3 0x0664 Clock Divider Status for PERIC_BLK (part4) 0x0000_0000 CLK_DIV_STAT_PERIC4 0x0668 Clock Divider Status for PERIC_BLK (part5) 0x0000_0000 CLK_DIV_STAT_PERIC5 0x066C Clock Divider Status for PERIC_BLK (part6) 0x0000_0000 RSVD 0x0670 to 0x067C Reserved Undefined SCLK_DIV_STAT_ISP 0x0680 Special Clock Divider Status for ISP_BLK 0x0000_0000 RSVD 0x0684 to 0x068C Reserved Undefined CLKDIV2_STAT0 0x0690 PCLK Divider Status for GSCL, GEN, DISP1 and MFC block 0x0000_0000 CLKDIV2_STAT1 0x0694 ATCLK, PCLKDBG Divider Status for FSYS block 0x0000_0000 RSVD 0x0698 to 0x069C Reserved Undefined CLKDIV4_STAT 0x06A0 PCLK Divider Status for MFC block 0x0000_0000 RSVD 0x06A4 to 0x0820 Reserved Undefined
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-42 Register Offset Description Reset Value CLK_GATE_TOP _SCLK_DISP1 0x0828 Gating Special Clock for DISP1_BLK 0xFFFF_FFFF CLK_GATE_TOP _SCLK_GEN 0x082C Gating Special Clock for GEN_BLK 0xFFFF_FFFF RSVD 0x0830 to 0x0838 Reserved Undefined CLK_GATE_TOP _SCLK_MAU 0x083C Gating Special Clock for MAUDIO_BLK 0xFFFF_FFFF CLK_GATE_TOP _SCLK_FSYS 0x0840 Gating Special Clock for FSYS_BLK 0xFFFF_FFFF RSVD 0x0844 to 0x084C Reserved Undefined CLK_GATE_TOP _SCLK_PERIC 0x0850 Gating Special Clock for PERIC_BLK 0xFFFF_FFFF RSVD 0x0854 to 0x086C Reserved Undefined CLK_GATE_TOP _SCLK_ISP 0x0870 Gating Special Clock for ISP_BLK 0xFFFF_FFFF RSVD 0x0874 to 0x091C Reserved Undefined CLK_GATE_IP_GSCL 0x0920 Control IP Clock Gating for GSCL_BLK 0xFFFF_FFFF RSVD 0x0924 Reserved Undefined CLK_GATE_IP_DISP1 0x0928 Control IP Clock Gating for DISP1_BLK 0xFFFF_FFFF CLK_GATE_IP_MFC 0x092C Control IP Clock Gating for MFC_BLK 0xFFFF_FFFF CLK_GATE_IP_G3D 0x0930 Control IP Clock Gating for G3D_BLK 0xFFFF_FFFF CLK_GATE_IP_GEN 0x0934 Control IP Clock Gating for GEN_BLK 0xFFFF_FFFF RSVD 0x0938 to 0x0940 Reserved Undefined CLK_GATE_IP_FSYS 0x0944 Control IP Clock Gating for FSYS_BLK 0xFFFF_FFFF RSVD 0x0948 to 0x094C Reserved Undefined CLK_GATE_IP_PERIC 0x0950 Control IP Clock Gating for PERIC_BLK 0xFFFF_FFFF RSVD 0x0954 to 0x095C Reserved Undefined CLK_GATE_IP_PERIS 0x0960 Control IP Clock Gating for PERIS_BLK 0xFFFF_FFFF RSVD 0x0964 to 0x097C Reserved Undefined CLK_GATE_BLOCK 0x0980 Control Block Clock Gating 0xFFFF_FFFF RSVD 0x0984 to 0x099C Reserved Undefined MCUIOP_PWR_CTRL 0x09A0 MCUIOP Power Control 0x0000_0000
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-43 Register Offset Description Reset Value RSVD 0x09A4 to 0x09FC Reserved Undefined CLKOUT_CMU_TOP 0x0A00 CLKOUT Control Register 0x0001_0000 CLKOUT_CMU_TOP _DIV_STAT 0x0A04 Clock Divider Status for CLKOUT 0x0000_0000 RSVD 0x0A08 to 0x41FC Reserved Undefined CLK_SRC_LEX 0x4200 Select Clock Source for CMU_LEX 0x0000_0000 RSVD 0x4204 to 0x43FC Reserved Undefined CLK_MUX_STAT_LEX 0x4400 Clock MUX Status for CMU_LEX 0x0000_0001 RSVD 0x4404 to 0x44FC Reserved Undefined CLK_DIV_LEX 0x4500 Set Clock Divider ratio for CMU_LEX 0x0000_0000 RSVD 0x4504 to 0x45FC Reserved Undefined CLK_DIV_STAT_LEX 0x4600 Clock Divider Status for CMU_LEX 0x0000_0000 RSVD 0x4604 to 0x47FC Reserved Undefined CLK_GATE_IP_LEX 0x4800 Control IP Clock Gating for LEX_BLK 0xFFFF_FFFF RSVD 0x4804 to 0x49FC Reserved Undefined CLKOUT_CMU_LEX 0x4A00 CLKOUT control register 0x0001_0000 CLKOUT_CMU_LEX _DIV_STAT 0x4A04 Clock Divider Status for CLKOUT 0x0000_0000 RSVD 0x4A08 to 0x84FC Reserved Undefined CLK_DIV_R0X 0x8500 Set clock Divider Ratio for CMU_R0X 0x0000_0000 RSVD 0x8504 to 0x85FC Reserved Undefined CLK_DIV_STAT_R0X 0x8600 Clock Divider Status for CMU_R0X 0x0000_0000 RSVD 0x8604 to 0x87FC Reserved Undefined CLK_GATE_IP_R0X 0x8800 Control IP Clock Gating for R0X_BLK 0xFFFF_FFFF RSVD 0x8804 to 0x89FC Reserved Undefined CLKOUT_CMU_R0X 0x8A00 CLKOUT control register 0x0001_0000 CLKOUT_CMU_R0X _DIV_STAT 0x8A04 Clock Divider Status for CLKOUT 0x0000_0000 RSVD 0x8A08 to 0xC4FC Reserved Undefined
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-44 Register Offset Description Reset Value CLK_DIV_R1X 0xC500 Set clock Divider ratio for CMU_R1X 0x0000_0000 RSVD 0xC504 to 0xC5FC Reserved Undefined CLK_DIV_STAT_R1X 0xC600 Clock Divider Status for CMU_R1X 0x0000_0000 RSVD 0xC604 to 0xC7FC Reserved Undefined CLK_GATE_IP_R1X 0xC800 Control IP Clock Gating for R1X_BLK 0xFFFF_FFFF RSVD 0xC804 to 0xC9FC Reserved Undefined CLKOUT_CMU_R1X 0xCA00 CLKOUT control register 0x0001_0000 CLKOUT_CMU_R1X _DIV_STAT 0xCA04 Clock Divider Status for CLKOUT 0x0000_0000 RSVD 0xCA08 to 0xCFFC Reserved Undefined