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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-55  
5.9.1.8 CLK_DIV_STAT_CPU0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0600, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:29] –=Reserved=0x0=
DIV_ARM2=[28]=o=
DIV_ARM2=status=
0 = Stable=
1 = Divider is=on changing=
0x0=
RSVD=x27:25]=–=Reserved=0x0=
DIV_APLL=[24]=o=
DIV_APLL status=
0 = Stable=
1 = Divider is=on changing=
0x0=
RSVD=[23:21]=–=Reserved=0x0=
DIV_PCLK_DBG=[20]=o=
DIV_PCLK_DBG status=
0 ==Stable=
1 = Divider is on changing=
0x0=
RSVD=[19:17]=–=Reserved=0x0=
DIV_ATB=[16]=o=
DIV_ATB status=
0 = Stable=
1 = Divider is=on changing=
0x0=
RSVD=[15:13]=–=Reserved=0x0=
DIV_PERIPH=[12]=o=
DIV_PERIPH=status=
0 = Stable=
1 = Divider is=on changing=
0x0=
RSVD=[11:9]=–=Reserved=0x0=
DIV_ACm=[8]=o=
DIV_ACm=status=
0 = Stable=
1 = Divider is=on changing=
0x0=
RSVD=[7:5]=–=Reserved=0x0=
DIV_CPUD=[4]=o=
DIV_CPUD=status=
0 = Stable=
1 = Divider is=on changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_ARM=[0]=o=
DIV_ARM=status=
0 = Stable=
1 = Divider is on changing=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-56  
5.9.1.9 CLK_DIV_STAT_CPU1 
 Base Address: 0x1001_0000 
 Address = 0x1004_4604, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
DIV_HPM=[4]=o=
DIV_HPM status=
0== Stable=
1 = Divider is on changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_COPY=[0]=o=
DIV_COPY status=
0 = Stable=
1 = Divider is=on changing=
0x0=
=
5.9.1.10 CLK_GATE_SCLK_CPU 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0800, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:2] –=Reserved=0x3FFF_FFFc=
pCLK_HPM=x1]=RW=
Gating=ppecial=Clock for HPM local clock=
0 = Masks==
1 = Passes=
0x1=
RSVD=x0]=–=Reserved=0x1=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-57  
5.9.1.11 CLKOUT_CMU_CPU 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = APLL_FOUT=
00001 = Reserved=
00010 = Reserved=
00011 = Reserved=
00100 = ARMCLK=
00101 = ACLK_CPUD=
00110 = Reserved=
00111 = ATCLh=
01000 = PERIPHCLh=
01001 = PCLK_DBG=
01010 = SCLK_HPM=
0x0=
=
5.9.1.12 CLKOUT_CMU_CPU_DIV_STAT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0A04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIV_CLKOUT status=
0 = Stable=
1 = Divider is on changing=
0x0=
=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-58  
5.9.1.13 ARMCLK_STOPCTRL 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1000, Reset Value = 0x0000_0044 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x0=
POST_W AIT_CNT=x7:4]=RW=
Clock freeze cycle after ARM clamp=(CLADUAL-
CORE0,=CLADUAi-CORE1,=CLADUAi-
COREOUT,=CLAMPL2_0,=CLAMPL2_1) or reset 
signal=(nCPURESET,=nDBGRESET,=nSCURESET,=
L2nRESET,=nWDRESET,=nPERIPHRESET,=
nPTMRESET) transition=
0x4=
PRE_t AIT_CNT=x3:0]=RW=
Clock freeze cycle=before ARM clamp=(CLADUAL-
CORE0,=CLADUAi-CORE1,=CLADUAi-
COREOUT,=CLAMPL2_0,=CLAMPL2_1) or reset 
signal=(nCPURESET,=nDBGRESET,=nSCURESET,=
L2nRESET,=nWDRESET,=nPERIPHRESET,=
nPTMRESET) transition=
0x4=
=
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Exynos 5250_UM 5 Clock Controller 
 5-59  
5.9.1.14 PARITYFAIL_STATUS 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1010, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:18] –=Reserved=0x0=
PARITYFAILSCr=[17:16]=o=
Parity output pin from SCU tag RAMs =
OR=operated=output from each E4D processor=
present in the design=
0x0=
PARITYFAIL1=[15:8]=o=
Parity output pin from the RAM array for CPU1=
Indicates a parity fail=
0 = No parity fail=
1 = Parity fail=
Bitx7]:=BTAC parity error=
BitxS]:=GHB parity error=
Bitx5]:=Instruction tag RAM parity error=
Bitx4]:=Instruction data RAM parity error=
Bitx3]:=Main TLB parity error=
Bitx2]:=D outer RAM parity error=
Bitx1]:Data tag RAM parity error=
Bitx0]:=Data RAM parity error=
0x0=
PARITYFAIL0=[7:0]=o=
Parity output pin from the RAM array for CPU0=
Indicates a Parity Fail=
0 = No parity fail=
1 = Parity fail=
Bitx7]:=BTAC parity error=
BitxS]:=GHB parity error=
Bitx5]:=Instruction tag RAM parity error=
Bitx4]:=Instruction data RAM parity error=
Bitx3]:=Main TLB parity error=
Bitx2]:=D outer RAM parity error=
Bitx1]:=Data tag RAM parity error=
Bitx0]:=Data RAM parity error=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-60  
5.9.1.15 PARITYFAIL_CLEAR 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1014, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:18] –=Reserved=0x0=
PARITYFAILSCr=[17:16]=RWu=
Parity output pin from SCU tag RAMs =
OR=operated output from each E4D processor 
present in the design=
0x0=
PARITYFAIL1=[15:8]=RWu=
Parity output pin from the RAM array for CPU1=
Indicates a Parity Fail=
0== No parity fail=
1 = Parity fail=
Bitx7]:=BTAC parity error=
BitxS]:=GHB parity error=
Bitx5]:=Instruction tag RAM parity error=
Bitx4]:=Instruction data RAM parity error=
Bitx3]:=Main TLB parity error=
Bitx2]:=D outer RAM parity error=
Bitx1]:=Data tag RAM parity error=
Bitx0]:=Data RAM parity error=
0x0=
PARITYFAIL0=[7:0]=RWu=
Parity output pin from the RAM array for CPU0=
Indicates a parity fail=
0 = No parity fail=
1 = Parity fail=
Bitx7]:=BTAC parity error=
BitxS]:=GHB parity error=
Bitx5]:=Instruction tag RAM parity error=
Bitx4]:=Instruction data RAM parity error=
Bitx3]:=Main TLB parity error=
Bitx2]:=D outer RAM parity error=
Bitx1]:=Data tag RAM parity error=
Bitx0]:=Data RAM parity error=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-61  
5.9.1.16 PWR_CTRL 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1020, Reset Value = 0x0000_0033 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ARM2_RATIO=x30:28]=RW=DIV_ARM2 clock divider=oatio when ARM cores 
are in W ait For Interrupt/Event state=0x0=
RSVD=x27:21]=–=Reserved=0x0=
CSCLK_AUTO=
_ENB_IN_DEBUd=x20]=RW=
Force CoreSight clocks to toggle when debugger=
is attached=
0 = Disables=
1 = Enables=
0x0=
RSVD=x19]=–=Reserved=0x0=
ARM_RATIl=[18:16]=RW=DIV_ARM clock divider oatio when ARM cores are 
in Wait For Interrupt/Event state=0x0=
RSVD=x15:10]=–=Reserved=0x0=
DIs_ARM2_DOW
N_ENB=[9]=RW=
Enable ARMCLK Down feature with ARM cores in=
IDLE mode for DIs_ARM2=
0 = Disables=
1 = Enables=
0x0=
DIs_ARM_DOW N=
_ENB=[8]=RW=
Enable ARMCLK down feature with ARM cores in=
IDLE=mode for DIV_ARM=
0 = Disables=
1 = Enables=
0x0=
RSVD=x7:S]=–=Reserved=0x0=
USE_STANDBYW
FE_ARM_CORE1=[5]=RW=Use ARM CORE1 STANDBYWFE to change=
ARMCLK frequency in ARM IDLE state=0x1=
USE_STANDBYW
FE_ARM_CORE0=[4]=RW=Use ARM CORE0 STANDBYWFE to change=
ARMCLK=frequency in ARM IDLE state=0x1=
RSVD=x3:2]=–=Reserved=0x0=
USE_STANDBYW
FI_ARM_CORE1=[1]=RW=Use ARM CORE1 STANDBYWFI to change=
ARMCLK frequency in ARM IDLE state=0x1=
USE_STANDBYW
FI_ARM_CORE0=[0]=RW=Use ARM CORE0 STANDBYWFI to change=
ARMCLK frequency in ARM IDLE state=0x1=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-62  
5.9.1.17 PWR_CTRL2 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1024, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0x0=
DIs_ARM2_UP=
_ENB=x25]=RW=
Enable ARMCLK up feature with ARM cores when=
exiting from IDLE mode for DIV_ARM2=
0 = Disables=
1 = Enables=
0x0=
DIs_ARM_UP_EN
B=x24]=RW=
Enable ARMCLK up feature with ARM cores when=
exiting from IDLE mode for DIV_ARM=
0 = Disables=
1 = Enables=
0x0=
DUR_STANDBY2=x23:1S]=RW=
Set duration to go to the normal divider value from 
the middle divider value. This bit=is=left-shifted by=
4-bit before comparing to counter value.=
0x0=
DUR_STANDBY1=x15:8]=RW=
Set duration to go to the middle divider value from 
the divider value in ARM idle. This bit is=left-shifted 
by 4-bit before comparing to counter value.=
0x0=
RSVD=x7]=–=Reserved=0x0=
UP_ARM2_RATIl=x6:4]=RW=
DIs_ARM2 clock divider ratio when either of=
ARM0 or=ARM1 cores is not in Wait For 
Interrupt/Event state.=
0x0=
RSVD=x3]=–=Reserved=0x0=
UP_ARM_RATIO=x2:0]=RW=
DIs_ARM clock divider ratio when either of ARM0=
or ARM1 cores is not in Wait For Interrupt/Event=
state.=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-63  
5.9.1.18 APLL_CON0_L8 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1100, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
5.9.1.19 APLL_CON0_L7 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1104, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-64  
5.9.1.20 APLL_CON0_L6 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1108, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
5.9.1.21 APLL_CON0_L5 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x110C, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
=
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