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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-89  
Name Bit Type Description Reset Value 
INTFIFOEN are high. 
FIFOLEVEL [4:2] RW 
Selects the Video FIFO Interrupt Level. 
000 = 0 to 25 %  
001 = 0 to 50 %  
010 = 0 to 75 % 
011 = 0 % (empty) 
100 = 100 % (full) 
0 
INTFIFOEN [1] RW 
Specifies the Video FIFO Interrupt enable control bit. 
0 = Disables video FIFO level interrupt 
1 = Enables video FIFO level interrupt 
NOTE: This bit is significant, when INTEN is high. 
0 
INTEN [0] RW 
Specifies the Video Interrupt enable control bit. 
0 = Disables video interrupt 
1 = Enables video interrupt  
0 
NOTE:  
1. When video frame interrupt occurs, you can set FRAMESEL0 and FRAMESEL1 to select maximum two points. For  
  example, when FRAMESEL0 = 00 and FRAMESEL1 = 11, the video frame interrupt triggers both at the start of  
  back porch and the front porch. 
2. Exynos 5250 interrupt controller contains three interrupt sources associated to display controller: LCD[0], LCD[1] and  
 LCD[2].  
  LCD[0] specifies FIFO level interrupt and LCD[1] specifies video frame sync interrupt and LCD[2] specifies i80 done  
  interface interrupt.
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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-90  
15.5.2.31 VIDINTCON1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0134, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0=
RSVD=[4:3]=–=Reserved (should be 0)=0=
INTI80PENa=[2]=–=
Specifies the i80 Done=interrupt. Writes=1 to clear this bit.=
0 = fnterrupt has not been requested=
1 = I80 Done status=has asserted the interrupt request=
0=
INTFRMPEND=[1]=RW=
Specifies the Frame sync=Interrupt. Writes=1 to clear this 
bit.=
0 = Does not request interrupt=
1 = Frame sync status=asserts the interrupt request=
0=
INTFIFOPENa=[0]=RW=
Specifies the FIFO Level interrupt. Writes=1 to clear this 
bit.=
0 = Does not request interrupt=
1 = FIFO=empty status asserts the interrupt request=
0=
=
15.5.2.32 W1KEYCON0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0140, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
KEYBLEN_F [26] RW 
Enables blending. 
0 = Disables blending 
1 = Enables blending by using original alpha for non-key 
area and KEY_ALPHA for key area 
0 
KEYEN_F [25] RW 
Enables/Disables Color Key (Chroma key). 
0 = Disables color key 
1 = Enables color key 
0 
DIRCON_F [24] RW 
Controls the direction of color key (Chroma key). 
0 = When the pixel value matches foreground image with 
COLVAL, it displays the pixel from background (only in 
OSD area) 
1 = When the pixel value matches background image with 
COLVAL, it displays the pixel from foreground image(only 
in OSD area) 
0 
COMPKEY_F [23:0] RW Each bit corresponds to COLVAL[23:0]. W hen a position bit 
is set, it disables the position bit of COLVAL. 0 
NOTE: Set BLD_PIX = 1, ALPHA_SEL = 0, A_FUNC = 0x2, and B_FUNC = 0x3 to enable alpha blending using color key.
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Exynos 5250_UM 15 Display Controller 
 15-91  
15.5.2.33 W1KEYCON1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0144, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
COLVAL_F  [23:0] RW Specifies the Color Key Value for transparent pixel effect. 0 
 
15.5.2.34 W2KEYCON0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0148, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
KEYBLEN_F [26] RW 
Enables blending. 
0 = Disables blending 
1 = Enables blending by using original alpha for non-key 
area and KEY_ALPHA for key area 
0 
KEYEN_F [25] RW 
Enables color key (Chroma key). 
0 = Disables color key 
1 = Enables color key 
0 
DIRCON_F [24] RW 
Controls the direction of color key (Chroma key). 
0 = When the pixel value matches foreground image with 
COLVAL, it displays the pixel from background image 
(only in OSD area) 
1 = When the pixel value matches background image with 
COLVAL, it displays the pixel from foreground image (only 
in OSD area) 
0 
COMPKEY_F [23:0] RW 
Each bit corresponds to COLVAL[23:0]. 
When a position bit is set, it disables the position bit of 
COLVAL. 
0 
NOTE: Set BLD_PIX = 1, ALPHA_SEL = 0, A_FUNC = 0x2, and B_FUNC = 0x3 to enable alpha blending by using color key. 
 
15.5.2.35 W2KEYCON1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x014C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
COLVAL_F [23:0] RW Specifies the Color Key Value for transparent pixel effect. 0
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Exynos 5250_UM 15 Display Controller 
 15-92  
15.5.2.36 W3KEYCON0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0150, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
KEYBLEN_F [26] RW 
Enables blending. 
0 = Disables blending 
1 = Enables blending by using original alpha for non-key 
area and  
KEY_ALPHA for key area 
0 
KEYEN_F [25] RW 
Enables Color Key (Chroma key). 
0 = Disables color key 
1 = Enables color key 
0 
DIRCON_F [24] RW 
Controls the direction of Color key (Chroma key). 
0 = When the pixel value matches foreground image with 
COLVAL, it displays the pixel from background image 
(only in OSD area) 
1 = When the pixel value matches background image with 
COLVAL, it displays the pixel from foreground image (only 
in OSD area) 
0 
COMPKEY_F [23:0] RW Each bit corresponds to COLVAL[23:0]. W hen a position 
bit is set, it disables the position bit of COLVAL. 0 
NOTE: Set BLD_PIX = 1, ALPHA_SEL = 0, A_FUNC = 0x2, and B_FUNC = 0x3 to enable alpha blending by using color key. 
 
15.5.2.37 W3KEYCON1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0154, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
COLVAL_F [23:0] RW Specifies the Color Key Value for transparent pixel effect. 0
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Exynos 5250_UM 15 Display Controller 
 15-93  
15.5.2.38 W4KEYCON0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0158, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
KEYBLEN_F [26] RW 
Enables blending. 
0 = Disables blending 
1 = Enables blending by using original alpha for non-key 
area and KEY_ALPHA for key area 
0 
KEYEN_F [25] RW 
Enables Color Key (Chroma key). 
0 = Disables color key 
1 = Enables color key 
0 
DIRCON_F [24] RW 
Controls the direction of Color Key (Chroma key). 
0 = When the pixel value matches foreground image with 
COLVAL, it displays the pixel from background image 
(only in OSD area) 
1 = When the pixel value matches background image with 
COLVAL, it displays the pixel from foreground image (only 
in OSD area) 
0 
COMPKEY_F [23:0] RW Each bit corresponds to COLVAL[23:0]. W hen a position 
bit is set, it disables the COLVAL position bit. 0 
NOTE: Set BLD_PIX = 1, ALPHA_SEL = 0, A_FUNC = 0x2, and B_FUNC = 0x3 to enable alpha blending by using color key.
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Exynos 5250_UM 15 Display Controller 
 15-94  
15.5.2.39 W4KEYCON1 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x015C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
COLVAL_F [23:0] RW Specifies the Color Key Value for transparent pixel effect. 0 
NOTE: COLVAL and COMPKEY use 24-bit color data in all BPP modes. 
 
At bpp -24 mode: 24-bit color value is valid  
 A. COLVAL 
 Red: COLVAL[23:17] 
 Green: COLVAL[15: 8] 
 Blue: COLVAL[7:0] 
 
 B. COMPKEY 
 Red: COMPKEY[23:17] 
 Green: COMPKEY[15: 8] 
 Blue: COMPKEY[7:0] 
 
At bpp-16 (5:6:5) mode: 16-bit color value is valid 
 A. COLVAL 
 Red: COLVAL[23:19] 
 Green: COLVAL[15:10] 
 Blue: COLVAL[7:3]  
 
 B. COMPKEY 
 Red: COMPKEY[23:19] 
 Green: COMPKEY[15:10] 
 Blue: COMPKEY[7:3] 
 Ensure COMPKEY[18:16] is 0x7 
 Ensure COMPKEY[9: 8] is 0x3 
 Ensure COMPKEY[2:0] is 0x7 
NOTE: Ensure to set the COMPKEY register appropriately for each BPP mode.
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Exynos 5250_UM 15 Display Controller 
 15-95  
15.5.2.40 W1KEYALPHA 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0160, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0=
KEYALPHA_R_F=[23:16]=RW=Specifies the hey=Alpha Red=value.=0=
KEYALPHA_G_F=x15:8]=RW=Specifies the=Key Alpha Green value.=0=
KEYALPHA_B_F=x7:0]=RW=Specifies the=Key Alpha Blue value.=0=
=
15.5.2.41 W2KEYALPHA 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0164, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0=
KEYALPHA_R_F=[23:16]=ot=Specifies the hey=Alpha Red=value.=0=
KEYALPHA_G_F=x15:8]=ot=Specifies the=Key Alpha Green value.=0=
KEYALPHA_B_F=x7:0]=ot=Specifies the=Key Alpha Blue value.=0=
=
15.5.2.42 W3KEYALPHA 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0168, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0=
KEYALPHA_R_F=[23:16]=ot=Specifies the hey=Alpha Red=value.=0=
KEYALPHA_G_F=x15:8]=ot=Specifies the=Key Alpha Green value.=0=
KEYALPHA_B_F=x7:0]=ot=Specifies the=Key Alpha Blue value.=0=
=
=
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Exynos 5250_UM 15 Display Controller 
 15-96  
15.5.2.43 W4KEYALPHA 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x016C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0=
KEYALPHA_R_F=[23:16]=ot=Specifies=the hey=Alpha Red=value.=0=
KEYALPHA_G_F=x15:8]=ot=Specifies the=Key Alpha Green value.=0=
KEYALPHA_B_F=x7:0]=ot=Specifies the=Key Alpha Blue value.=0=
=
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Exynos 5250_UM 15 Display Controller 
 15-97  
15.5.2.44 WIN0MAP 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0180, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
MAPCOLEN_F [24] RW 
Specifies window Color Mapping control bit. 
When this bit is enabled, the Video DMA stops, and 
MAPCOLOR appears on background image, instead of 
the original image. 
0 = Disables color mapping 
1 = Enables color mapping 
0 
MAPCOLOR [23:0] RW Specifies the Color value. 0 
 
15.5.2.45 WIN1MAP 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0184, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
MAPCOLEN_F [24] RW 
Specifies the window Color Mapping control bit. W hen this 
bit is enabled, the Video DMA stops, and MAPCOLOR 
appears on background image, instead of original image. 
0 = Disables color mapping 
1 = Enables color mapping 
0 
MAPCOLOR [23:0] RW Specifies the Color value. 0 
 
15.5.2.46 WIN2MAP 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0188, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
MAPCOLEN_F [24] RW 
Specifies the window Color Mapping control bit. 
When this bit is enabled, the Video DMA stops, and 
MAPCOLOR appears on background image, instead of 
original image. 
0 = Disables color mapping 
1 = Enables color mapping 
0 
MAPCOLOR [23:0] RW Specifies the Color value. 0
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Exynos 5250_UM 15 Display Controller 
 15-98  
15.5.2.47 WIN3MAP 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x018C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
MAPCOLEN_F [24] RW 
Specifies the window Color Mapping control bit. 
When this bit is enabled, the Video DMA stops, and 
MAPCOLOR appears on background image, instead of 
original image. 
0 = Disables color mapping 
1 = Enables color mapping 
0 
MAPCOLOR [23:0] RW Specifies the Color value. 0 
 
15.5.2.48 WIN4MAP 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0190, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
MAPCOLEN_F [24] RW 
Specifies the window Color Mapping control bit. 
When this bit is enabled, the Video DMA stops, and 
MAPCOLOR appears on background image, instead of 
original image. 
0 = Disables color mapping 
1 = Enables color mapping 
0 
MAPCOLOR [23:0] RW Specifies the Color value. 0 
 
15.5.2.49 WPALCON_H 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x019C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:19] –=oeserved=0=
W4PAL_e=x18:17]=RW=W4PAL[2:1]=0=
oSVa=[16:15]=–=oeserved=0=
W3PAL_e=x14:13]=RW=W3PAL[2:1]=0=
RSVD=[12:11]=RW=oeserved=0=
W2PAL_e=x10: 9]=RW=W2PAL[2:1]=0=
oSVa=[ 8: 0]=–=oeserved=0=
=
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