Samsung Exynos 5 User Manual
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Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-190
5.9.1.193 CLK_GATE_IP_CDREX
Base Address: 0x1003_0000
Address = Base Address + 0x0900, Reset Value = 0xFFFF_FFFF
Name Bit Type Description Reset Value
RSVD [31:26] –=Reserved=0x3F=
CLK_TZASC=
_CBXt=[25]=RW=
Gating AXI=Clock for TZASC_XCBXW and DRAM
controller port1=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_CBXo=[24]=RW=
Gating AXI=Clock for TZASC_XCBXR=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_DRBXW=[23]=RW=
Gating AXI=Clock for...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-555.png "Page 556
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-190
5.9.1.193 CLK_GATE_IP_CDREX
Base Address: 0x1003_0000
Address = Base Address + 0x0900, Reset Value = 0xFFFF_FFFF
Name Bit Type Description Reset Value
RSVD [31:26] –=Reserved=0x3F=
CLK_TZASC=
_CBXt=[25]=RW=
Gating AXI=Clock for TZASC_XCBXW and DRAM
controller port1=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_CBXo=[24]=RW=
Gating AXI=Clock for TZASC_XCBXR=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_DRBXW=[23]=RW=
Gating AXI=Clock for...")
![Page 557
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-191
Name Bit Type Description Reset Value
CLK_DREX2 [3] RW
Gating all Clocks for DRAM controller and clk2x for
LPDDRHPHY0 and LPDDRHPHY1
0 = Masks
1 = Passes
0x1
CLK
_SFRCDREXP [2] RW
Gating all Clocks for AHB2APB_CDREXP and
ASYNCAHBM_PCX_CDREXP
0 = Masks
1 = Passes
0x1
RSVD [1:0] – Reserved 0x3](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-556.png "Page 557
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-191
Name Bit Type Description Reset Value
CLK_DREX2 [3] RW
Gating all Clocks for DRAM controller and clk2x for
LPDDRHPHY0 and LPDDRHPHY1
0 = Masks
1 = Passes
0x1
CLK
_SFRCDREXP [2] RW
Gating all Clocks for AHB2APB_CDREXP and
ASYNCAHBM_PCX_CDREXP
0 = Masks
1 = Passes
0x1
RSVD [1:0] – Reserved 0x3")
![Page 558
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-192
5.9.1.194 DMC_FREQ_CTRL
Base Address: 0x1003_0000
Address = Base Address + 0x0914, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
RSVD [31:15] –=Reserved=0x0=
MCLK_CDREX2=
_RATIO=[14:12]=RW=
DIV_MCLK_CDREX2 clock divider oatio=
MCLK_CDREX2 = MOUT_MCLK_DPHY/==
(MCLK_CDREX2_RATIO + 1)=
0x0=
RSVD=[11]=–=Reserved=0x0=
MCLK_DPHY=
_RATIO=[10:8]=RW=
DIV_MCLK_DPHY clock divider oatio=
MCLK_DPHY = MOUT_MCLK_DPHY/==...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-557.png "Page 558
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-192
5.9.1.194 DMC_FREQ_CTRL
Base Address: 0x1003_0000
Address = Base Address + 0x0914, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
RSVD [31:15] –=Reserved=0x0=
MCLK_CDREX2=
_RATIO=[14:12]=RW=
DIV_MCLK_CDREX2 clock divider oatio=
MCLK_CDREX2 = MOUT_MCLK_DPHY/==
(MCLK_CDREX2_RATIO + 1)=
0x0=
RSVD=[11]=–=Reserved=0x0=
MCLK_DPHY=
_RATIO=[10:8]=RW=
DIV_MCLK_DPHY clock divider oatio=
MCLK_DPHY = MOUT_MCLK_DPHY/==...")
![Page 559
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-193
5.9.1.196 CLKOUT_CMU_CDREX
Base Address: 0x1003_0000
Address = Base Address + 0x0A00, Reset Value = 0x0001_0000
Name Bit Type Description Reset Value
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = MCLK_CDREX=
00001 = ACLK_CDREX=
00010...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-558.png "Page 559
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-193
5.9.1.196 CLKOUT_CMU_CDREX
Base Address: 0x1003_0000
Address = Base Address + 0x0A00, Reset Value = 0x0001_0000
Name Bit Type Description Reset Value
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = MCLK_CDREX=
00001 = ACLK_CDREX=
00010...")
![Page 560
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-194
5.9.1.199 LPDDR3PHY_CON3
Base Address: 0x1003_0000
Address = Base Address + 0x0A20, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
DRAM_POP_EN [31] RW Set this bit to 1 for POP 0x0
RSVD [30:0] –=Reserved=0x0=
=
5.9.1.200 PLL_DIV2_SEL
Base Address: 0x1003_0000
Address = Base Address + 0x0A24, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
RSVD [31:5] –=Reserved=0x0=
MPLL_FOUT_SEi=x4]=RW=...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-559.png "Page 560
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-194
5.9.1.199 LPDDR3PHY_CON3
Base Address: 0x1003_0000
Address = Base Address + 0x0A20, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
DRAM_POP_EN [31] RW Set this bit to 1 for POP 0x0
RSVD [30:0] –=Reserved=0x0=
=
5.9.1.200 PLL_DIV2_SEL
Base Address: 0x1003_0000
Address = Base Address + 0x0A24, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
RSVD [31:5] –=Reserved=0x0=
MPLL_FOUT_SEi=x4]=RW=...")
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Samsung Confidential
Exynos 5250_UM 6 Interrupt Controller
6-2
6.2 Interrupt Source
6.2.1 Interrupt Sources Connection
Figure 6-1 Interrupt Sources Connection
The Cortex-A15 has an external GIC which has 128 SPIs. GICs interrupt sources pass via INT_COMBINER block
that combines interrupt sources for GIC as shown in Figure 6-1.
Main CPU
(Dual Cortex-A15)
GIC_CPU
INT_COMBINER_CPU
nFIQ_cpu[1:0]
nIRQ_cpu[1:0]
nVIRQ_cpu[1:0]
nVFIQ_cpu[1:0]
[31:0]
……
[127:32]
SPI[127:0]
…… Raw interrupt...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-561.png "Page 562
Samsung Confidential
Exynos 5250_UM 6 Interrupt Controller
6-2
6.2 Interrupt Source
6.2.1 Interrupt Sources Connection
Figure 6-1 Interrupt Sources Connection
The Cortex-A15 has an external GIC which has 128 SPIs. GICs interrupt sources pass via INT_COMBINER block
that combines interrupt sources for GIC as shown in Figure 6-1.
Main CPU
(Dual Cortex-A15)
GIC_CPU
INT_COMBINER_CPU
nFIQ_cpu[1:0]
nIRQ_cpu[1:0]
nVIRQ_cpu[1:0]
nVFIQ_cpu[1:0]
[31:0]
……
[127:32]
SPI[127:0]
…… Raw interrupt...")
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Samsung Confidential
Exynos 5250_UM 6 Interrupt Controller
6-3
6.2.2 External GIC Interrupt Table
Softwared Generated Interrupts (SGIs[15:0], ID[15:0]), Private Peripheral Interrupts (PPIs[15:0], ID[31:16]) and
Shared Peripheral Interrupts (SPIs[127:0], ID[159:32]) are supported. For SPI, maximal 32 4 = 128 interrupt
requests shall be serviced. See the following table.
Table 6-2 External GIC Interrupt Table (SPI[127:32]: Non-Combined Interrupt)
SPI Port No ID Interrupt Source Source Block...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-562.png "Page 563
Samsung Confidential
Exynos 5250_UM 6 Interrupt Controller
6-3
6.2.2 External GIC Interrupt Table
Softwared Generated Interrupts (SGIs[15:0], ID[15:0]), Private Peripheral Interrupts (PPIs[15:0], ID[31:16]) and
Shared Peripheral Interrupts (SPIs[127:0], ID[159:32]) are supported. For SPI, maximal 32 4 = 128 interrupt
requests shall be serviced. See the following table.
Table 6-2 External GIC Interrupt Table (SPI[127:32]: Non-Combined Interrupt)
SPI Port No ID Interrupt Source Source Block...")
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Samsung Confidential
Exynos 5250_UM 6 Interrupt Controller
6-6
Table 6-3 External GIC Interrupt Table (SPI[31:0]: Combined Interrupt)
SPI Port No Id Int_e_combiner Interrupt Source Source Block
31 63 IntG31_1 EINT[15] –
IntG31_0 EINT[14] –
30 62 IntG30_1 EINT[13] –
IntG30_0 EINT[12] –
29 61 IntG29_1 EINT[11] –
IntG29_0 EINT[10] –
28 60 IntG28_1 EINT[9] –
IntG28_0 EINT[8] –
27 59 IntG27_1 EINT[7] –
IntG27_0 EINT[6] –
26 58 IntG26_1 EINT[5] –
IntG26_0 EINT[4] –
25 57
IntG25_3 MCT_G3...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-565.png "Page 566
Samsung Confidential
Exynos 5250_UM 6 Interrupt Controller
6-6
Table 6-3 External GIC Interrupt Table (SPI[31:0]: Combined Interrupt)
SPI Port No Id Int_e_combiner Interrupt Source Source Block
31 63 IntG31_1 EINT[15] –
IntG31_0 EINT[14] –
30 62 IntG30_1 EINT[13] –
IntG30_0 EINT[12] –
29 61 IntG29_1 EINT[11] –
IntG29_0 EINT[10] –
28 60 IntG28_1 EINT[9] –
IntG28_0 EINT[8] –
27 59 IntG27_1 EINT[7] –
IntG27_0 EINT[6] –
26 58 IntG26_1 EINT[5] –
IntG26_0 EINT[4] –
25 57
IntG25_3 MCT_G3...")
Samsung Confidential Exynos 5250_UM 6 Interrupt Controller 6-1 6 Interrupt Controller 6.1 Overview 6.1.1 Features of the Generic Interrupt Controller (GIC) Exynos 5250 adopts CoreLink GIC-400 Generic Interrupt Controller as a centralized resource for supporting and managing interrupts in a system. For GIC details, please refer to the following ARM documents. CoreLink GIC-400 Generic Interrupt Controller-Technical Reference Manual, Revision r0p0 ARM Generic Interrupt Controller-Architecture Specification, Architecture version 2.0 6.1.2 Implementation-Specific Configurable Features Software Generated Interrupts (SGIs), external Private Peripheral Interrupts for each processor (PPIs), internal PPI for each processor and Shared Peripheral Interrupts (SPIs) are supported. For SPI, maximal 32 4 = 128 interrupt requests shall be serviced. See the following the configuration table. Table 6-1 GIC Configuration Values Items Configuration Values AMBA Protocol AXI Software Generated Interrupts (SGI) 16 External Private Peripheral Interrupts (PPI) 8 (4 for each processor) Shared Peripheral Interrupts (SPI) 128 Priority Level 32 Legacy interrupt Support No Number of CPUs 2
Samsung Confidential
Exynos 5250_UM 6 Interrupt Controller
6-2
6.2 Interrupt Source
6.2.1 Interrupt Sources Connection
Figure 6-1 Interrupt Sources Connection
The Cortex-A15 has an external GIC which has 128 SPIs. GICs interrupt sources pass via INT_COMBINER block
that combines interrupt sources for GIC as shown in Figure 6-1.
Main CPU
(Dual Cortex-A15)
GIC_CPU
INT_COMBINER_CPU
nFIQ_cpu[1:0]
nIRQ_cpu[1:0]
nVIRQ_cpu[1:0]
nVFIQ_cpu[1:0]
[31:0]
……
[127:32]
SPI[127:0]
…… Raw interrupt sources
Samsung Confidential Exynos 5250_UM 6 Interrupt Controller 6-3 6.2.2 External GIC Interrupt Table Softwared Generated Interrupts (SGIs[15:0], ID[15:0]), Private Peripheral Interrupts (PPIs[15:0], ID[31:16]) and Shared Peripheral Interrupts (SPIs[127:0], ID[159:32]) are supported. For SPI, maximal 32 4 = 128 interrupt requests shall be serviced. See the following table. Table 6-2 External GIC Interrupt Table (SPI[127:32]: Non-Combined Interrupt) SPI Port No ID Interrupt Source Source Block 127 159 RP_TIMER – 126 158 CAM_B – 125 157 CAM_A – 124 156 MDMA1 – 123 155 Reserved – 122 154 Reserved – 121 153 MCT_L1 – 120 152 MCT_L0 – 119 151 G3D_IRQMMU – 118 150 G3D_IRQJOB – 117 149 G3D_IRQGPU – 116 148 Reserved – 115 147 SATA – 114 146 CEC – 113 145 DP1_1 – 112 144 INTFEEDCTRL_SSS – 111 143 PMU – 110 142 CAM_C – 109 141 SATAPMEREQ – 108 140 SATAPHY – 107 139 Reserved – 106 138 ADC0 – 105 137 SPDIF – 104 136 PCM2 – 103 135 PCM1 – 102 134 PCM0 – 101 133 AC97 – 100 132 I2S2 – 99 131 I2S1 – 98 130 I2S0 – 97 129 AUDIO_SS – 96 128 MFC –
Samsung Confidential Exynos 5250_UM 6 Interrupt Controller 6-4 SPI Port No ID Interrupt Source Source Block 95 127 HDMI – 94 126 MIXER – 93 125 EFNFCON_1 – 92 124 EFNFCON_0 – 91 123 G2D – 90 122 EFNFCON_DMA – 89 121 JPEG – 88 120 GSCL3 – 87 119 GSCL2 – 86 118 GSCL1 – 85 117 GSCL0 – 84 116 ROTATOR – 83 115 WDT_IOP – 82 114 MIPI_DSI_4LANE – 81 113 EFNFCON_DMA_ABORT – 80 112 MIPI_CSI_B – 79 111 MIPI_CSI_A – 78 110 SDMMC3 – 77 109 SDMMC2 – 76 108 SDMMC1 – 75 107 SDMMC0 – 74 106 USBOTG – 73 105 MIPI_HSI – 72 104 USB_DRD30 – 71 103 USB_HOST20 – 70 102 SPI2 – 69 101 SPI1 – 68 100 SPI0 – 67 99 CPU_nFIQ[1] – 66 98 CPU_nFIQ[0] – 65 97 TMU – 64 96 I2C HDMI – 63 95 I2C7 – 62 94 I2C6 – 61 93 I2C5 – 60 92 I2C4 – 59 91 I2C3/USI3 –
Samsung Confidential Exynos 5250_UM 6 Interrupt Controller 6-5 SPI Port No ID Interrupt Source Source Block 58 90 I2C2/USI2 – 57 89 I2C1/USI1 – 56 88 I2C0/USI0 – 55 87 MONOCNT – 54 86 UART3 – 53 85 UART2 – 52 84 UART1 – 51 83 UART0 – 50 82 GPIO_C2C – 49 81 Reserved – 48 80 Reserved – 47 79 GPIO – 46 78 GPIO_LB – 45 77 GPIO_RT – 44 76 RTC_TIC – 43 75 RTC_ALARM – 42 74 WDT – 41 73 RTIC – 40 72 TIMER4 – 39 71 TIMER3 – 38 70 TIMER2 – 37 69 TIMER1 – 36 68 TIMER0 – 35 67 PDMA1 – 34 66 PDMA0 – 33 65 MDMA0_CORE – 32 64 EINT16_31 External Interrupt
Samsung Confidential Exynos 5250_UM 6 Interrupt Controller 6-6 Table 6-3 External GIC Interrupt Table (SPI[31:0]: Combined Interrupt) SPI Port No Id Int_e_combiner Interrupt Source Source Block 31 63 IntG31_1 EINT[15] – IntG31_0 EINT[14] – 30 62 IntG30_1 EINT[13] – IntG30_0 EINT[12] – 29 61 IntG29_1 EINT[11] – IntG29_0 EINT[10] – 28 60 IntG28_1 EINT[9] – IntG28_0 EINT[8] – 27 59 IntG27_1 EINT[7] – IntG27_0 EINT[6] – 26 58 IntG26_1 EINT[5] – IntG26_0 EINT[4] – 25 57 IntG25_3 MCT_G3 – IntG25_2 MCT_G2 – IntG25_1 EINT[3] – IntG25_0 EINT[2] – 24 56 IntG24_7 Reserved – IntG24_6 SYSMMU_G2D[1] – IntG24_5 SYSMMU_G2D[0] – IntG24_4 Reserved – IntG24_3 Reserved – IntG24_2 SYSMMU_FIMC_LITE1[1] – IntG24_1 SYSMMU_FIMC_LITE1[0] – IntG24_0 EINT[1] – 23 55 IntG23_7 Reserved – IntG23_6 Reserved – IntG23_5 Reserved – IntG23_4 MCT_G1 – IntG23_3 MCT_G0 – IntG23_2 Reserved – IntG23_1 Reserved – IntG23_0 EINT[0] – 22 54 IntG22_7 CPU_nCNTVIRQ[1] – IntG22_6 CPU_nCTIIRQ[1] – IntG22_5 CPU_nCNTPSIRQ[1] – IntG22_4 CPU_nPMUIRQ[1] –
Samsung Confidential Exynos 5250_UM 6 Interrupt Controller 6-7 SPI Port No Id Int_e_combiner Interrupt Source Source Block IntG22_3 CPU_nCNTPNSIRQ[1] – IntG22_2 CPU_PARITYFAILSCU[1] – IntG22_1 CPU_nCNTHPIRQ[1] – IntG22_0 CPU_PARITYFAIL[1] – 21 53 IntG21_0 CPU_nIRQ[1] – 20 52 IntG20_0 CPU_nIRQ[0] – 19 51 IntG19_7 CPU_nRAMERRIRQ – IntG19_6 CPU_nAXIERRIRQ – IntG19_5 Reserved – IntG19_4 INT_COMB_ISP_GIC – IntG19_3 INT_COMB_IOP_GIC – IntG19_2 CCI_nERRORIRQ – IntG19_1 INT_COMB_ARMISP_GIC – IntG19_0 INT_COMB_ARMIOP_GIC – 18 50 IntG18_7 DISP1[3] – IntG18_6 DISP1[2] – IntG18_5 DISP1[1] – IntG18_4 DISP1[0] – IntG18_3 Reserved – IntG18_2 Reserved – IntG18_1 Reserved – IntG18_0 Reserved – 17 49 IntG17_7 Reserved – IntG17_6 Reserved – IntG17_5 Reserved – IntG17_4 Reserved – IntG17_3 SSCM_PULSE_IRQ_C2CIF[1] – IntG17_2 SSCM_PULSE_IRQ_C2CIF[0] – IntG17_1 SSCM_IRQ_C2CIF[1] – IntG17_0 SSCM_IRQ_C2CIF[0] – 16 48 IntG16_7 Reserved – IntG16_6 Reserved – IntG16_5 Reserved – IntG16_4 Reserved – IntG16_3 PEREV_M1_CDREX – IntG16_2 PEREV_M0_CDREX – IntG16_1 PEREV_A1_CDREX –
Samsung Confidential Exynos 5250_UM 6 Interrupt Controller 6-8 SPI Port No Id Int_e_combiner Interrupt Source Source Block IntG16_0 PEREV_A0_CDREX – 15 47 IntG15_7 Reserved – IntG15_6 Reserved – IntG15_5 Reserved – IntG15_4 Reserved – IntG15_3 MDMA0_ABORT – IntG15_2 Reserved – IntG15_1 Reserved – IntG15_0 Reserved – 14 46 IntG14_7 Reserved – IntG14_6 Reserved – IntG14_5 Reserved – IntG14_4 Reserved – IntG14_3 Reserved – IntG14_2 Reserved – IntG14_1 Reserved – IntG14_0 Reserved – 13 45 IntG13_7 Reserved – IntG13_6 Reserved – IntG13_5 Reserved – IntG13_4 Reserved – IntG13_3 Reserved – IntG13_2 Reserved – IntG13_1 MDMA1_ABORT – IntG13_0 Reserved – 12 44 IntG12_7 Reserved – IntG12_6 Reserved IntG12_5 Reserved IntG12_4 Reserved IntG12_3 Reserved IntG12_2 Reserved IntG12_1 Reserved IntG12_0 Reserved 11 43 IntG11_7 SYSMMU_DRCISP[1] – IntG11_6 SYSMMU_DRCISP[0] IntG11_5 Reserved IntG11_4 Reserved
Samsung Confidential Exynos 5250_UM 6 Interrupt Controller 6-9 SPI Port No Id Int_e_combiner Interrupt Source Source Block IntG11_3 Reserved IntG11_2 Reserved IntG11_1 SYSMMU_ODC[1] IntG11_0 SYSMMU_ODC[0] 10 42 IntG10_7 SYSMMU_ISP[1] – IntG10_6 SYSMMU_ISP[0] – IntG10_5 SYSMMU_DIS0[1] – IntG10_4 SYSMMU_DIS0[0] – IntG10_3 DP1 – IntG10_2 Reserved – IntG10_1 Reserved – IntG10_0 Reserved – 9 41 IntG9_7 Reserved – IntG9_6 Reserved – IntG9_5 SYSMMU_DIS1[1] – IntG9_4 SYSMMU_DIS1[0] – IntG9_3 Reserved – IntG9_2 Reserved – IntG9_1 Reserved – IntG9_0 Reserved – 8 40 IntG8_7 Reserved – IntG8_6 SYSMMU_MFCL[1] – IntG8_5 SYSMMU_MFCL[0] – IntG8_4 Reserved – IntG8_3 Reserved – IntG8_2 Reserved – IntG8_1 Reserved – IntG8_0 Reserved – 7 39 IntG7_7 Reserved – IntG7_6 Reserved – IntG7_5 SYSMMU_TV_M0[1] – IntG7_4 SYSMMU_TV_M0[0] – IntG7_3 SYSMMU_MDMA1[1] – IntG7_2 SYSMMU_MDMA1[0] – IntG7_1 SYSMMU_MDMA0[1] – IntG7_0 SYSMMU_MDMA0[0] – 6 38 IntG6_7 SYSMMU_SSS[1] –
Samsung Confidential Exynos 5250_UM 6 Interrupt Controller 6-10 SPI Port No Id Int_e_combiner Interrupt Source Source Block IntG6_6 SYSMMU_SSS[0] – IntG6_5 SYSMMU_RTIC[1] – IntG6_4 SYSMMU_RTIC[0] – IntG6_3 SYSMMU_MFCR[1] – IntG6_2 SYSMMU_MFCR[0] – IntG6_1 SYSMMU_ARM[1] – IntG6_0 SYSMMU_ARM[0] – 5 37 IntG5_7 SYSMMU_3DNR[1] – IntG5_6 SYSMMU_3DNR[0] – IntG5_5 SYSMMU_MCUISP[1] – IntG5_4 SYSMMU_MCUISP[0] – IntG5_3 SYSMMU_SCALERCISP[1] – IntG5_2 SYSMMU_SCALERCISP[0] – IntG5_1 SYSMMU_FDISP[1] – IntG5_0 SYSMMU_FDISP[0] – 4 36 IntG4_7 MCUIOP_CTIIRQ – IntG4_6 MCUIOP_PMUIRQ – IntG4_5 MCUISP_CTIIRQ – IntG4_4 MCUISP_PMUIRQ – IntG4_3 SYSMMU_JPEGX[1] – IntG4_2 SYSMMU_JPEGX[0] – IntG4_1 SYSMMU_ROTATOR[1] – IntG4_0 SYSMMU_ROTATOR[0] – 3 35 IntG3_7 SYSMMU_SCALERPISP[1] – IntG3_6 SYSMMU_SCALERPISP[0] – IntG3_5 SYSMMU_FIMC_LITE0[1] – IntG3_4 SYSMMU_FIMC_LITE0[0] – IntG3_3 SYSMMU_DISP1_M0[1] – IntG3_2 SYSMMU_DISP1_M0[0] – IntG3_1 SYSMMU_FIMC_LITE2[1] – IntG3_0 SYSMMU_FIMC_LITE2[0] – 2 34 IntG2_7 SYSMMU_GSCL3[1] – IntG2_6 SYSMMU_GSCL3[0] – IntG2_5 SYSMMU_GSCL2[1] – IntG2_4 SYSMMU_GSCL2[0] – IntG2_3 SYSMMU_GSCL1[1] – IntG2_2 SYSMMU_GSCL1[0] –