Samsung Exynos 5 User Manual

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-7  
1.4.1 ARM Core 
Exynos 5250 provides the latest ARM CPU core for high performance. 
 The ARM Cortex-A15 dual core processor uses ARMv7-A architecture with additional architecture extensions 
for MP and virtualization. 
 Owing to its ability to reach 1.7 GHz in speed, the Cortex-A15 dual core processor can meet requirements for 
performance-optimized consumer applications. It means 5,950 Dhrystone MIPS for each core (11,900 DMIPS 
in total), which is 40 per cent more DMIPS/MHz than the Cortex-A9. 
 The key features of ARM Cortex-A15 Dual Core include: 
 Advanced bus interface for maximum throughput: Support for synchronous 1/n clock ratios to reduce the 
latencies on high-speed processor designs (n: integer) 
 Advanced Single Instruction Multiple Data version 2 (SIMDv2) architecture extension for integer and 
floating-point vector operations  
 ARM NEON Advanced SIMD Instruction: Supports 64/128-bit registers with 8/16/32-bit Integer data and 
32-bit FP data formats and enlarging 32 double precision registers  
 High performance single or 16 double precision (D16) Floating Point Unit with VFPv4 architecture: 
Compatible with the IEEE 754 standard, VFPv2 (Cortex-A8), and VFP11 (ARM11)  
 Security extensions for enhanced security  
 Virtualization extensions for development of virtualized systems that enables switching of guest operating 
systems  
 Multi-Processing extensions for multiprocessing functionality  
 Multi-core ARM TrustZone technology with interrupt virtualization  
 ARM Generic Timer with 64-bit counter/timer and support for Virtualization Extensions (A15)  
 Program Trace Macrocell (PTM) based on the Program Flow Trace (PFT) v1.1 architecture  
 ARMv7.1 Debug architecture that includes support for Security Extensions and CoreSight 
 
 
  
						

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Exynos 5250_UM 1 Product Overview 
 1-8  
1.4.2 Memory Subsystem 
Exynos 5250 provides the leading memory bandwidth for mobile applications. 
 Mobile DDR3 (LPDDR3) Interface 
 Two ports x32 data bus with 800 MHz per pin, double data rate (DDR) 
 1.2 V interface voltage 
 Density: Maximum 4 GB by memory map limit, Recommend: Maximum 2 memory dice per port. 
NOTE: The max number of column address bits is 10. 
 
 Mobile DDR2 (LPDDR2) interface 
 Two ports x32 data bus with 533 MHz per pin and double data rate (DDR) 
 1.2 V interface voltage 
 Density: Maximum 4 GB by memory map limit, Recommend: Maximum 2 memory dice per port. 
NOTE: The max number of column address bits is 10. 
 
 DDR3/DDR3L Interface 
 Two ports x32 data bus with 800 MHz per pin and double data rate (DDR) 
 1.5 V/1.35 V interface voltage 
 Density: Maximum 4 GB by memory map limit, Recommend: Maximum 2 memory dice per port. 
NOTE: The max number of column address bits is 10. 
 
 eMMC and SD card interface 
 One channel 8-bit eMMC4.5 (1.8 V only)  
 One channel 4-bit SD3.0 (1.8 V only)  
 Two channel eMMC4.3/SD2.0 3.3 V/1.8 V interface voltage 
 EF-NAND3.0 interface 
 Two ports x8-bit data bus with up to 200 MHz per pin and double data rate (DDR) 
 Embedded internal ROM booting: The system does not need a booting device 
  
						

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-9  
1.4.3 Display Subsystem 
This section includes: 
 LCD Controller  
 eDisplayPort Interface  
 Digital TV Display  
 MIPI DSI Interface 
 
1.4.3.1 LCD Controller 
 Maximum resolution up to WQXGA (2560  1600) 
 Virtual screen size up to 16 MB pixels 
 Supports transparent overlay and real-time overlay plane multiplexing 
 Supports color key and simultaneous blend dual operations 
 Soft Scrolling: Horizontal one byte resolution and vertical one pixel resolution 
 Source Format: 
 Windows 0, 1, 2, 3 and 4 
o Supports 1, 2, 4, or 8-bpp (bits per pixel) palletized color 
o Supports 8, 16, 18, or 24-bpp non-palletized color 
o Supports RGB (8:8:8) 
 Palettes and Look-up tables 
 Five 256  32-bit (αRGB8888) palettes for windows 0 to 4 
 8-bit alpha blending 
 Bus Interface: 64-bit AMBA AXI master and 32-bit AMBA AHB slave 
 Supports 3D stereoscopic display 
 
  
						

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Exynos 5250_UM 1 Product Overview 
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1.4.3.2 eDisplayPort (eDP) Interface 
 Compliant with DisplayPortTM Specification, Version 1.1a. 
 Main link containing four physical lanes of 2.7/1.62 Gbps/lane 
 Bi-directional auxiliary link with up to one Mbps speed 
 Video Format: RGB 24bpp 
 Video slave mode 
 APB slave bus interface 
 Hot plug and unplug detection and link status monitor 
 Support VESA DMT and CVT timing standards 
 Built-in video BIST patterns 
 Specially designed low power PHY for mobile 
 
1.4.3.3 Digital TV Display 
 High Definition Multimedia Interface (HDMI) 1.4 compliant (with 3D) 
 Single-cable digital audio/video connection with a maximum bit rate of 4.46 Gbps 
 Supports 5.1-channel/96 KHz/24-bit audio 
 Supports 24-bit (RGB or YCbCr) color depth  
 Supports 480p, 576p, 720p, and 1080i/p 
 Supports HDMI stereoscopy 
 
1.4.3.4 MIPI DSI Interface 
 MIPI DSI Master v1.01_R11 (default) and r03 compliant 
 One port MIPI D-PHY v1.0: Four lanes, linked with MIPI DSI master 
 Tx bandwidth in high-speed mode: 80 Mbps to 920 Mbps per 1-lane 
 One data command bi-directional FIFO 
 Input format: RGB 24 bpp only 
 Output format: RGB 24 bpp 
 Maximum resolution: 1920  1200 (WUXGA) 
  
						

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Exynos 5250_UM 1 Product Overview 
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1.4.4 Camera and General Scaling Subsystem 
This section includes: 
 Camera Interface  
 General Scaler  
 MIPI CSI Interface 
 
1.4.4.1 Camera Interface 
 ITU-R BT 601 compliant 
 8-bit YCbCr422 input 
 MIPI CSI-2 Standard Specification v1.01r06 compliant with YUV, RGB, and Bayer Raw format input 
 One ITU camera input support and format: YCbCr422 or Bayer RAW 8/10/12/14-bit 
 Two MIPI CSI camera input support and format: YCbCr422 or Bayer RAW 8/10/12/14-bit 
 
1.4.4.2 General Scaler 
 DMA input and output support and format 
 YCbCr420: Two planes (Including tile) and three planes 
 YCbCr422: one plane, two planes 
 RGB888/RGB565 
 Maximum input resolution support 
 2048  2048 for Tile Mode or Rotation  
 4800  3344 for Other Cases 
 Built-in enhanced Color Space Conversion (CSC) engine 
 Input or Output image mirroring and rotation: 90°/180°/270° Rotation and X-Flip/Y-Flip 
 Scaling Algorithm: Vertical 4 taps/16 poly-phase filter, horizontal 8 taps/16 poly-phase filter 
 4 circular frame buffer support for DMA Read part 
 16 circular frame buffer support for DMA Write part 
 Supporting two local-out paths, which are FIMD1/MIXER. 
 Supporting two local-in paths, which are Camera/FIMD1. 
  
						

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Exynos 5250_UM 1 Product Overview 
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1.4.4.3 MIPI CSI Interface 
 MIPI CSI-2 Standard Specification v1.01r06 compliant 
 Two ports MIPI D-PHY v1.0: each port has 4-lanes, linked with MIPI CSI-2 slave 
 Rx bandwidth in high-speed mode: 80 Mbps to 920 Mbps per lane 
 Input formats 
 YUV422-8bit format 
 Bayer Raw 8/10/12/14 and Embedded 8-bit based packets 
 User-defined packets (for example, JPEG) 
 Output: 32-bit bus-width for parallel output 
 Three clock domains for SFR configuration, BYTECLK, and pixel clock assignment for ISP or camera 
 
 
  
						

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Exynos 5250_UM 1 Product Overview 
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1.4.5 Graphics, Multimedia Acceleration Hardware and Image Signal Processor 
This section includes: 
 3D Hardware Graphic Accelerator  
 2D Hardware Graphic Accelerator  
 Hardware Rotator 
 JPEG Hardware Codec 
 Multi Format Video Hardware Codec 
 Audio Subsystem 
 Image Signal Processor (ISP) Sub System 
 
1.4.5.1 3D Hardware Graphic Accelerator 
 A rich API feature set 
 An effective core for General Purpose GPU (GPGPU) applications 
 Leading memory bandwidth and power consumption for 3D graphics content 
 Scalability for products from smart phones to high-end mobile computing 
 Performance leading 3D graphics 
 Leading image quality with FP64 and anti-aliasing 
 Ease of integration, latency tolerance, and standard hardware interfaces 
 Versatile power management strategy, which you can tune to give the best power and performance 
combination for applications. Each core is individually power managed 
 
1.4.5.2 2D Hardware Graphic Accelerator 
 BitBLT: 
 Stretched BitBLT support using scale factor: Nearest sampling, smooth scaling (Bilinear sampling) 
 Memory-to-Memory BitBLT 
 Reverse Addressing: X Positive/Negative, Y Positive/Negative 
 Various repeat type support: Repeat, Reflect, Pad, Clamp, and None 
 Per-pixel Operation 
 Maximum 8000  8000 image size 
 Window clipping 
 90°/180°/270° Rotation and X-Flip/Y-Flip 
 Four operand Raster Operation (ROP4) 
 Alpha Blending: User-specified constant alpha value or per-pixel alpha value, Porter/Duff Rule support 
 Color Key: RGBA Color Key, YCbCr Color Key 
 Dithering 
 4 Pixel Pipeline 
 Data Format: 8/16/24/32-bpp, Packed 24-bpp Input/Output Color Format, and YCbCr format support  
						

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Exynos 5250_UM 1 Product Overview 
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1.4.5.3 Hardware Rotator 
 Supported image format: YCbCr422 (Interleave), YCbCr420 (non-interleave), RGB565, 
and RGB888 (unpacked) 
 Supported rotate degree: 90, 180, 270, flip vertical, and flip horizontal 
 
1.4.5.4 JPEG Hardware Codec 
 Encoding input format: YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0, RGB888, RGB565, or Gray 
 
1.4.5.5 Multi Format Video Hardware Codec 
 Full HD 60 fps capable of time-multiplexed, multi-stream, and multi-format encoding and decoding hardware 
 H.264 1080p 60 fps decoding: BP @ L4.2, MP @ L4.2, HP @ L4.2 
 H.264 1080p 60 fps encoding: BP @ L4.2, MP @ L4.2, HP @ L4.2 
 H.263 D1 30 fps decoding: Profile 3, Annex-I/J/K/T/D/F (except OBMC) support 
 H.263 D1 30 fps encoding: Baseline Profile 
 MPEG-4 1080p 30 fps decoding: SP, ASP @ L5, Xvid support 
 MPEG-4 1080p 30 fps encoding: SP, ASP @ L5 
 VC-1 1080p 30 fps decoding only: SP @ ML, MP @ HL, AP @ L3 
and WMV-9 conformant stream (except CP) 
 VP8 1080p 60fps decoding: Version0/1/2/3 
 MPEG-2 1080p 30 fps decoding only: MP @ HL and MPEG-1 support (except D-picture) 
 Encoder common features 
 [ 256,  256] ½  and ¼-pel accuracy motion estimation 
 B-picture support (number of B-pictures: 1 or 2) 
 16  16, 16  8, 8  16, and 8  8 block size support in H.264 
 Spatial mode of direct mode support in H.264 
 4 MV and unrestricted motion vector support in MPEG-4 
 Rate control support (Variable Bit-Rate and Constant Bit-Rate) 
 Cyclic intra refresh support 
 Decoder common features 
 Provides range mapping information for post-processing in VC-1 
 One warp point GMC support in MPEG-4 
 De-blocking filter for post-processing in MPEG-4 
 Error detection and concealment 
 Error resilience tool (re-sync marker and data partitioning with RVLC) support in MPEG-4 
 Video telephony (H.263) support up to D1 30 fps 
  
						

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
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1.4.5.6 Audio Subsystem 
 Low power audio subsystem 
 5.1 channel I2S with 32-bit width 64-depth FIFO 
 Hardware mixer mixes primary and secondary sounds 
 
1.4.5.7 Image Signal Processor (ISP) Sub System 
 Imaging subsystem to process image signal from an image sensor 
 Dedicated processor for controlling many sub-IPs: Cortex-A5 with Neon, 16 K I-Cache and 16 K D-Cache 
 Supported image resolution: 4808  3356 @ 15 fps, Full-HD @ 60 fps 
 Image processing 
 Demosaic 
 Denoise 
 Dynamic range compression 
 Image resizing 
 Optical distortion correction 
 Digital image stabilization: available only for less than full-HD 
 Inter-frame noise reduction 
 Face detection 
 System control feature 
 Interrupt controller of Cortex-A5 
 Watch Dog timer 
 Controller communicates with main host processor 
 Peripherals for sensor module control 
 Multi-PWM 6 channel 
 I2C 3 channel 
 SPI 2 channel 
 ADC 4 channel for motor control 
 UART for debugging 
 18 GPIO 
 Debugging system 
 Coresight for multi-core co-debugging 
 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
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1.4.6 Security Subsystem 
Exynos 5250 provides hardware engines and memories for security.  
 On-chip secure boot ROM: 64 KB ROM for secure boot 
 On-chip secure RAM: 352 KB secure RAM for security function 
 Hardware Crypto Accelerators: AES, DES/3DES, ARC4, SHA-1/SHA-256/MD5/HMAC/PRNG, TRNG, PKA, 
and Secure Key Manager 
 e-Fuse: 
 128-bit root key 
 112-bit Chip ID 
 24-bit Thermal Sensor 
 RTIC (Run-Time Integrity Check): Memory data integrity check during run-time. 
 Monotonic Counter: incremental counter for secure contents