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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-7  
14.4 I/O Description 
Signal I/O Description Pad Type 
SPI_0_CLK 
SPI_1_CLK 
SPI_2_CLK 
ISP_SPI_0_CLK 
ISP_SPI_1_CLK 
In/Out 
XspiCLK is the serial clock used to control time of 
data transfer. 
 
Out: W hen used as master 
In: W hen used as slave 
XspiCLK_0 
XspiCLK_1 
Xi2s2CDCLK 
XispSPICLK 
XispI2C1SDA 
muxed 
SPI_0_nSS 
SPI_1_nSS 
SPI_2_nSS 
ISP_SPI_0_nSS 
ISP_SPI_1_nSS 
In/Out 
Slave selection signal. All data Tx/Rx sequences 
are executed when XspiCS is set to low. 
 
Out: W hen used as master 
In: W hen used as slave 
XspiCSn_0 
XspiCSn_1 
Xi2s2LRCK 
XispSPICSn 
XispI2C1SCL 
muxed 
SPI_0_MISO 
SPI_1_MISO 
SPI_2_MISO 
ISP_SPI_0_MISO 
ISP_SPI_1_MISO 
In/Out 
This port is the input port in Master mode. Input 
mode is used to obtain data from slave output port. 
Data are transmitted to master through this port in 
slave mode. 
 
Out: W hen used as master 
In: W hen used as slave 
XspiMISO_0 
XspiMISO_1 
Xi2s2SDI 
XispSPIMISO 
XispGP4 
muxed 
SPI_0_MOSI 
SPI_1_MOSI 
SPI_2_MOSI 
ISP_SPI_0_MOSI 
ISP_SPI_1_MOSI 
In/Out 
This port is the output port in Master mode. This 
port is used to transfer data from master output 
port. Data are received from master through this 
port in slave mode. 
 
Out: W hen used as master 
In: W hen used as slave 
XspiMOSI_0 
XspiMOSI_1 
Xi2s2SDO 
XispSPIMOSI 
XispGP5 
muxed 
NOTE: Type field indicates if pads are dedicated to the signal or pads are connected to the multiplexed signals. The unused 
SPI ports are used as General Purpose I/O ports. Refer to Chapter 6 General Purpose I/O for more information.
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-8  
14.5 Register Description 
14.5.1 Register Map Summary  
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
Register Offset Description Reset Value 
CH_CFGn 0x0000 Specifies SPI configuration 0x0 
MODE_CFGn 0x0008 Specifies FIFO control 0x0 
CS_REGn 0x000C Specifies slave selection control 0x1 
SPI_INT_ENn 0x0010  Specifies interrupt enable 0x0 
SPI_STATUSn 0x0014 Specifies SPI status 0x0 
SPI_TX_DATAn 0x0018 Specifies Tx data 0x0 
SPI_RX_DATAn 0x001C Specifies Rx data 0x0 
PACKET_CNT_REGn 0x0020 Specifies packet count 0x0 
PENDING_CLR_REGn 0x0024 Specifies interrupt pending clear 0x0 
SW AP_CFGn 0x0028 Specifies swap configuration 0x0 
FB_CLK_SELn 0x002C Specifies feedback clock selection 0x0 
 
Setting Sequence of Special Function Register 
Steps to set Special Function Register (nCS manual mode): 
1. Set Transfer Type. (CPOL and CPHA set) 
2. Set Feedback Clock Selection register. 
3. Set SPI MODE_CFG register. 
4. Set SPI INT_EN register. 
5. Set PACKET_CNT_REG register if necessary. 
6. Set Tx or Rx Channel on. 
7. Set nSSout to low to start either Tx or Rx operation: 
 a. Set nSSout Bit to low, then start Tx data writing. 
 b. If auto chip selection bit is set, nSSout is controlled automatically.
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-9  
14.5.1.1 CH_CFGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0000, Reset Value = 0x0 
Name Bit Type Description Reset Value 
HIGH_SPEED_EN [6] RW 
Slave Tx output time control bit 
When this bit is enabled, slave Tx output time is 
reduced as much as half period of SPICLKout 
period. 
This bit is valid only in CPHA 0.  
0 = Disables      
1 = Enables 
0 
SW _RST [5] RW 
Software reset  
This bit clears these registers and bits.  
Rx/Tx FIFO Data, SPI_STATUS  
Once reset, this bit must be clear manually.  
0 = Inactive    
1 = Active 
0 
SLAVE [4] RW 
Whether SPI Port is Master or Slave  
0 = Master      
1 = Slave 
0 
CPOL [3] RW 
Determines whether active high or active low clock  
0 = Active High  
1 = Active Low 
0 
CPHA [2] RW 
Selects one of the two fundamentally different 
transfer formats  
0 = Format A    
1 = Format B 
0 
RX_CH_ON [1] RW 
SPI Rx Channel On  
0 = Channel Off              
1 = Channel On 
0 
TX_CH_ON [0] RW 
SPI Tx Channel On  
0 = Channel Off          
1 = Channel On 
0 
NOTE: SPI controller should reset when:  
1. Reconfiguration of SPI registers   
2. Error interrupt occurs 
3.  Before software reset using SW_RST, you should channel off.
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-10  
14.5.1.2 MODE_CFGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0008, Reset Value = 0x0 
Name Bit Type Description Reset Value 
CH_W IDTH [30:29] RW 
00 = Byte    
01 = Halfword  
10 = W ord        
11 = Reserved 
0 
TRAILING_CNT [28:19] RW Count value from writing the last data in Rx FIFO to 
flush trailing bytes in FIFO  0 
BUS_W IDTH [18:17] RW 
00 = Byte          
01 = Halfword  
10 = Word      
11 = Reserved 
0 
RX_RDY_LVL [16:11] RW 
Rx FIFO trigger level in INT mode.  
SPI Port 0 and ISP-SPI Port 0, 1: Trigger level 
(bytes) = 4  N 
SPI Port 1, 2: Trigger level (bytes) = N 
(N = value of RX_RDY_LVL field) 
0 
TX_RDY_LVL [10:5] RW 
Tx FIFO trigger level in INT mode.  
SPI Port 0 and ISP-SPI Port 0, 1: Trigger level 
(bytes) = 4  N 
SPI Port 1, 2: Trigger level (bytes) = N 
(N = value of TX_RDY_LVL field) 
0 
RSVD [4:3] –=oeserved==-=
RX_DMA_St=[2]=RW=
Rx=DMA mode=enable/disable =
0 ==Disables=DMA Mode    =
1 ==Enables DMA Mode=
0=
TX_DMA_St=[1]=RW=
Tx=DMA mode=enable/disable=
0 ==Disables=DMA Mode  = = = = ===
1 ==Enables DMA Mode =
0=
DMA_TYPb=[0]=RW=
DMA transfer type, single or 4 bursts.= ==
0===Single==
1===4 burst==
DMA transfer size must=be set as the same size in=
SPI DMA.=
0=
=
=
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-11  
NOTE:  
1. CH_WIDTH is shift-register width.  
2. BUS_WIDTH is SPI FIFO width. The transfer data size should be aligned with BUS_WIDTH. 
 For example, TX/RX data size must be aligned with 4 bytes if BUS_WIDTH is word.  
3. CH_WIDTH must be smaller than BUS_WIDTH or same.
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-12  
14.5.1.3 CS_REGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x000C, Reset Value = 0x1 
Name Bit Type Description Reset Value 
NCS_TIME_COUNT [9:4] RW NSSOUT inactive time = ((nCS_time_count + 3)/2) 
 SPICLKout 0 
RSVD [3:2] –=oeserved==–=
AUTO_N_MANUAi=[1]=RW=
Chip=select toggle manual or auto selection=
0== Manual=
1 = Auto=
0=
NSSOUT=[0]=RW=
Slave selection signal=(manual only)=
0== Active=
1 = Inactive=
1=
NOTE: If AUTO_N_MANUAL is set, SPI controller controls NSSOUT and data transfer is not performed continuously. Unit 
data size depends on CH_WIDTH. 
 
 Figure 14-3 illustrates Auto Chip Select Mode Waveform (CPOL = 0, CPHA = 0, CH_WIDTH = Byte). 
 
    Figure 14-3   Auto Chip Select Mode Waveform (CPOL = 0, CPHA = 0, CH_WIDTH = Byte) 
 
 SPICLK
MOSIMSB654321LSB
MSB654321LSB*MSBMISO
NSSOUT
*MSB654321*LSB
654321*LSB**MSB
NCS_TIME_COUNT
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-13  
14.5.1.4 SPI_INT_ENn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0010, Reset Value = 0x0 
Name Bit Type Description Reset Value 
INT_EN_TRAILING [6] RW 
Interrupt Enable for trailing count to be 0  
0 = Disables interrupt 
1 = Enables interrupt 
0 
INT_EN_RX_OVER
RUN [5] RW 
Interrupt Enable for RxOverrun  
0 = Disables interrupt 
1 = Enables interrupt 
0 
INT_EN_RX_UNDE
RRUN [4] RW 
Interrupt Enable for RxUnderrun  
0 = Disables interrupt 
1 = Enables interrupt 
0 
INT_EN_TX_OVER
RUN [3] RW 
Interrupt Enable for TxOverrun  
0 = Disables interrupt 
1 = Enables interrupt 
0 
INT_EN_TX_UNDE
RRUN [2] RW 
Interrupt Enable for TxUnderrun. In slave mode, this 
bit must be clear first after turning on slave Tx path.  
0 = Disables interrupt 
1 = Enables interrupt 
0 
INT_EN_RX_FIFO_
RDY [1] RW 
Interrupt Enable for RxFifoRdy (INT mode)  
0 = Disables interrupt 
1 = Enables interrupt 
0 
INT_EN_TX_FIFO_
RDY [0] RW 
Interrupt Enable for TxFifoRdy (INT mode)  
0 = Disables interrupt 
1 = Enables interrupt 
0
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-14  
14.5.1.5 SPI_STATUSn (n = 0 to 4)  
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0014, Reset Value = 0x0 
Name Bit Type Description Reset Value 
TX_DONE [25] R 
Indication of transfer done in Shift register (master 
mode only) 
0 = All case except Tx FIFO and shift register case 
1 = When Tx FIFO and shift register are empty after 
transmission start 
0 
TRAILING_BYTE [24] R Indication that trailing count is 0 0 
RX_FIFO_LVL [23:15] R 
Data level in Rx FIFO 
0 to 256 bytes in port 0 
0 to 64 bytes in port 1 and 2 
0 
TX_FIFO_LVL [14:6] R 
Data level in Tx FIFO 
0 to 256 bytes in port 0 
0 to 64 bytes in port 1 and 2 
0 
RX_OVERRUN [5] R 
Rx FIFO overrun error 
0 = No Error 
1 = Overrun   Error 
0 
RX_UNDERRUN [4] R 
Rx FIFO underrun error 
0 = No Error 
1 = Underrun Error 
0 
TX_OVERRUN [3] R 
Tx FIFO overrun error 
0 = No Error 
1 = Overrun Error 
0 
TX_UNDERRUN [2] R 
Tx FIFO underrun error 
0 = No Error 
1 = Underrun Error 
NOTE: Tx FIFO underrun error occurs when Tx 
FIFO is empty in slave mode. 
0 
RX_FIFO_RDY [1] R 0 = Data in FIFO less than trigger level 
1 = Data in FIFO more than trigger level 0 
TX_FIFO_RDY [0] R 0 = Data in FIFO more than trigger level 
1 = Data in FIFO less than trigger level 0
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-15  
14.5.1.6 SPI_TX_DATAn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0018, Reset Value = 0x0 
Name Bit Type Description Reset Value 
TX_DATA [31:0] W This field contains the data to be transmitted over 
the SPI channel. 0 
 
14.5.1.7 SPI_RX_DATAn (n = 0 to 4)  
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x001C, Reset Value = 0x0 
Name Bit Type Description Reset Value 
RX_DATA [31:0] R This field contains the data to be received over the 
SPI channel. 0 
 
14.5.1.8 PACKET_CNT_REGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0020, Reset Value = 0x0 
Name Bit Type Description Reset Value 
PACKET_CNT_EN [16] RW 
Enable bit for packet count 
0 = Disables 
1 = Enables 
0 
COUNT_VALUE [15:0] RW Packet count value 0
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-16  
14.5.1.9 PENDING_CLR_REGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0024, Reset Value = 0x0 
Name Bit Type Description Reset Value 
TX_UNDERRUN_CLR [4] RW 
TX underrun pending clear bit 
0 = Non-Clear 
1 = Clear 
0 
TX_OVERRUN_CLR [3] RW 
TX overrun pending clear bit  
0 = Non-Clear 
1 = Clear 
0 
RX_UNDERRUN_CLR [2] RW 
RX underrun pending clear bit  
0 = Non-clear 
1 = Clear 
0 
RX_OVERRUN_CLR [1] RW 
RX overrun pending clear bit  
0 = Non-Clear 
1 = Clear 
0 
TRAILING_CLR [0] RW 
Trailing pending clear bit  
0 = Non-Clear 
1 = Clear 
0 
NOTE: After error interrupt pending clear, the SPI controller should be reset.  
Error interrupt list: Tx underrun, Tx overrun, Rx underrun, and Rx overrun
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