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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-107  
Name Bit Type Description Reset Value 
_CON[2] 0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
RSVD [7] – Reserved 0x0 
EXT_INT13 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT13[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT13 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT13[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0
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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-108  
4.4.1.146 EXT_INT30CON 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0734, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
RSVD=[27]=–=Reserved=0x0=
EXT_INT13=
_CON[6]=[26:24]=RW=
Setting the signaling method=of EXT_INT30[6]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[23]=–=Reserved=0x0=
EXT_INT13=
_CON[5]=[22:20]=RW=
Setting the signaling method=of EXT_INT30[5]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[19]=–=Reserved=0x0=
EXT_INT13=
_CON[4]=[18:16]=RW=
Setting the signaling method=of EXT_INT30[4]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[15]=–=Reserved=0x0=
EXT_INT13=
_CON[3]=[14:12]=RW=
Setting the signaling method of EXT_INT30[3]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[11]=–=Reserved=0x0=
EXT_INT13=
_CON[2]=[10:8]=RW=
Setting the signaling method=of EXT_INT30[2]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[7]=–=Reserved=0x0=
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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-109  
Name Bit Type Description Reset Value 
EXT_INT13 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT30[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT13 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT30[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0
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Exynos 5250_UM 4 Pad Control 
 4-110  
4.4.1.147 EXT_INT1_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0800, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN1[3] [31] RW 
Enables Filter for EXT_INT1[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[3] [30:24] RW Filtering width of EXT_INT1[3] 0x00 
FLTEN1[2] [23] RW 
Enables Filter for EXT_INT1[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[2] [22:16] RW Filtering width of EXT_INT1[2] 0x00 
FLTEN1[1] [15] RW 
Enables Filter for EXT_INT1[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[1] [14:8] RW Filtering width of EXT_INT1[1] 0x00 
FLTEN1[0] [7] RW 
Enables Filter for EXT_INT1[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[0] [6:0] RW Filtering width of EXT_INT1[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-111  
4.4.1.148 EXT_INT1_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0804, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN1[7] [31] RW 
Enables Filter for EXT_INT1[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[7] [30:24] RW Filtering width of EXT_INT1[7] 0x00 
FLTEN1[6] [23] RW 
Enables Filter for EXT_INT1[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[6] [22:16] RW Filtering width of EXT_INT1[6] 0x00 
FLTEN1[5] [15] RW 
Enables Filter for EXT_INT1[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[5] [14:8] RW Filtering width of EXT_INT1[5] 0x00 
FLTEN1[4] [7] RW 
Enables Filter for EXT_INT1[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[4] [6:0] RW Filtering width of EXT_INT1[4] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-112  
4.4.1.149 EXT_INT2_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0808, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN2[3] [31] RW 
Enables Filter for EXT_INT2[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[3] [30:24] RW Filtering width of EXT_INT2[3] 0x00 
FLTEN2[2] [23] RW 
Enables Filter for EXT_INT2[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[2] [22:16] RW Filtering width of EXT_INT2[2] 0x00 
FLTEN2[1] [15] RW 
Enables Filter for EXT_INT2[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[1] [14:8] RW Filtering width of EXT_INT2[1] 0x00 
FLTEN2[0] [7] RW 
Enables Filter for EXT_INT2[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[0] [6:0] RW Filtering width of EXT_INT2[0] 0x00 
 
4.4.1.150 EXT_INT2_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x080C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0000=
FLTEN2[5]=[15]=RW=
Enables Filter=for EXT_INT2[5]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH2[5]=[14:8]=RW=Filtering width of EXT_INT2[5]=0x00=
FLTEN2[4]=[7]=RW=
Enables Filter=for EXT_INT2[4]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH2[4]=[6:0]=RW=Filtering=width of EXT_INT2[4]=0x00=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-113  
4.4.1.151 EXT_INT3_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0810, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN3[3] [31] RW 
Enables Filter for EXT_INT3[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[3] [30:24] RW Filtering width of EXT_INT3[3] 0x00 
FLTEN3[2] [23] RW 
Enables Filter for EXT_INT3[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[2] [22:16] RW Filtering width of EXT_INT3[2] 0x00 
FLTEN3[1] [15] RW 
Enables Filter for EXT_INT3[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[1] [14:8] RW Filtering width of EXT_INT3[1] 0x00 
FLTEN3[0] [7] RW 
Enables Filter for EXT_INT3[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[0] [6:0] RW Filtering width of EXT_INT3[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-114  
4.4.1.152 EXT_INT3_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0814, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN3[7] [31] RW 
Enables Filter for EXT_INT3[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[7] [30:24] RW Filtering width of EXT_INT3[7] 0x00 
FLTEN3[6] [23] RW 
Enables Filter for EXT_INT3[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[6] [22:16] RW Filtering width of EXT_INT3[6] 0x00 
FLTEN3[5] [15] RW 
Enables Filter for EXT_INT3[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[5] [14:8] RW Filtering width of EXT_INT3[5] 0x00 
FLTEN3[4] [7] RW 
Enables Filter for EXT_INT3[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[4] [6:0] RW Filtering width of EXT_INT3[4] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-115  
4.4.1.153 EXT_INT4_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0818, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN4[3] [31] RW 
Enables Filter for EXT_INT4[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[3] [30:24] RW Filtering width of EXT_INT4[3] 0x00 
FLTEN4[2] [23] RW 
Enables Filter for EXT_INT4[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[2] [22:16] RW Filtering width of EXT_INT4[2] 0x00 
FLTEN4[1] [15] RW 
Enables Filter for EXT_INT4[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[1] [14:8] RW Filtering width of EXT_INT4[1] 0x00 
FLTEN4[0] [7] RW 
Enables Filter for EXT_INT4[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[0] [6:0] RW Filtering width of EXT_INT4[0] 0x00 
 
4.4.1.154 EXT_INT4_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x081C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
FLTEN4[4]=[7]=RW=
Enables Filter=for EXT_INT4[4]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH4[4]=[6:0]=RW=Filtering width of EXT_INT4[4]=0x00=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-116  
4.4.1.155 EXT_INT5_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0820, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN5[3] [31] RW 
Enables Filter for EXT_INT5[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[3] [30:24] RW Filtering width of EXT_INT5[3] 0x00 
FLTEN5[2] [23] RW 
Enables Filter for EXT_INT5[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[2] [22:16] RW Filtering width of EXT_INT5[2] 0x00 
FLTEN5[1] [15] RW 
Enables Filter for EXT_INT5[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[1] [14:8] RW Filtering width of EXT_INT5[1] 0x00 
FLTEN5[0] [7] RW 
Enables Filter for EXT_INT5[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[0] [6:0] RW Filtering width of EXT_INT5[0] 0x00 
 
4.4.1.156 EXT_INT5_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0824, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
FLTEN5[4]=[7]=RW=
Enables Filter=for EXT_INT5[4]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH5[4]=[6:0]=RW=Filtering width of EXT_INT5[4]=0x00=
=
=
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