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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-287  
4.4.1.414 EXT_INT62_FLTCON0 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0810, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN3[3] [31] RW 
Enables Filter for EXT_INT62[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[3] [30:24] RW Filtering width of EXT_INT62[3] 0x00 
FLTEN3[2] [23] RW 
Enables Filter for EXT_INT62[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[2] [22:16] RW Filtering width of EXT_INT62[2] 0x00 
FLTEN3[1] [15] RW 
Enables Filter for EXT_INT62[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[1] [14:8] RW Filtering width of EXT_INT62[1] 0x00 
FLTEN3[0] [7] RW 
Enables Filter for EXT_INT62[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[0] [6:0] RW Filtering width of EXT_INT62[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-288  
4.4.1.415 EXT_INT62_FLTCON1 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0814, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN3[7] [31] RW 
Enables Filter for EXT_INT62[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[7] [30:24] RW Filtering width of EXT_INT62[7] 0x00 
FLTEN3[6] [23] RW 
Enables Filter for EXT_INT62[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[6] [22:16] RW Filtering width of EXT_INT62[6] 0x00 
FLTEN3[5] [15] RW 
Enables Filter for EXT_INT62[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[5] [14:8] RW Filtering width of EXT_INT62[5] 0x00 
FLTEN3[4] [7] RW 
Enables Filter for EXT_INT62[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[4] [6:0] RW Filtering width of EXT_INT62[4] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-289  
4.4.1.416 EXT_INT63_FLTCON0 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0818, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN4[3] [31] RW 
Enables Filter for EXT_INT63[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[3] [30:24] RW Filtering width of EXT_INT63[3] 0x00 
FLTEN4[2] [23] RW 
Enables Filter for EXT_INT63[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[2] [22:16] RW Filtering width of EXT_INT63[2] 0x00 
FLTEN4[1] [15] RW 
Enables Filter for EXT_INT63[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[1] [14:8] RW Filtering width of EXT_INT63[1] 0x00 
FLTEN4[0] [7] RW 
Enables Filter for EXT_INT63[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[0] [6:0] RW Filtering width of EXT_INT63[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-290  
4.4.1.417 EXT_INT63_FLTCON1 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x081C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN4[7] [31] RW 
Enables Filter for EXT_INT63[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[7] [30:24] RW Filtering width of EXT_INT63[7] 0x00 
FLTEN4[6] [23] RW 
Enables Filter for EXT_INT63[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[6] [22:16] RW Filtering width of EXT_INT63[6] 0x00 
FLTEN4[5] [15] RW 
Enables Filter for EXT_INT63[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[5] [14:8] RW Filtering width of EXT_INT63[5] 0x00 
FLTEN4[4] [7] RW 
Enables Filter for EXT_INT63[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[4] [6:0] RW Filtering width of EXT_INT63[4] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-291  
4.4.1.418 EXT_INT64_FLTCON0 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0820, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0000=
FLTEN5[1]=[15]=RW=
Enables Filter for EXT_INT64[1]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH5[1]=[14:8]=RW=Filtering width of EXT_INT64[1]=0x00=
FLTEN5[0]=[7]=RW=
Enables Filter=for EXT_INT64[0]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH5[0]=[6:0]=RW=Filtering width of EXT_INT64[0]=0x00=
=
4.4.1.419 EXT_INT64_FLTCON1 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0824, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-292  
4.4.1.420 EXT_INT60_MASK 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0900, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
EXT_INT60=
_MASK[7]=[7]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT60=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT60=
_MASK[5]=[5]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT60=
_MASK[4]=[4]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT60=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT60=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT60=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT60=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-293  
4.4.1.421 EXT_INT61_MASK 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0904, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
EXT_INT61=
_MASK[7]=[7]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT61=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT61=
_MASK[5]=[5]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT61=
_MASK[4]=[4]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT61=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT61=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT61=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT61=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-294  
4.4.1.422 EXT_INT62_MASK 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0908, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
EXT_INT62=
_MASK[7]=[7]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT62=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT62=
_MASK[5]=[5]=RW=0x0== Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT62=
_MASK[4]=[4]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT62=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT62=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT62=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT62=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-295  
4.4.1.423 EXT_INT63_MASK 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x090C, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
EXT_INT63=
_MASK[7]=[7]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT63=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT63=
_MASK[5]=[5]=RW=0x0== Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT63=
_MASK[4]=[4]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT63=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT63=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT63=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT63=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
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Exynos 5250_UM 4 Pad Control 
 4-296  
4.4.1.424 EXT_INT64_MASK 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0910, Reset Value = 0x0000_0003 
Name Bit Type Description Reset Value 
RSVD [31:2] –=Reserved=0x00000000=
EXT_INT64=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT64=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
4.4.1.425 EXT_INT60_PEND 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0A00, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
EXT_INT60=
_PEND[7]=[7]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT60=
_PEND[6]=[6]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT60=
_PEND[5]=[5]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT60=
_PEND[4]=[4]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT60=
_PEND[3]=[3]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT60=
_PEND[2]=[2]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT60=
_PEND[1]=[1]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
EXT_INT60=
_PEND[0]=[0]=RWu=0x0 = Does not=occur=
0x1 = Interrupt occurs=0x0=
=
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