Samsung Exynos 5 User Manual

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-13  
7.5.1.4 IMSR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x000C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
SYSMMU_SCALERPISP[1] [31] R 
Masked interrupt pending status  
If the corresponding interrupt enable bit is set to 
0, the IMSR bit is read out as 0. 
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
SYSMMU_SCALEoPISP[0]=[30]=o=–=
SYSMMU_FIMC_LITE0[1]=[29]=o=–=
SYSMMU_FIMC_LITE0[0]=[28]=o=–=
SYSMMU_DISP1_M0[1]=[27]=o=–=
SYSMMU_DISP1_M0[0]=[26]=o=–=
SYSMMU_FIMC_LITE2[1]=[25]=o=–=
SYSMMU_FIMC_LITE2[0]=[24]=o=–=
SYSMMU_GSCL3[1]=[25]=o=
Masked interrupt pending status =
If the corresponding interrupt enable bit is=set to=
0, the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
SYSMMU_GSCL3[0]=[24]=o=–=
SYSMMU_GSCL2[1]=[23]=o=–=
SYSMMU_GSCL2[0]=[20]=o=–=
SYSMMU_GSCL1[1]=[19]=o=–=
SYSMMU_GSCL1[0]=[18]=o=–=
SYSMMU_GSCL0[1]=[17]=o=–=
SYSMMU_GSCL0[0]=[16]=o=–=
CPU_nCNTVIRQ[0]=[15]=o=
Masked interrupt pending status =
If the corresponding interrupt enable bit is=set to=
0, the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
CPU_nCNTPSIRQ[0]=[14]=o=–=
CPU_nCNTPSNIRQ[0]=[13]=o=–=
CPU_nCNTHPIRQ[0]=[12]=o=–=
CPU_nCTIIRQ[0]=[11]=o=–=
CPU_nPMUIRQ[0]=[10]=o=–=
CPU_PARITYFAILSCU[0]=[9]=o=–=
CPU_PARITYFAIL0=[8]=o=–=
TZASC_XR1BXt=[7]=o=
Masked interrupt pending status =
If the=corresponding interrupt enable bit is=set to=
0, the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
TZASC_XR1BXo=[6]=o=–=
TZASC_XLBXW=[5]=o=–=
TZASC_XLBXR=[4]=o=–=
TZASC_DRBXW=[3]=o=–=
TZASC_DRBXR=[2]=o=–=
TZASC_CBXt=[1]=o=–=
TZASC_CBXo=[0]=o=–=
= 
						

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-14  
7.5.1.5 IESR1 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0010, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 ==Masks=
1===Enables=
–=
RSVD=[30]=–=–=
SYSMMU_TV_M0[1]=[29]=RW=0=
SYSMMU_TV_M0x0]=[28]=RW=0=
SYSMMU_MDMA1[1]=[27]=RW=0=
SYSMMU_MDMA1[0]=[26]=RW=0=
SYSMMU_MDMA0[1]=[25]=RW=0=
SYSMMU_MDMA0[0]=[24]=RW=0=
SYSMMU_SSp[1]=[23]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
0=
SYSMMU_SSS[0]=[22]=RW=0=
pYSMMU_RTIC[1]=[21]=RW=0=
pYSMMU_RTIC[0]=[20]=RW=0=
SYSMMU_MFCR[1]=[19]=RW=0=
SYSMMU_MFCR[0]=[18]=RW=0=
SYSMMU_ARM[1]=[17]=RW=0=
SYSMMU_ARM[0]=[16]=RW=0=
pYSMMU_3DNR[1]=[15]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
0=
pYSMMU_3DNR[0]=[14]=RW=0=
SYSMMU_MCUISP[1]=[13]=RW=0=
SYSMMU_MCUISP[0]=[12]=RW=0=
SYSMMU_SCALERCISP[1]=[11]=RW=0=
SYSMMU_SCALERCISP[0]=[10]=RW=0=
SYSMMU_FDISP[1]=[9]=RW=0=
SYSMMU_FDISP[0]=[8]=RW=0=
MCUIOP_CTIIRQ=[7]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
0=
MCUIOP_PMUIRQ=[6]=RW=0=
MCUISP_CTIIRQ=[5]=RW=0=
MCUISP_PMUIRQ=[4]=RW=0=
pYSMMU_JPEGX[1]=[3]=RW=0=
pYSMMU_JPEGX[0]=[2]=RW=0=
pYSMMU_ROTATOR[1]=[1]=RW=0=
pYSMMU_ROTATOR[0]=[0]=RW=0=
= 
						

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-15  
7.5.1.6 IECR1 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0014, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is=cleared, the=
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
oSVa=[30]=–=–=
SYSMMU_TV_M0[1]=[29]=RW=0=
SYSMMU_TV_M0x0]=[28]=RW=0=
SYSMMU_MDMA1[1]=[27]=RW=0=
SYSMMU_MDMA1[0]=[26]=RW=0=
SYSMMU_MDMA0[1]=[25]=RW=0=
SYSMMU_MDMA0[0]=[24]=RW=0=
SYSMMU_SSp[1]=[23]=RW=Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enabled=
0=
SYSMMU_SSS[0]=[22]=RW=0=
pYSMMU_RTIC[1]=[21]=RW=0=
pYSMMU_RTIC[0]=[20]=RW=0=
SYSMMU_MFCR[1]=[19]=RW=0=
SYSMMU_MFCR[0]=[18]=RW=0=
SYSMMU_ARM[1]=[17]=RW=0=
SYSMMU_ARM[0]=[16]=RW=0=
pYSMMU_3DNR[1]=[15]=RW=Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enabled=
0=
pYSMMU_3DNR[0]=[14]=RW=0=
SYSMMU_MCUISP[1]=[13]=RW=0=
SYSMMU_MCUISP[0]=[12]=RW=0=
SYSMMU_SCALERCISP[1]=[11]=RW=0=
SYSMMU_SCALERCISP[0]=[10]=RW=0=
SYSMMU_FDISP[1]=[9]=RW=0=
SYSMMU_FDISP[0]=[8]=RW=0=
MCUIOP_CTIIRQ=[7]=RW=Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enabled=
0=
MCUIOP_PMUIRQ=[6]=RW=0=
MCUISP_CTIIRQ=[5]=RW=0=
MCUISP_PMUIRQ=[4]=RW=0=
pYSMMU_JPEGX[1]=[3]=RW=0=
pYSMMU_JPEGX[0]=[2]=RW=0=
pYSMMU_ROTATOR[1]=[1]=RW=0=
pYSMMU_ROTATOR[0]=[0]=RW=0=
= 
						

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-16  
7.5.1.7 ISTR1 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0018, Reset Value = Undefined 
Name Bit Type Description Reset Value 
RSVD [31] –=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
oSVa=[30]=–=–=
SYSMMU_TV_M0[1]=[29]=o=–=
SYSMMU_TV_M0x0]=[28]=o=–=
SYSMMU_MDMA1[1]=[27]=o=–=
SYSMMU_MDMA1[0]=[26]=o=–=
SYSMMU_MDMA0[1]=[25]=o=–=
SYSMMU_MDMA0[0]=[24]=o=–=
SYSMMU_SSp[1]=[23]=o=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
SYSMMU_SSS[0]=[22]=o=–=
pYSMMU_RTIC[1]=[21]=o=–=
pYSMMU_RTIC[0]=[20]=o=–=
SYSMMU_MFCR[1]=[19]=o=–=
SYSMMU_MFCR[0]=[18]=o=–=
SYSMMU_ARM[1]=[17]=o=–=
SYSMMU_ARM[0]=[16]=o=–=
pYSMMU_3DNR[1]=[15]=o=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
pYSMMU_3DNR[0]=[14]=o=–=
SYSMMU_MCUISP[1]=[13]=o=–=
SYSMMU_MCUISP[0]=[12]=o=–=
SYSMMU_SCALERCISP[1]=[11]=o=–=
SYSMMU_SCALERCISP[0]=[10]=o=–=
SYSMMU_FDISP[1]=[9]=o=–=
SYSMMU_FDISP[0]=[8]=o=–=
MCUIOP_CTIIRQ=[7]=o=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
MCUIOP_PMUIRQ=[6]=o=–=
MCUISP_CTIIRQ=[5]=o=–=
MCUISP_PMUIRQ=[4]=o=–=
pYSMMU_JPEGX[1]=[3]=o=–=
pYSMMU_JPEGX[0]=[2]=o=–=
pYSMMU_ROTATOR[1]=[1]=o=–=
pYSMMU_ROTATOR[0]=[0]=o=–=
= 
						

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-17  
7.5.1.8 IMSR1 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x001C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
RSVD [31] –=
Masked interrupt pending status =
If=the corresponding interrupt enable bit is 0,=
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
oSVa=[30]=–=–=
SYSMMU_TV_M0[1]=[29]=o=–=
SYSMMU_TV_M0x0]=[28]=o=–=
SYSMMU_MDMA1[1]=[27]=o=–=
SYSMMU_MDMA1[0]=[26]=o=–=
SYSMMU_MDMA0[1]=[25]=o=–=
SYSMMU_MDMA0[0]=[24]=o=–=
SYSMMU_SSp[1]=[23]=o=
Masked interrupt pending status =
If=the corresponding interrupt enable bit is 0,=
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
SYSMMU_SSS[0]=[22]=o=–=
pYSMMU_RTIC[1]=[21]=o=–=
pYSMMU_RTIC[0]=[20]=o=–=
SYSMMU_MFCR[1]=[19]=o=–=
SYSMMU_MFCR[0]=[18]=o=–=
SYSMMU_ARM[1]=[17]=o=–=
SYSMMU_ARM[0]=[16]=o=–=
pYSMMU_3DNR[1]=[15]=o=
Masked interrupt pending status =
If=the corresponding interrupt enable bit is 0,=
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
pYSMMU_3DNR[0]=[14]=o=–=
SYSMMU_MCUISP[1]=[13]=o=–=
SYSMMU_MCUISP[0]=[12]=o=–=
SYSMMU_SCALERCISP[1]=[11]=o=–=
SYSMMU_SCALERCISP[0]=[10]=o=–=
SYSMMU_FDISP[1]=[9]=o=–=
SYSMMU_FDISP[0]=[8]=o=–=
MCUIOP_CTIIRQ=[7]=o=
Masked interrupt pending status =
If=the corresponding interrupt enable bit is 0,=
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
MCUIOP_PMUIRQ=[6]=o=–=
MCUISP_CTIIRQ=[5]=o=–=
MCUISP_PMUIRQ=[4]=o=–=
pYSMMU_JPEGX[1]=[3]=o=–=
pYSMMU_JPEGX[0]=[2]=o=–=
pYSMMU_ROTATOR[1]=[1]=o=–=
pYSMMU_ROTATOR[0]=[0]=o=–=
= 
						

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-18  
7.5.1.9 IESR2 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0020, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
SYSMMU_DRCISP[1] [31] RW Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the 
interrupt request is served. 
Write 
0 = Does not change the current setting 
1 = Sets the interrupt enable bit to 1 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
SYSMMU_DRCISP[0] [30] RW 0 
RSVD [29] –=–=
oSVa=[28]=–=–=
oSVa=[27]=–=–=
oSVa=[26]=–=–=
SYSMMU_ODC[1]=[25]=RW=0=
SYSMMU_ODC[0]=[24]=RW=0=
SYSMMU_ISP[1]=[23]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt=enable bit is set to 1, the 
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
0=
SYSMMU_ISP[0]=[22]=RW=0=
pYSMMU_DIS0[1]=[21]=RW=0=
pYSMMU_DIS0[0]=[20]=RW=0=
aP1=[19]=RW=0=
oSVa=[18]=–=–=
oSVa=[17]=–=–=
oSVa=x16]=–=–=
oSVa=[15]=–=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
oSVa=[14]=–=–=
SYSMMU_DIS1[1]=[13]=RW=0=
pYSMMU_DIS1[0]=[12]=RW=0=
oSVa=[11]=–=–=
oSVa=[10]=–=–=
oSVa=[9]=–=–=
oSVa=[8]=–=–=
oSVa=[7]=–=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
pYSMMU_MFCL[1]=[6]=RW=0=
pYSMMU_MFCL[0]=[5]=RW=0=
oSVa=[4]=–=–=
oSVa=[3]=–=–=
oSVa=[2]=–=–=
oSVa=[1]=–=–=
oSVa=[0]=–=–=
= 
						

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-19  
7.5.1.10 IECR2 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0024, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
SYSMMU_DRCISP[1] [31] RW Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked. 
Write 
0 = Does not change the current setting 
1 = Clear the interrupt enable bit to 0 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
SYSMMU_DRCISP[0] [30] RW 0 
RSVD [29] –=0=
oSVa=[28]=–=0=
oSVa=[27]=–=0=
oSVa=[26]=–=0=
SYSMMU_ODC[1]=[25]=RW=0=
SYSMMU_ODC[0]=[24]=RW=0=
SYSMMU_ISP[1]=[23]=RW=Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clear=the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
0=
SYSMMU_ISP[0]=[22]=RW=0=
pYSMMU_DIS0[1]=[21]=RW=0=
pYSMMU_DIS0[0]=[20]=RW=0=
aP1=[19]=RW=0=
oSVa=[18]=–=–=
oSVa=[17]=–=–=
oSVa=x16]=–=–=
oSVa=[15]=–=Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clear=the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
oSVa=[14]=–=–=
SYSMMU_DIS1[1]=[13]=RW=0=
pYSMMU_DIS1[0]=[12]=RW=0=
oSVa=[11]=–=–=
oSVa=[10]=–=–=
oSVa=[9]=–=–=
oSVa=[8]=–=–=
oSVa=[7]=–=Clear the corresponding interrupt enable bit to=
0. If=the interrupt enable bit is cleared, the=
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clear=the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
pYSMMU_MFCL[1]=[6]=RW=0=
pYSMMU_MFCL[0]=[5]=RW=0=
oSVa=[4]=–=–=
oSVa=[3]=–=–=
oSVa=[2]=–=–=
oSVa=[1]=–=–=
oSVa=[0]=–=–=
= 
						

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-20  
7.5.1.11 ISTR2 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0028, Reset Value = Undefined 
Name Bit Type Description Reset Value 
SYSMMU_DRCISP[1] [31] R 
Interrupt pending status  
The corresponding interrupt enable bit does not 
affect this pending status.  
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
SYSMMU_DRCISP[0]=[30]=o=–=
oSVa=[29]=–=–=
oSVa=[28]=–=–=
oSVa=[27]=–=–=
oSVa=[26]=–=–=
SYSMMU_ODC[1]=[25]=o=–=
SYSMMU_ODC[0]=[24]=o=–=
SYSMMU_ISP[1]=[23]=o=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
SYSMMU_ISP[0]=[22]=o=–=
pYSMMU_DIS0[1]=[21]=o=–=
pYSMMU_DIS0[0]=[20]=o=–=
aP1=[19]=o=–=
oSVa=[18]=–=–=
oSVa=[17]=–=–=
oSVa=x16]=–=–=
oSVa=[15]=–=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
oSVa=[14]=–=–=
SYSMMU_DIS1[1]=[13]=o=–=
pYSMMU_DIS1[0]=[12]=o=–=
oSVa=[11]=–=–=
oSVa=[10]=–=–=
oSVa=[9]=–=–=
oSVa=[8]=–=–=
oSVa=[7]=–=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
pYSMMU_MFCL[1]=[6]=o=–=
pYSMMU_MFCL[0]=[5]=o=–=
oSVa=[4]=–=–=
oSVa=[3]=–=–=
oSVa=[2]=–=–=
oSVa=[1]=–=–=
oSVa=[0]=–=–=
= 
						

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-21  
7.5.1.12 IMSR2 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x002C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
SYSMMU_DRCISP[1] [31] R 
Masked interrupt pending status  
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.  
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
SYSMMU_DRCISP[0]=[30]=o=–=
oSVa=[29]=–=–=
oSVa=[28]=–=–=
oSVa=[27]=–=–=
oSVa=[26]=–=–=
SYSMMU_ODC[1]=[25]=o=–=
SYSMMU_ODC[0]=[24]=o=–=
SYSMMU_ISP[1]=[23]=o=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
SYSMMU_ISP[0]=[22]=o=–=
pYSMMU_DIS0[1]=[21]=o=–=
pYSMMU_DIS0[0]=[20]=o=–=
aP1=[19]=o=–=
oSVa=[18]=–=–=
oSVa=[17]=–=–=
oSVa=x16]=–=–=
oSVa=[15]=–=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
oSVa=[14]=–=–=
SYSMMU_DIS1[1]=[13]=o=–=
pYSMMU_DIS1[0]=[12]=o=–=
oSVa=[11]=–=–=
oSVa=[10]=–=–=
oSVa=[9]=–=–=
oSVa=[8]=–=–=
oSVa=[7]=–=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
pYSMMU_MFCL[1]=[6]=o=–=
pYSMMU_MFCL[0]=[5]=o=–=
oSVa=[4]=–=–=
oSVa=[3]=–=–=
oSVa=[2]=–=–=
oSVa=[1]=–=–=
oSVa=[0]=–=–=
= 
						

							Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-22  
7.5.1.13 IESR3 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0030, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
MDMA0_ABORT=[27]=RW=0=
RSVD=[2S:10]=–=–=
MDMA1_ABORT=[9]=RW=0=
RSVD=[8:0]=–=–=
=
7.5.1.14 IECR3 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0034, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
MDMA0_ABORT=[27]=RW=0=
RSVD=[2S:10]=–=–=
MDMA1_ABORT=[9]=RW=0=
RSVD=[8:0]=–=–=
=
=