Samsung Exynos 5 User Manual

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-5  
5.2.2 Clocks from CMU 
CMUs generate internal clocks with intermediate frequencies using clocks from the clock pads (i.e., XRTCXTI and 
XXTI), seven PLLs (i.e., APLL, MPLL, BPLL, CPLL, EPLL, GPLL and VPLL) and USB PHY and HDMI PHY 
clocks. Some of these clocks can be selected, pre-scaled, and provided to the corresponding modules.  
It is recommended to use 24 MHz input clock source for APLL, MPLL, BPLL, CPLL, EPLL, GPLL and VPLL. 
In typical Exynos 5250 applications, 
 E4D Dual-core, CoreSight, and HPM use APLL 
 DRAM, System Bus clocks, and other peripheral clocks (for example Audio IPs and SPI) use MPLL and 
EPLL. 
 Video clock uses VPLL 
 G3D uses GPLL as input clock source 
 MFC uses CPLL as input clock source 
 
To generate internal clocks, these configurations are used:. 
 APLL uses XXTI as input and generate 22 MHz to 1.7GHz. This PLL generates 1.7 GHz clock to E4D Dual-
core CPU. 
 MPLL uses XXTI as input to generate 22 MHz to 1.6 GHz. This PLL generates 1.6 GHz clock to provide 400 
MHz/533 MHz/800 MHz for DRAM memory controller, LPDDR Phy, and G3D. It provides 266 MHz for main 
bus system. 
 BPLL uses XXTI as input to generate 22 MHz to 1.6 GHz. This PLL generates 1066 MHz clock to provide 
533 MHz for DRAM memory controller. 
 CPLL uses XXTI as input to generate 333 MHz. This PLL generates 333 MHz clock to provide 333 MHz for 
MFC, DISP1 and GSCLER. 
 EPLL uses XXTI as input to generate 22 MHz to 1.4 GHz. This PLL generates 192 MHz clock to Audio Sub-
System. 
 VPLL uses XXTI or SCLK_HDMI24M as input to generate 22 MHz to 1.4 GHz. This PLL generates 
54 MHz video clock, 300 MHz clock to DISP1 and GSCALER. 
 GPLL use XXTI as input to generate 22 MHz to 1.4 GHz. This PLL generates 533 MHz to G3D. 
 USB Host and Device PHY use XXTI to generate 30 MHz and 48 MHz. 
 HDMI PHY uses XXTI to generate 54 MHz. 
Clock controllers allow bypassing of PLLs for slow clock. Additionally, they can gate clocks in each block for power 
reduction. 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-6  
5.3 Clock Relationship 
Clocks have these relationships: 
 CPU_BLK clocks 
 freq. (ARMCLK) = freq. (MOUTCPU)/n, where n = 1 to 64 
 freq. (ACLK_CPUD) = freq. (ARMCLK)/n, where n = 1 to 8 
 freq. (ACLK_ACP) = freq. (ARMCLK)/n, where n = 1 to 8 
 freq. (PERIPHCLK) = freq. (ARMCLK)/n, where n = 1 to 8 
 freq. (ATCLK) = freq. (MOUTCPU)/n, where n = 1 to 8 
 freq. (PCLK_DBG) = freq. (ATCLK)/n, where n = 1 to 8 
 
 DMC_BLK clocks 
 freq. (MCLK_CDREX) = freq. (MOUTMCLK_CDREX2)/n, where n = 1 to 8 
 freq. (ACLK_CDREX) = freq. (MCLK_CDREX)/n, where n = 1 to 8 
 freq. (MCLK_DPHY) = freq. (MOUTMCLK_DPHY)/n, where n = 1 to 8  
 freq. (C2C_CLK) = freq. (MOUTC2C_CLK_400)/n, where n = 1 to 8  
 freq. (ACLK_C2C) = freq. (C2C_CLK)/n, where n = 1 to 8  
 freq. (ACLK_CORED) = freq. (MOUTMPLL)/n, where n = 1 to 8 
 freq. (ACLK_COREP) = freq. (ACLK_CORED)/n, where n = 1 to 8 
 freq. (ACLK_ACP) = freq. (FOUTMPLL)/n, where n = 1 to 8 
 freq. (PCLK_ACP) = freq. (ACLK_ACP)/n, where n = 1 to 8 
 freq. (EFCLK_SYSLFT) = freq. (FOUTMPLL)/n, where n = 1 to 8 
 
Caution: It should be guaranteed that the ratio between freq (MCLK_CDREX) and freq (ACLK_CDREX) is kept 
as 2 to 1 all the time. 
 LEX_BLK clocks 
 freq. (ACLK_DLEX) = freq. (ACLK_266)/n, where n = 1 to 8 
 freq. (ACLK_PLEX) = freq. (ACLK_DLEX)/n, where n = 1 to 8 
 
 R0X/R1X_BLK clocks  
 freq. (ACLK_DR0X) = freq. (ACLK_266)/n, where n = 1 to 8 
 freq. (ACLK_PR0X) = freq. (ACLK_DR0X)/n, where n = 1 to 8 
 freq. (ACLK_DR1X) = freq. (ACLK_266)/n, where n = 1 to 8 
 freq. (ACLK_PR1X) = freq. (ACLK_DR1X)/n, where n = 1 to 8 
 
  
						

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Exynos 5250_UM 5 Clock Controller 
 5-7  
 CMU_TOP clocks  
 freq. (ACLK_400_G3D) = freq. (MOUTACLK_400_G3D)/n, where n = 1 to 8  
 freq. (ACLK_400_IOP) = freq. (MOUTACLK_400_IOP)/n, where n = 1 to 8  
 freq. (ACLK_400_ISP) = freq. (MOUTACLK_400_ISP)/n, where n = 1 to 8 
 freq. (ACLK_333) = freq. (MOUTACLK_333)/n, where n = 1 to 8  
 freq. (ACLK_300_DISP1) = freq. (MOUTACLK_300_DISP1)/n, where n = 1 to 8  
 freq. (ACLK_300_GSCL) = freq. (MOUTACLK_300_GSCL)/n, where n = 1 to 8  
 freq. (ACLK_266) = freq. (SCLKMPLL_USER)/n, where n = 1 to 8  
 freq. (ACLK_266_GSCL) = freq. (ACLK_266)  
 freq. (ACLK_266_ISP) = freq. (ACLK_266)  
 freq. (ACLK_200) = freq. (MOUTACLK_200)/n, where n = 1 to 8  
 freq. (ACLK_200_DISP1) = freq. (ACLK_200)  
 freq. (ACLK_MIPI_HSI_TXBASE) = freq. (MOUTACLK_MIPI_HSI_TXBASE)/n, where n = 1 to 8  
 freq. (ACLK_166) = freq. (MOUTACLK_166)/n, where n = 1 to 8 
 freq. (ACLK_66_pre) = freq. (MOUTMPLL_USER)/n, where n = 1 to 8  
 freq. (ACLK_66) = freq. (ACLK_66_pre)/n, where n = 1 to 8 
 
 MAU_BLK clocks 
 freq. (RP_CLK) = freq. (MOUTASS)/n, where n = 1 to 16 
 freq. (BUS_CLK) = freq. (MOUTRP)/n, where n = 1 to 16 
 
NOTE: Clock names and clock tree diagram of MAUDIO_BLK are illustrated in Figure 34-3 of Chapter 34 Audio Subsystem. 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-8  
Values for high-performance operation: 
 freq. (ARMCLK) = 1.7 GHz 
 freq. (ACLK_CPUD) = 450 MHz, 500 MHz 
 freq. (PERIPHCLK) = 169 MHz, 125 MHz 
 freq. (ATCLK) = 200 MHz 
 freq. (PCLK_DBG) = 100 MHz 
 freq. (MCLK_CDREX) = 800 MHz, 667 MHz, 533 MHz, 400 MHz 
 freq. (ACLK_CDREX) = 400 MHz, 333 MHz, 266 MHz, 200 MHz 
 freq. (PCLK_CDREX) = 133 MHz 
 freq. (ACLK_ACP) = 266 MHz 
 freq. (PCLK_ACP) = 133 MHz 
 freq. (ACLK_DLEX) = 266 MHz 
 freq. (ACLK_PLEX) = 133 MHz 
 freq. (ACLK_DR0X/R1X) = 266 MHz 
 freq. (ACLK_DR1X/R1X) = 133 MHz 
 freq. (ACLK_400) = 250 MHz 
 freq. (ACLK_400_IOP) = 400 MHz 
 freq. (ACLK_400_ISP) = 400 MHz 
 freq. (ACLK_333) = 333 MHz 
 freq. (ACLK_300_DISP1) = 333 MHz 
 freq. (ACLK_300_GSCL) = 333 MHz 
 freq. (ACLK_266) = 266 MHz 
 freq. (ACLK_266_GSCL) = 266 MHz 
 freq. (ACLK_266_ISP) = 266 MHz 
 freq. (ACLK_200) = 200 MHz 
 freq. (ACLK_200_DISP1) = 200 MHz 
 freq. (ACLK_MIPI_HSI_TXBASE) = 200 MHz 
 freq. (ACLK_166) = 166 MHz 
 freq. (ACLK_66) = 66 MHz 
 
  
						

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Exynos 5250_UM 5 Clock Controller 
 5-9  
 PLL 
 APLL primarily drives CPU_BLK clocks. It can generate up to 1.7 GHz.  
 MPLL primarily drives DMC_BLK, LEX_BLK, R0X_BLK, R1X_BLK and TOP block clocks. It can generate 
up to 1.6 GHz. MPLL can also generate CPU_BLK clocks when APLL is blocked for locking during 
Dynamic Voltage Frequency Scaling (DVFS).  
 BPLL is primarily used to generate 1066 MHz, providing 533 MHz to DMC_BLK. 
 CPLL is primarily used to generate 333 MHz, providing 333 MHz to MFC_BLK. 
 EPLL is primarily used to generate audio clock. 
 GPLL is primarily used to generate 533 MHz, providing 533 MHz to G3D_BLK. 
 VPLL is primarily used to generate video system operating clock. It uses 54 MHz and 300 MHz clock to 
GSCALER_BLK and DISP1_BLK. 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-10  
5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL 
Table 5-2 lists the APLL, MPLL, BPLL, CPLL and GPLL PMS value. 
Table 5-2   APLL, MPLL, BPLL, CPLL and GPLL PMS Value 
FIN 
(MHz) 
Target FOUT 
(MHz) P M S AFC_ENB AFC FVCO 
(MHz) 
FOUT 
(MHz) 
24 200 3 100 2 0 0 800 200 
24 333 4 222 2 0 0 1332 333 
24 400 3 100 1 0 0 800 400 
24 533 12 533 1 0 0 1066 533 
24 600 4 200 1 0 0 1200 600 
24 667 7 389 1 0 0 1333.71429 666.857143 
24 800 3 100 0 0 0 800 800 
24 1000 3 125 0 0 0 1000 1000 
24 1066 12 533 0 0 0 1066 1066 
24 1200 3 150 0 0 0 1200 1200 
24 1400 3 175 0 0 0 1400 1400 
24 1600 3 200 0 0 0 1600 1600 
NOTE:  
1. The other PLL control inputs should be set as: 
 RESV1 = 0   RESV0 = 1 
 DCC_ENB = 1  EXTAFC = 0 
 LOCK_CON_IN = 3  LOCK_CON_OUT = 0 
 LOCK_CON_DLY = 8  AFC_ENB = 0 
2. Although there is an equation for choosing PMS values, we strongly recommend only the values in the above table. 
 If you have to use other values, please contact us. 
 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-11  
5.3.2 Recommended PLL PMS Value for EPLL 
Table 5-3 lists the EPLL PMS value. 
Table 5-3   EPLL PMS Value 
FIN (MHz) Target FOUT 
(MHz) P M S K FOUT (MHz) 
24 48.0000 2 64 4 0 48 
24 96.0000 2 64 3 0 96 
24 144.0000 2 96 3 0 114 
24 192.0000 2 64 2 0 192 
24 288.0000 2 96 2 0 288 
24 84.0000 2 112 4 0 84 
24 50.0000 2 67 4 43691 (  21845) 50 
24 80.0000 2 107 4 43691 (  21845) 80 
24 32.7680 3 131 5 4719 32.768 
24 49.1520 3 98 4 19923 49.152 
24 67.7376 2 90 4 20762 67.7376 
24 73.7280 2 98 4 19923 73.728 
24 45.1584 3 90 4 20762 45.1584 
NOTE:  
1. The other PLL control inputs should be set as: 
 DCC_ENB = 1 ICP_BOOST = 0 
 SSCG_EN = 0 (Disable dithered mode) 
 AFC_ENB = 0 EXTAFC = 0 
2. K value description Positive value (Negative value): 
 Positive values is that you should write to EPLLCON/VPLLCON register. 
 Negative value is that you can calculate PLL output frequency with it. 
3. Although there is an equation for choosing PMS values, we strongly recommend only the values in the above table. 
 If you have to use other values, please contact us. 
 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-12  
5.3.3 Recommended PLL PMS Value for VPLL 
Table 5-4 describes the VPLL PMS value. 
Table 5-4   VPLL PMS Value 
FIN 
(MHz) 
Target FOUT 
(MHz) P M S K MFR MRR SSCG_EN 
24 
54 2 72 4 0   0 
108 2 72 3 0   0 
74.25 2 99 4 0   0 
148.5 2 99 3 0   0 
222.75 2 74 2 16384   0 
371.25 2 62 1 57344 (  8192)   0 
445.5 2 74 1 16384   0 
74.176 2 99 4 59070 (  6466)   0 
148.352 2 99 3 59070 (  6466)   0 
222.528 3 111 2 17302   0 
370.879 2 62 1 53292 (  12244)   0 
445.055 3 111 1 17285   0 
519.231 3 130 1 52937 (  12599)   0 
27.027 2 72 5 4719   0 
27 2 72 5 0   0 
600 2 100 1 0   0 
300 2 100 2 0   0 
320 2 107 2 43691 (  21845)   0 
330 2 110 2 0   0 
333 2 111 2 0   0 
335 2 112 2 43691 (  21845)   0 
NOTE:  
1. The other PLL control inputs should be set as: 
 DCC_ENB = 1 
 ICP_BOOST = 0 
 AFC_ENB = 0 
 EXTAFC = 0 
2. Although there is an equation for choosing PMS values, we strongly recommend only the values in the above table. 
 If you have to use other values, please contact us. 
3. K value description Positive value (Negative value): 
 Positive values is that you should write to EPLLCON/VPLLCON register. 
 Negative value is that you can calculate PLL output frequency with it. 
  
						

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Exynos 5250_UM 5 Clock Controller 
 5-13  
5.4 Clock Generation 
Figure 5-2 through Figure 5-5 illustrate block diagram of the clock generation logic. An external crystal clock is 
connected to the oscillation amplifier. The PLL converts low input frequency to high-frequency clock that Exynos 
5250 requires. The clock generator block also includes a built-in logic to stabilize the clock frequency after each 
system reset, because clock takes time for stabilizing. 
Figure 5-2 through Figure 5-5 also illustrates two types of clock mux. Clock mux in grey color represents glitch-
free clock mux, which is free of glitches while clock selection is changed. Clock mux in white color represents non-
glitch-free clock mux, which can suffer from glitches when changing clock sources. Care must be taken in using 
each clock mux. For glitch-free mux, ensure to run all clock sources when clock selection is changed from one 
mux to other mux. If the clock sources are not run, clock changing process is not finished. It might result in 
unknown clock states. 
For non-glitch-free clock mux, there is a possibility to have a glitch when clock selection is changed. To prevent 
glitch signals, it is recommended to disable output of a non-glitch-free mux before trying to change clock sources. 
After clock changing is completed, you can re-enable output of the non-glitch-free clock mux so that no glitches 
will result from clock changes.  Clock source mask control registers with prefix CLK_SRC_MASK handle 
masking output of non-glitch free muxes. 
Clock dividers illustrated in Figure 5-2 through Figure 5-5 indicate possible dividing value in parentheses. During 
run-time, clock divider registers can change these dividing values. Some clock dividers may have only one 
dividing value and user is not allowed to change the dividing value. For such dividers, that is denoted as /2, there 
is no corresponding field in clock divider registers. 
 
  
						

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Exynos 5250_UM 5 Clock Controller 
 5-14  
Figure 5-2 and Figure 5-3 illustrate the Exynos 5250 clock generation circuit. (CPU, BUS, DRAM Clocks) 
 
    Figure 5-2   Exynos 5250 Clock Generation Circuit (CPU, BUS, DRAM Clocks) 1 CMU_CDREX
CMU_CORE
MUXMPLL
MOUTMPLL
0
1
DIVRSVD3_CORE(1~16)
MUXPWI
MOUTPWI
XXTIXusbXTISCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHYSCLKMPLLSCLKEPLLSCLKVPLL
SCLKMPLL
FOUTMPLL
DIVRSVD1_CORE(1~128)
DIVRSVD2_CORE(1~128)
DIVCORED(1~8)
DIVCOREP(1~8)
ACLK_COREP
ACLK_CORED
CMU_CPU
APLL(PLL3500)
0
1DIVARM(1~8) /1
0
1
XXTI
MUXAPLLMUXCPU
MOUTCPUFINPLLMOUTAPLL
DIVATB(1~8) /5
Clock stop request
When EAGLE(A15) 
reset/isolation 
DIVCOPY(1~8) /8
SCLK_HPMDIVHPM(1~8) /8DOUTCOPY
MOUTAPLL
FOUTAPLL
Voltage domain 
crossing
Paired inverters are 
added before/after 
the line
0
1
0
1
glitch-free
mux
normal
mux
synchronous 
clocks
ARM_CLK
PCLK_DBGDIVPCLK_DBG(1~8) /2
MOUTAPLL
SCLKMPLL
DIVCPUD(1~8) /2
ACLK_CPUD
0
1
DIVPERIPH(1~8) /8PERIPHCLK
HCLK_CSSYSCTMCLKTRACECLKATCLKEN
DIVACP(1~8) /8
OSCCLK
MUXHPM
MOUTHPM
DIVAPLL(1~8) /2SCLK_APLL
PCLKEN_DBG
ATCLKE4D : PCLKDBGCSSYS : ATCLK
E4D : PCLKENDBG → source clock = E4D : PCLKDBG
E4D : CLK
E4D : PERIPHCLKEN → source clock = E4D : CLK
CSSYS : PCLKDBGSECJTAG : PCLK
ASYNCAXIS_EAGLE_CBX : ACLK
DIVARM2(1~8) /1
OSCCLKRCLK_CDREXRCLK_DREX2
BPLL(PLL3500)DIV/2(fixed)0
1
MUXBPLL_FOUT
MOUT_BPLL_FOUT
0
1
MUXBPLL
SCLKBPLL
MPLL(PLL3500)DIV/2(fixed)0
1
MUXMPLL_FOUT
MOUT_MPLL_FOUT
0
1
1600
800
DIVMCLK_CDREX(1~8) (3)DIVPCLK_CDREX(1~8) (2)
PCLK_CDREX
MUXMCLK_CDREX
266133
0
1
DIVMCLK_CDREX2(1~8) (1)
DIVMCLK_DPHY(1~8) (1)
MCLK_DPHYMCLK_DPHY0MCLK_DPHY1
800
MUXMCLK_DPHY
MOUT_BPLL
MOUT_MCLK_CDREX
MOUT_MCLK_DPHY
DIVACLK_CDREX(1~8) (2)
DIVACLK_SFRTZASCP(1~8) (2)
ACLK_SFRTZASCP
200
400
800MCLK_CDREX
ACLK_CDREX
MCLK_DREX2
synchronous 
clocks
SCLKMPLL_LFT
MPLLFOUT_RGT
MPLLFOUT_RGT
800
800
CMU_ACP
PCLK_ACPDIVPCLK_ACP(1~8) (2)
ACLK_ACP
synchronous 
clocks
DIVACLK_ACP(1~8) (3)
SCLKMPLL_LFT
DIVACLK_SYSLFT(1~8)  (2)
DIVPCLK_SYSLFT(1~8)  (2)
PCLK_SYSLFT
ACLK_SYSLFT
synchronous 
clocks
DIVEFCLK_SYSLFT(1~16) (4)
EFCLK_SYSLFT
266
133
400
200
200
DIVC2C_CLK_400(1~8)
DIVACLK_C2C_200(1~8)
ACLK_C2C
C2C_CLK
DIVACLK_R1BX(1~8)
ACLK_R1BX
800
800400
200
400
266
133
MPLL SFR is in CMU_CORE
800
1000MHz
500MHz
1000MHz
500MHz
not used
not used
200MHz
100MHz
FOUTBPLL
not used
not used
not used
not used