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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-165  
5.9.1.158 CLK_GATE_IP_DISP1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0928, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:10] –=Reserved=0x3F_FFFc=
CLK_SMMUTVu=x9]=RW=
Gating all=Clocks for=SMMUTVu=
0 = Masks=
1 = Passes=
0x1=
CLh=
_SMMUFIMD1u=x8]=RW=
Gating all=Clocks for=SMMUFIMD1X=
0 = Masks=
1 = Passes=
0x1=
CLK_ASYNCTVX=[7]=RW=
Gating all=Clocks for ASYNCTVX=
0: Masks=
1: Passes=
0x1=
CLK_HDMI=xS]=RW=
Gating all=Clocks for=HDMI=
0 = Masks=
1 = Passes=
0x1=
CLK_MIXEo=x5]=RW=
Gating all=Clocks for=MIXEo=
0 = Masks=
1 = Passes=
0x1=
CLK_DP1=[4]=RW=
Gating all=Clocks for=DP1=
0 = Masks=
1 = Passes=
0x1=
CLK_DSIM1=[3]=RW=
Gating all=Clocks for DSIM1=
0 = Masks=
1 = Passes=
0x1=
oSVa=[2]=–=Reserved=0x1=
CLK_MIE1=[1]=RW=
Gating all=Clocks for MIE1=
0 = Masks=
1 = Passes=
0x1=
CLK_FIMD1=[0]=RW=
Gating all=Clocks for FIMD1=
0 = Masks=
1 = Passes=
0x1=
=
=
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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-166  
5.9.1.159 CLK_GATE_IP_MFC 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x092C, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:3] –=Reserved=0x1FFF_FFFc=
CLK_SMMUMFCR=[2]=RW=
Gating all=Clocks for=SMMUMFCR=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUMFCL=[1]=RW=
Gating all=Clocks for=SMMUMFCL=
0 = Masks=
1 = Passes=
0x1=
CLK_MFC=[0]=RW=
Gating all=Clocks for=MFC=
0 = Masks=
1 = Passes=
0x1=
=
5.9.1.160 CLK_GATE_IP_G3D 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0930, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x7FFF_FFFc=
CLK_G3a=[0]=RW=
Gating all=Clocks for=G3a=
0 = Masks=
1 = Passes=
0x1=
=
=
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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-167  
5.9.1.161 CLK_GATE_IP_GEN 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0934, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:10] –=Reserved=0x3F_FFFc=
CLh=
_SMMUMDMA1=x9]=RW=
Gating all=Clocks for=SMMUMDMA1=
0 = Masks=
1 = Passes=
0x1=
RSVD=x8]=–=Reserved=0x1=
CLK_SMMUJPEG=x7]=RW=
Gating all=Clocks for=SMMUJPEG=
0 = Masks=
1 = Passes=
0x1=
CLh=
_SMMUROTATOo=xS]=RW=
Gating all=Clocks for=SMMUROTATOo=
0 = Masks=
1 = Passes=
0x1=
RSVD=x5]=–=Reserved=0x1=
CLK_MDMA1=x4]=RW=
Gating all=Clocks for=MDMA1=
0 = Masks=
1 = Passes=
0x1=
RSVD=x3]=–=Reserved=0x1=
CLK_JPEG=[2]=RW=
Gating all=Clocks for=JPEG=
0 = Masks=
1 = Passes=
0x1=
CLK_ROTATOo=[1]=RW=
Gating all=Clocks for=ROTATOo=
0 = Masks=
1 = Passes=
0x1=
RSVD=x0]=–=Reserved=0x1=
=
=
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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-168  
5.9.1.162 CLK_GATE_IP_FSYS 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0944, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:31] –=Reserved=0x1FFF=
CLK_WDT_IOm=x30]=RW=
Gating all=Clocks for=WDT_IOm=
0 = Masks=
1 = Passes=
0x1=
RSVD=x29:27]=–=Reserved=0x7=
CLh_SMMUMCU=
_IOP=x26]=RW=
Gating all=Clocks for=SMMUMCU_ISm=
0 = Masks=
1 = Passes=
0x1=
CLK_SATA_PHY=
_I2C=x25]=RW=
Gating all=Clocks for=SATA PHY I2C=
0 = Masks=
1 = Passes=
0x1=
CLK_SATA_PHY=
_CTRi=x24]=RW=
Gating all=Clocks for=SATA PHY CTRi=
0 = Masks=
1 = Passes=
0x1=
CLK_MCUCTL=
_IOP=x23]=RW=
Gating all=Clocks for=MCUCTL_IOP=
0 = Masks=
1 = Passes=
0x1=
CLK_NFCON=x22]=RW=Set 0 to=reduce power for deprecated function=0x1=
RSVD=x21:20]=–=Reserved=0x3=
CLK_USBDRD30=x19]=RW=
Gating all=Clocks for=USBDRD30=
0 = Masks=
1 = Passes=
0x1=
CLK_USBHOST20=[18]=RW=
Gating all=Clocks for=USBHOST20=
0== Masks=
1 = Passes=
0x1=
CLK_SROMC=[17]=RW=
Gating all=Clocks for=SROMC=
0 = Masks=
1 = Passes=
0x1=
RSVD=x16]=–=Reserved=0x1=
CLK_SDMMC3=[15]=RW=
Gating all=Clocks for=SDMMC3=
0 = Masks=
1 = Passes=
0x1=
CLK_SDMMC2=[14]=RW=
Gating all=Clocks for=SDMMC2=
0 = Masks=
1 = Passes=
0x1=
CLK_SDMMC1=[13]=RW=
Gating all=Clocks for=SDMMC1=
0 = Masks=
1 = Passes=
0x1=
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Exynos 5250_UM 5 Clock Controller 
 5-169  
Name Bit Type Description Reset Value 
CLK_SDMMC0 [12] RW 
Gating all clocks for SDMMC0 
0 = Masks 
1 = Passes 
0x1 
CLK_SMMURTIC [11] RW 
Gating all Clocks for SMMURTIC 
0 = Masks 
1 = Passes 
0x1 
RSVD [10] – Reserved 0x1 
CLK_RTIC [9] RW 
Gating all Clocks for RTIC 
0 = Masks 
1 = Passes 
0x1 
CLK_MIPI_HSI [8] RW 
Gating all Clocks for MIPI_HSI 
0 = Masks 
1 = Passes 
0x1 
CLK_USBOTG [7] RW 
Gating all Clocks for USBOTG 
0 = Masks 
1 = Passes 
0x1 
CLK_SATA [6] RW 
Gating all Clocks for SATA Link 
0 = Masks 
1 = Passes 
0x1 
RSVD [5:3] – Reserved 0x7 
CLK_PDMA1 [2] RW 
Gating all Clocks for PDMA1 
0 = Masks 
1 = Passes 
0x1 
CLK_PDMA0 [1] RW 
Gating all Clocks for PDMA0 
0 = Masks 
1 = Passes 
0x1 
CLK_MCU_IOP [0] RW 
Gating all Clocks for MCU_IOP 
0 = Masks 
1 = Passes 
0x1
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Exynos 5250_UM 5 Clock Controller 
 5-170  
5.9.1.163 CLK_GATE_IP_PERIC 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0950, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
CLK_HS-I2C3 [31] RW 
Gating all Clocks for HS-I2C3 
0 = Masks 
1 = Passes 
0x1 
CLK_HS-I2C2 [30] RW 
Gating all Clocks for HS-I2C2 
0 = Masks 
1 = Passes 
0x1 
CLK_HS-I2C1 [29] RW 
Gating all Clocks for HS-I2C1 
0 = Masks 
1 = Passes 
0x1 
CLK_HS-I2C0 [28] RW 
Gating all Clocks for HS-I2C0 
0 = Masks 
1 = Passes 
0x1 
CLK_AC97 [27] RW 
Gating all Clocks for AC97 
0 = Masks 
1 = Passes 
0x1 
CLK_SPDIF [26] RW 
Gating all Clocks for SPDIF 
0 = Masks 
1 = Passes 
0x1 
RSVD [25] –=Reserved=0x1=
CLK_PWM=[24]=RW=
Gating all=Clocks for PWM=
0 = Masks=
1 = Passes=
0x1=
CLK_PCM2=[23]=RW=
Gating all Clocks for PCM2=
0 ==Masks=
1 = Passes=
0x1=
CLK_PCM1=[22]=RW=
Gating all Clocks for PCM1=
0 = Masks=
1 = Passes=
0x1=
CLK_I2S2=[21]=RW=
Gating all Clocks for I2S2=
0 = Masks=
1 = Passes=
0x1=
CLK_I2S1=[20]=RW=
Gating all=Clocks for I2S1=
0 = Masks=
1 = Passes=
0x1=
RSVD=[19]=–=Reserved=0x1=
CLK_SPI2=[18]=RW=
Gating all Clocks for SPI2=
0 = Masks=
1 = Passes=
0x1=
CLK_SPI1=[17]=RW=Gating all Clocks for SPI1=0x1=
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Exynos 5250_UM 5 Clock Controller 
 5-171  
Name Bit Type Description Reset Value 
0 = Masks 
1 = Passes 
CLK_SPI0 [16] RW 
Gating all Clocks for SPI0 
0 = Masks 
1 = Passes 
0x1 
CLK_ADC [15] RW 
Gating all Clocks for ADC 
0 = Masks 
1 = Passes 
0x1 
CLK_I2CHDMI [14] RW 
Gating all Clocks for I2CHDMI 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C7 [13] RW 
Gating all Clocks for I2C7 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C6 [12] RW 
Gating all Clocks for I2C6 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C5 [11] RW 
Gating all Clocks for I2C5 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C4 [10] RW 
Gating all Clocks for I2C4 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C3 [9] RW 
Gating all Clocks for I2C3 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C2 [8] RW 
Gating all Clocks for I2C2 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C1 [7] RW 
Gating all Clocks for I2C1 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C0 [6] RW 
Gating all Clocks for I2C0 
0 = Masks 
1 = Passes 
0x1 
RSVD [5:4] – Reserved 0x1 
CLK_UART3 [3] RW 
Gating all Clocks for UART3 
0 = Masks 
1 = Passes 
0x1 
CLK_UART2 [2] RW 
Gating all Clocks for UART2 
0 = Masks 
1 = Passes 
0x1 
CLK_UART1 [1] RW Gating all Clocks for UART1 0x1
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Exynos 5250_UM 5 Clock Controller 
 5-172  
Name Bit Type Description Reset Value 
0 = Masks 
1 = Passes 
CLK_UART0 [0] RW 
Gating all Clocks for UART0 
0 = Masks 
1 = Passes 
0x1
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Exynos 5250_UM 5 Clock Controller 
 5-173  
5.9.1.164 CLK_GATE_IP_PERIS 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0960, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x3FFc=
CLK_MONOCNT=x24]=RW=
Gating all Clocks for Monotonic Counter=
0 = Masks=
1 = Passes=
0x1=
CLK_PKEY1=x23]=RW=
Gating all Clocks for Provision key 1=
0 = Masks=
1 = Passes=
0x1=
CLK_PKEY0=x22]=RW=
Gating all Clocks for Provision key 0=
0 = Masks=
1 = Passes=
0x1=
CLK_TMU_APBIc=x21]=RW=
Gating all=Clocks for=TMU_APBIc=
0 = Masks=
1 = Passes=
0x1=
CLK_RTC=x20]=RW=
Gating all=Clocks for=RTC=
0 = Masks=
1 = Passes=
0x1=
CLK_WDT=[19]=RW=
Gating all=Clocks for=WDT=
0 = Masks=
1 = Passes=
0x1=
CLK_pT=[18]=RW=
Gating all=Clocks for=pT=
0 = Masks=
1 = Passes=
0x1=
CLK_SECKEY=
_APBIF=[17]=RW=
Gating all=Clocks for=SECKEY_APBIF=
0 = Masks=
1 = Passes=
0x1=
CLK_HDMI_CEC=[16]=RW=
Gating all=Clocks for=HDMI_CEC=
0 = Masks=
1 = Passes=
0x1=
CLK_TZPC9=[15]=RW=
Gating all=Clocks for=TZPC9=
0 = Masks=
1 = Passes=
0x1=
CLK_TZPC8=[14]=RW=
Gating all=Clocks for=TZPC8=
0 = Masks=
1 = Passes=
0x1=
CLK_TZPC7=[13]=RW=
Gating all=Clocks for=TZPC7=
0 = Masks=
1 = Passes=
0x1=
CLK_TZPCS=[12]=RW=Gating all=Clocks for=TZPCS=
0 = Masks=0x1=
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Exynos 5250_UM 5 Clock Controller 
 5-174  
Name Bit Type Description Reset Value 
1 = Passes 
CLK_TZPC5 [11] RW 
Gating all clocks for TZPC5 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC4 [10] RW 
Gating all Clocks for TZPC4 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC3 [9] RW 
Gating all Clocks for TZPC3 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC2 [8] RW 
Gating all Clocks for TZPC2 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC1 [7] RW 
Gating all Clocks for TZPC1 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC0 [6] RW 
Gating all Clocks for TZPC0 
0 = Masks 
1 = Passes 
0x1 
CLK_CMU 
_MEMPART [5] RW 
Gating all Clocks for CMU_MEMPART 
(CMU_CDREX) 
0 = Masks 
1 = Passes 
0x1 
CLK_CMU 
_COREPART [4] RW 
Gating all Clocks for CMU_COREPART 
(CMU_CPU, CMU_CORE, CMU_ACP, CMU_ISP) 
0 = Masks 
1 = Passes 
0x1 
CLK_CMU 
_TOPPART [3] RW 
Gating all Clocks for CMU_TOPPART (CMU_TOP, 
CMU_LEX, CMU_R0X, CMU_R1X) 
0 = Masks 
1 = Passes 
0x1 
CLK_PMU_APBIF [2] RW 
Gating all Clocks for PMU_APBIF 
0 = Masks 
1 = Passes 
0x1 
CLK_SYSREG [1] RW 
Gating all Clocks for SYSREG 
0 = Masks 
1 = Passes 
0x1 
CLK_CHIPID 
_APBIF [0] RW 
Gating all Clocks for CHIPID_APBIF 
0 = Masks 
1 = Passes 
0x1
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